DE102015007709B4 - Invalidationsdatenbereich für einen Cache - Google Patents

Invalidationsdatenbereich für einen Cache Download PDF

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Publication number
DE102015007709B4
DE102015007709B4 DE102015007709.0A DE102015007709A DE102015007709B4 DE 102015007709 B4 DE102015007709 B4 DE 102015007709B4 DE 102015007709 A DE102015007709 A DE 102015007709A DE 102015007709 B4 DE102015007709 B4 DE 102015007709B4
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journal
cache
block
invalidation
data
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DE102015007709.0A
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German (de)
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DE102015007709A1 (de
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Pulkit Misra
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Western Digital Technologies Inc
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Western Digital Technologies Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1435—Saving, restoring, recovering or retrying at system level using file system or storage system metadata
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1471—Saving, restoring, recovering or retrying involving logging of persistent data for recovery
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Library & Information Science (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
DE102015007709.0A 2014-06-26 2015-06-17 Invalidationsdatenbereich für einen Cache Active DE102015007709B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/316,256 2014-06-26
US14/316,256 US9501418B2 (en) 2014-06-26 2014-06-26 Invalidation data area for cache

Publications (2)

Publication Number Publication Date
DE102015007709A1 DE102015007709A1 (de) 2015-12-31
DE102015007709B4 true DE102015007709B4 (de) 2025-05-22

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Country Status (5)

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US (4) US9501418B2 (enExample)
CN (1) CN105302744B (enExample)
DE (1) DE102015007709B4 (enExample)
FR (1) FR3023030B1 (enExample)
GB (3) GB2546634B (enExample)

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US9501418B2 (en) 2014-06-26 2016-11-22 HGST Netherlands B.V. Invalidation data area for cache
US11061876B2 (en) * 2016-11-15 2021-07-13 Sap Se Fast aggregation on compressed data
US10642796B2 (en) * 2017-07-18 2020-05-05 International Business Machines Corporation File metadata verification in a distributed file system
CN109284066B (zh) * 2017-07-19 2022-09-30 阿里巴巴集团控股有限公司 一种数据处理方法、装置、设备及系统
JP6731553B2 (ja) * 2017-07-20 2020-07-29 株式会社日立製作所 分散ストレージシステム及び分散ストレージ制御方法
US10210086B1 (en) 2017-08-16 2019-02-19 International Business Machines Corporation Fast cache demotions in storage controllers with metadata
US10877890B2 (en) * 2018-06-01 2020-12-29 Intel Corporation Providing dead-block prediction for determining whether to cache data in cache devices
KR102835938B1 (ko) 2019-07-30 2025-07-18 에스케이하이닉스 주식회사 데이터 저장 장치, 데이터 처리 시스템 및 데이터 저장 장치의 동작 방법
KR102835515B1 (ko) * 2019-04-09 2025-07-17 에스케이하이닉스 주식회사 메모리 시스템 및 그것의 동작방법
KR20210011201A (ko) 2019-07-22 2021-02-01 에스케이하이닉스 주식회사 메모리 시스템 및 그의 온도 조절 방법
US11237973B2 (en) 2019-04-09 2022-02-01 SK Hynix Inc. Memory system for utilizing a memory included in an external device
KR20210011216A (ko) 2019-07-22 2021-02-01 에스케이하이닉스 주식회사 메모리 시스템의 메타 데이터 관리 방법 및 장치
KR102784548B1 (ko) 2019-05-15 2025-03-21 에스케이하이닉스 주식회사 메모리 시스템에서 맵 데이터를 전송하는 방법 및 장치
KR102803702B1 (ko) 2019-07-22 2025-05-09 에스케이하이닉스 주식회사 메모리 시스템의 액세스 동작 방법 및 장치
CN112685431B (zh) * 2020-12-29 2024-05-17 京东科技控股股份有限公司 异步缓存方法、装置、系统、电子设备和存储介质
KR102497130B1 (ko) 2021-11-11 2023-02-07 삼성전자주식회사 스토리지 장치 및 그것의 동작 방법
US12197340B2 (en) * 2022-11-01 2025-01-14 Arm Limited Apparatus and method for cache invalidation
CN120233942A (zh) * 2023-12-28 2025-07-01 华为云计算技术有限公司 处理数据的方法、处理系统及计算机可读存储介质

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US20140047193A1 (en) 2012-08-07 2014-02-13 Dell Products L.P. System and Method for Utilizing Non-Volatile Memory in a Cache

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Publication number Publication date
US9501418B2 (en) 2016-11-22
GB2529035B (en) 2017-03-15
US20150378925A1 (en) 2015-12-31
US20170068623A1 (en) 2017-03-09
US20210042235A1 (en) 2021-02-11
GB2546634A (en) 2017-07-26
US10445242B2 (en) 2019-10-15
GB201509965D0 (en) 2015-07-22
GB2546634B (en) 2017-11-22
CN105302744A (zh) 2016-02-03
GB2540681B (en) 2017-06-14
DE102015007709A1 (de) 2015-12-31
GB2540681A (en) 2017-01-25
FR3023030B1 (fr) 2019-10-18
US11372771B2 (en) 2022-06-28
CN105302744B (zh) 2019-01-01
GB201701188D0 (en) 2017-03-08
FR3023030A1 (enExample) 2016-01-01
US10810128B2 (en) 2020-10-20
GB2529035A (en) 2016-02-10
US20190317900A1 (en) 2019-10-17

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