DE102014221364A1 - Microelectronic component arrangement with a plurality of substrates and corresponding production method - Google Patents

Abstract

The invention provides a microelectronic component arrangement with a plurality of substrates and a corresponding production method. The microelectronic component arrangement comprises a first substrate (C1); a second substrate (C2), wherein the first substrate (C1) and the second substrate (C2) are interconnected in a stacked configuration. The first substrate (C1) and / or the second substrate (C2) has a recess (A), within which a third substrate (C3) is at least partially accommodated.

Description

The present invention relates to a microelectronic component arrangement with a plurality of substrates and to a corresponding production method.

State of the art

Although applicable to any micromechanical device arrangements, the present invention and its underlying problem will be explained with reference to MEMS substrate arrangements with silicon-based chips.

From the DE 10 2010 006 132 A1 is a miniaturized electrical device with a stack of a MEMS substrate and an ASIC substrate known, wherein the MEMS substrate and the ASIC substrate are stacked in a stacked construction and a gap between the MEMS substrate and the ASIC substrate present is.

Such three-dimensionally integrated microelectronic components require through contacts through all substrate layers or use interposer substrates with through contacts, which cause additional costs, increase the overall height and usually increase the lateral dimensions. Through contacts are always very expensive. Also very expensive is the bonding of the substrates of individual components. By contrast, the bonding of substrates with a large number of components (wafer level bonding) is much more favorable, which is possible with the same lateral substrate size on two or more of the substrate planes of a single component. Moreover, by simply stacking the substrates, the devices become relatively high, which can limit the flexibility in placing the devices.

6 FIG. 12 is a schematic vertical cross-sectional view for explaining an exemplary microelectronic component array having a plurality of substrates for explaining the problem underlying the present invention. FIG.

In 6 T denotes a component carrier to which a substrate stack consisting of a first substrate C10 and a second substrate C20 is bonded by means of bonding connections L1, L2.

The first substrate C10 and the second substrate C20 are connected to each other by means of bonding connections L5, L6. The first substrate C10 is, for example, an ASIC chip substrate, and the second substrate C20 is, for example, a MEMS sensor substrate which has MEMS structures M10, M20.

Between the bonding connections L1, L2, a third substrate C30 is suspended on the side of the first substrate C10 facing the component carrier T by means of bonding connections L3, L4. Such a suspension brings a critical tolerance KT between the bonds L1, L2 and the third substrate C30 with it. In addition, they must have a certain height so that the third substrate C30 does not touch the component carrier T.

Disclosure of the invention

The present invention provides a microelectronic component arrangement having a plurality of substrates according to claim 1 and a corresponding production method according to claim 14.

Preferred developments are the subject of the respective subclaims.

Advantages of the invention

The present invention makes it possible to provide a low cost and compact stacking structure for microelectronic devices, allowing for partial wafer level bonding.

In particular, it is possible to dispense with plated-through holes in the third substrate, which is accommodated at least partially in a recess of the first and / or second substrate. Thus, in the simplest case, a wafer level bonding between the first and second substrate is possible, which reduces the manufacturing cost. It can be z. B. apply a solid-liquid interdiffusion bonding process in which a resulting higher melting intermetallic compound is formed, which does not melt again in subsequent bonding steps. By multiple use of the same bonding metallization system, the manufacturing costs can also be reduced.

The idea underlying the present invention is to at least partially accommodate a smaller substrate in a recess of a larger substrate.

With the same lateral dimensions of the first substrate and the second substrate, the more cost-effective wafer-wafer bonding method can be used with the same wafer size. By saving space, conventional solder bumps can be replaced by Cu-Studbumps to save area.

In particular, there is a height saving of the bonds for the connection with a Component carrier when a hung according to the prior art above the component carrier kangaroo chip is housed in a recess in the first chip, whereby the overall height can be significantly reduced.

According to a preferred development, the first substrate has the recess.

According to a further preferred refinement, the cutout is located on the side of the first substrate facing the second substrate, wherein the third substrate is bonded to the second substrate above the cutout. Contacting the third substrate via the recess-free substrate has the advantage that simple conductor tracks can be realized on a planar surface. However, it is also possible to make the contacting of the third substrate in the recess, wherein the substrate material and the contact layer must be equally withdrawn.

According to a further preferred development, the recess is located on the side of the first substrate facing the second substrate, the third substrate being bonded to the first substrate within the recess.

According to a further preferred development, the recess is located on the side of the first substrate facing away from the second substrate, wherein the third substrate is bonded to the first substrate within the recess.

According to a further preferred development, the second substrate has the recess.

According to a further preferred refinement, the cutout is located on the side of the second substrate facing the first substrate, wherein the third substrate is bonded to the first substrate below the cutout.

According to a further preferred development, the recess is located on the side of the second substrate facing the first substrate, wherein the third substrate is bonded to the second substrate within the recess.

According to a further preferred development, the first substrate is bonded to a component carrier.

According to a further preferred development, the third substrate is completely accommodated in the recess. Thus, a particularly compact arrangement can be achieved.

According to a further preferred development, a fourth substrate is bonded to the side of the first substrate facing away from the second substrate.

According to a further preferred development, the second substrate is a MEMS sensor substrate. In many cases, MEMS structures are protected from external influences by capping. A recess can therefore be structured very well into this capping.

According to a further preferred development, the first substrate has an integrated circuit arrangement. Alternatively, the recess can also be etched into a side of another substrate, for example an ASIC substrate, which has no circuit arrangement.

Brief description of the drawings

Further features and advantages of the present invention will be explained below with reference to embodiments with reference to the figures.

Show it:

1 12 is a schematic vertical cross-sectional view for explaining a microelectronic component array having a plurality of substrates and a corresponding manufacturing method according to a first embodiment of the present invention;

2 12 is a schematic vertical cross-sectional view for explaining a microelectronic component array having a plurality of substrates and a corresponding manufacturing method according to a second embodiment of the present invention;

3 12 is a schematic vertical cross-sectional view for explaining a microelectronic component array having a plurality of substrates and a corresponding manufacturing method according to a third embodiment of the present invention;

4 12 is a schematic vertical cross-sectional view for explaining a microelectronic component array having a plurality of substrates and a corresponding manufacturing method according to a fourth embodiment of the present invention;

5 a schematic vertical cross-sectional view for explaining a microelectronic component array having a plurality of substrates and a corresponding one Manufacturing method according to a fifth embodiment of the present invention; and

6 a schematic vertical cross-sectional view for explaining an exemplary microelectronic component array having a plurality of substrates for explaining the problem underlying the present invention.

Embodiments of the invention

In the figures, like reference numerals designate the same or functionally identical elements.

1 shows a schematic vertical cross-sectional view for explaining a microelectronic component assembly having a plurality of substrates and a corresponding manufacturing method according to a first embodiment of the present invention.

In 1 Reference symbol C1 denotes a first substrate, for example an ASIC chip substrate, with plated-through holes DK11, DK12. On the upper side of the first substrate C1 is an integrated circuit arrangement SE.

A second substrate C2, for example a MEMS sensor chip substrate, is bonded to the integrated circuit arrangement SE of the first substrate C1 by means of bonding connections L5, L8. The second substrate C2 has MEMS sensor structures M1, M2. A through-connection DK2 in the second substrate C2 connects, by way of example, the MEMS sensor structures M1, M2 with the bonding connection L8.

On the side facing the first substrate C1, the second substrate C2 has a recess A. Within the recess A is a third substrate C3, for example, also an ASIC chip substrate accommodated, which is bonded below the recess A to the integrated circuit arrangement SE of the first substrate by means of bonds L6, L7. The third substrate C3, which has smaller lateral dimensions than the second substrate C2, is bonded by means of bonding connections L6, L7 to the integrated circuit arrangement SE of the first substrate C1. The first substrate C1 in the present case has the same lateral dimensions as the second substrate C2.

The plated-through holes DK11, DK12 connect the circuit plane SE of the first substrate C1 with bonding connections L1, L2 on the side of the first substrate C1 opposite the third substrate C3. By means of these bond connections L1, L2, the first substrate can be connected to a component carrier T.

Between the bonding connections L1, L2 on the side of the first substrate C1 opposite the third substrate C3, a fourth substrate C4, for example likewise an ASIC chip substrate, is bonded to the first substrate C1 in "kangaroo fashion" by means of bonding connections L3, L4.

In order to achieve a further reduction in height of the component stack formed in this way, the fourth substrate C4 could likewise be accommodated completely in a further recess in the first substrate C1 opposite the third substrate C3. This would mean that the thickness of the bonding connections L1, L2 could be reduced (cf. 5 below).

2 FIG. 12 is a schematic vertical cross-sectional view for explaining a microelectronic component array having a plurality of substrates and a corresponding manufacturing method according to a second embodiment of the present invention. FIG.

In 2 reference numeral C1 'denotes a modified first substrate which has an integrated circuit arrangement SE' which can be connected to a component carrier T by means of the bonding connections L1, L2. The attachment of the fourth substrate C4 by means of the bonding connections L3, L4 is analogous to the first embodiment.

In the second embodiment, the modified first substrate C1 'has a recess A' within which the third substrate C3 is completely accommodated.

Above the recess A ', the third substrate C3 is connected by means of bonding connections L6, L7 to the modified second substrate C2', which in this embodiment has no recess.

If, in this embodiment, connections of the third substrate C3 with the circuit arrangement on the first substrate are desired, these would be via plated-through holes DK11, DK12 through the first substrate or corresponding to the (not shown) printed conductors on the third substrate C3 side facing the modified second To realize substrate C2 '.

3 FIG. 12 is a schematic vertical cross-sectional view for explaining a microelectronic component array having a plurality of substrates and a corresponding manufacturing method according to a third embodiment of the present invention. FIG.

In 3 reference numeral C1 '' denotes a comparison with the first embodiment and second Embodiment modified first substrate, which has a recess A ', wherein the third substrate C3 is completely housed in the recess A' and is bonded therein to the first substrate C1 '' by means of the bonds L6 ', L7'. Below the bonding connections L6 ', L7', the modified first substrate C1 "has plated-through holes DK13, DK14 which connect the third substrate C3 to the integrated circuit arrangement SE", which can be connected to the component carrier T via the bonding connections L1, L2 , The suspension of the fourth substrate C4 via the bonds L3, L4 is analogous to the first and second embodiments described above.

As in the first and second embodiments, a second substrate C2 "is bonded to the modified first substrate C1" by means of the bonds L5, L8. Also in this third embodiment, the modified second substrate C2 "has no recess.

4 FIG. 12 is a schematic vertical cross-sectional view for explaining a microelectronic component array having a plurality of substrates and a corresponding manufacturing method according to a fourth embodiment of the present invention. FIG.

In the fourth embodiment, the modified first substrate C1 '' 'has no recess as in the first embodiment and can be connected to the component carrier T via the bonding connections L1, L2. The suspension of the fourth substrate C4 via the bonds L3, L4 is analogous to the first embodiment.

The modified second substrate C2 '' 'is likewise provided with a recess A as in the first embodiment, but here the third substrate C3 is bonded to the second substrate C2' 'within the recess A by means of bonding connections L6' ', L7' ' ,

The connection of the first substrate C1 "to the second substrate C2 '" takes place, as in the first embodiment, by means of the bonding connections L5, L8.

5 FIG. 12 is a schematic vertical cross-sectional view for explaining a microelectronic component array having a plurality of substrates and a corresponding manufacturing method according to a fifth embodiment of the present invention. FIG.

In the fifth embodiment, reference character C1 "" designates a modified first substrate, again an ASIC chip substrate, which has a recess A "on the side facing the component carrier T. The third substrate C3 is here by means of bonds L3 ', L4' so within the recess A '' on the first substrate C1 '' '' mounted so that it is completely housed within the recess A ''. ST1, ST2 denote Cu studbumps, which can be realized as particularly flat bond connections.

C2 "" is a modified second substrate, again a MEMS sensor substrate, which has MEMS structures M1 ', M2'. It is bonded to the first substrate C1 "" by means of the bonds L5, L8.

Although the present invention has been described in terms of preferred embodiments, it is not limited thereto. In particular, the materials and topologies mentioned are only examples and not limited to the illustrated examples.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• DE 102010006132 A1 [0003]

Claims (14)

 A microelectronic component array comprising a plurality of substrates, comprising: a first substrate (C1; C1 '; C1' '; C1' ''; C1 '' ''); a second substrate (C2; C2 '; C2' '; C2' ''; C2 '' ''), wherein the first substrate (C1; C1 '; C1' '; C1' ''; C1 '' '') and the second substrate (C2; C2 '; C2' '; C2' ''; C2 '' '') are interconnected in a stacked configuration; and wherein the first substrate (C1; C1 '; C1' '; C1' ''; C1 '' '') and / or the second substrate (C2; C2 '; C2' '; C2' ''; C2 '' ' ') has a recess (A; A'; A ''), within which a third substrate (C3) is at least partially accommodated. A microelectronic component device according to claim 1, wherein the first substrate (C1 '; C1' '; C1' '' ') has the recess (A'; A '').  Microelectronic component arrangement according to claim 2, wherein the recess (A ') is located on the side of the first substrate (C1') facing the second substrate (C2 ') and the third substrate (C3) is located above the recess (A') on the second Substrate (C2 ') is bonded.  The microelectronic component arrangement according to claim 2, wherein the recess (A ') is located on the side of the first substrate (C1' ') facing the second substrate (C2'), and the third substrate (C3) is located inside the recess (A ') on the first substrate (C1 ") is bonded.  A microelectronic component arrangement according to claim 2, wherein the recess (A '') is located on the side of the first substrate (C1 '' ') remote from the second substrate (C2' '' ') and the third substrate (C3) within the recess (A ") is bonded to the first substrate (C1" ").  A microelectronic component arrangement according to claim 1, wherein the second substrate (C2; C2 '' ') has the recess (A).  Microelectronic component arrangement according to claim 6, wherein the recess (A) is located on the side of the second substrate (C2) facing the first substrate (C1), and the third substrate (C3) is located below the recess (A) on the first substrate (C1). is bonded.  A microelectronic component arrangement according to claim 6, wherein the recess (A) is located on the side of the second substrate (C2 '' ') facing the first substrate (C1' ''), and the third substrate (C3) is located within the recess (A) the second substrate (C2 '' ') is bonded.  The microelectronic component arrangement according to one of the preceding claims, wherein the first substrate (C1; C1 '; C1' '; C1' ''; C1 '' '') can be connected to a component carrier (T).  Microelectronic component arrangement according to one of the preceding claims, wherein the third substrate (C3) is completely accommodated in the recess (A; A '; A' ').  A microelectronic component arrangement according to one of the preceding claims, wherein a fourth substrate (C4) faces the side of the first substrate (C1, C1 ', C2' ', C2' ', C2' '', C2 '' '') facing away from the second substrate (C1; '; C1' '; C1' ''; C1 '' '') is bonded.  A microelectronic component arrangement according to one of the preceding claims, wherein the second substrate (C2; C2 '; C2' '; C2' ''; C2 '' '') is a MEMS sensor substrate.  A microelectronic component device according to any one of the preceding claims, wherein said first substrate (C1; C1 '; C1' '; C1' ''; C1 '' '') comprises an integrated circuit arrangement.  Manufacturing method for a microelectronic component arrangement with a plurality of substrates, comprising the following steps: Providing a first substrate (C1; C1 '; C1' '; C1' ''; C1 '' '') and a second substrate (C2; C2 '; C2' '; C2' ''; C2 '' '' ), wherein the first substrate (C1; C1 '; C1' '; C1' ''; C1 '' '') and / or the second substrate (C2; C2 '; C2' '; C2' ''; C2 ' '' ') has a recess (A; A'; A ''); at least partially housing a third substrate (C3) in the recess (A; A '; A' '); and Connecting the first substrate (C1; C1 '; C1' '; C1' ''; C1 '' '') and the second substrate (C2; C2 '; C2' '; C2' ''; C2 '' '') in a stack construction with each other.

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