DE102014013482B4 - Bipolar electronic component - Google Patents

Abstract

Bipolar electronic component (poly_T), characterized in that • the bipolar electronic component (poly_T) is manufactured in a CMOS process in polycrystalline silicon and • that it has at least one n-doped region (n_poly_a, n_poly_b) and that it has at least one Having a p-type region (p_poly_a, p_poly_b), and • that a current flow when applying a voltage from the p-doped region (p_ploy_a, p_poly_b) in the n-doped region (n_poly_a, n_poly_b) is possible and that the component is disregarded its wiring is electrically isolated from other components without this and • that it is a poly-silicon NPN transistor or • that it is a poly-silicon PNP transistor (poly_T).

Description

Introduction and state of the art

In many integrated circuits driver transistors are required for the driving of loads, which may include, for example, actuators, e.g. Can supply motors or ohmic loads with electrical energy. Here, the necessary chip area plays a crucial role in order to manufacture such circuits economically. The factor that is typically essential in MOS smart power integrated circuits, limiting the compactness and size reduction of such power drivers, is the temperature that the MOS power drivers can achieve when operating as specified. A major problem is caused by the fact that the current density distribution and the gradient of the electrical potential via the MOS power transistor are not homogeneously distributed and may be subject to significant fluctuations due to manufacturing fluctuations, layout structure-related fluctuations and local heating. This can lead to locally extremely upward heating. Such deviations are commonly referred to as hotspots. Also, the mounting technique may contribute to such local heaters due to inhomogeneous adhesions between die paddle and integrated circuit. For example, a different metal coverage of the integrated circuit or the construction and connection technology lead to a different dynamics in the heat dissipation, which can heat up one place faster than the other. As a result, such power drivers must be made larger in order to safely exclude the critical temperature range in the specification-compliant operation can.

The invention will be explained below with reference to N-channel DMOS transistors as exemplary power transistors. The invention is of course also applicable to other and P-channel transistors analog.

1 shows by way of example a typical N-channel DMOS transistor, as in the prior art, in cross section. A low n ^- doped well (NWELL) is driven into the semiconductor substrate, which is typically a low p-doped silicon substrate (Sub). The corresponding methods and structures are well known from the prior art and are therefore explained here only to the extent absolutely necessary. In this N-well (NWELL) is a highly n-doped drain contact region, the drain (D), and spaced therefrom a highly n-doped source contact region, the source (S) introduced. In addition, a relatively high p ⁺ doped counter-doping (body) is introduced around the source (S) through a second, very p ⁺⁺ -doped region, the body contact (BC), which is typically located on the drain (FIG. D) facing away from the source (S), contacted and which is electrically connected to a first terminal (A1) of the source (S). This path between the source (S) and the drain (D) is divided into a first part, which is covered by a thin electrically insulating gate oxide (GOX), and a second part, which in this example with a thicker electrically insulating field oxide (FOX) is covered. These regions are covered with a gate (G), which is typically made of polycrystalline silicon, wherein the source-side edge of the gate (G) due to the production in a self-aligning process with the drain-side edge of the source contact region, the Source (S), is aligned. On the other hand, the drain-side edge of the gate (G) is spaced from the drain (D). The drain is electrically conductively connected via a second terminal (A2) and through-connection through the intermediate oxide stack (ZOX) covering the transistor. The electrically insulating intermediate oxide stack (ZOX) has the task to electrically isolate the transistor from the outside world and is broken only for the first and second terminals (A1, A2), as well as for the non-illustrated gate contact.

2 shows the essential layout elements of a simple DMOS sub-transistor according to the prior art in the supervision. The drain contacts (D) lie in areas. These active areas (Act_D, Act_S) are areas covered with gate oxide (GOX). When implanting the n ⁺ contacts, the ions do not stop in the thicker field oxide (FOX) but penetrate the thinner gate oxide (GOX) and Thus, when the gate oxide (GOX) is not shielded from the implantation ions by a polycrystalline silicon plate, such as the gate (G), the contact areas (S, D, BC) are formed. The gate plate (G) has a slot (SL) in this example. In this, the n ⁺ source contact of the source (S) is made in the overlap region of slot (SL) and source active region (Act_S).

The two overlap regions between source-active region (Act_S) and gate plate (G) form the actual channel of the exemplary MOS transistor. Between the drain-side edge of the source-active region (Act_S) and the drain-active region, the field oxide (FOX) is formed.

3 now shows a typical exemplary transistor of the prior art based on a plurality of subtransistors corresponding to the individual subtransistors of the 2 , For simplicity, in the 1 and 2 no metallizations drawn. In principle, all figures contain only the immediate ones in this disclosure necessary elements that allow a person skilled in the orientation and understanding. In this respect, it is all about schemas.

In addition to a suitable FEM modeling of the thermal-electrical dynamics in such power transistors for optimum design of the transistors, as described for example in the lecture "Predicting and Extending the Thermal Limits of DMOS Driver Stages for Automotive Power Applications" by Martin Pfost from 22. 06. 2011 is explained, a regulation of the power output by the transistors in question.

From the patent and non-patent literature, therefore, various publications and publications are already known, which are dedicated to the efficient measurement of the temperature of such driver transistors.

In Scripture "Small embedded sensors for accurate temperature measurements in DMOS power transistors" by M. Pfost et. Al (Microelectronic Test Structures (ICMTS), Proceedings of the IEEE International Conference on Microelectronic Test Structures, March 22-25, 2010, Hiroshima, Japan. 2010, Page (s): 3 - 7) For example, a method for measuring the temperature of a VDMOS transistor is disclosed. In this case, the temperature of the VDMOS transistors is detected in whole or in part by means of the base-emitter PN diode of a parasitic bipolar transistor present in the substrate and the VDMOS transistors are readjusted. In this case, the VDMOS power transistors to be regulated are preferably decomposed into smaller segments, that is to say VDMOS subtransistors, which are individually readjusted.

4 explains the unclaimed method of M. Pfost. To the left, the source part of a DMOS transistor according to the prior art is torn. To the right is the special, unclaimed structure used by M. Pfost. In the p-doped counter-doping (body) a further n ⁺ contact (E) is introduced. This forms the emitter (E) of a parasitic PNP transistor, wherein the base (B) of the parasitic transistor through the very high p ⁺⁺ -doped contact (BC) of the counter-doping (body) and the collector through the N-well (NWELL ) is formed. If a positive base-emitter voltage (V _BE ) is now applied in the direction of flow of the base-emitter diode, an emitter current (I _E ) begins to flow. However, the parasitic bipolar transistor also opens with a low current gain, which is why a collector current that differs from zero also begins to flow. Therefore, also show the 4 and 5 the writing "Small embedded sensors for accurate temperature measurements in DMOS power transistors" by M. Pfost et. Al (Microelectronic Test Structures (ICMTS), Proceedings of the IEEE International Conference on Microelectronic Test Structures, March 22-25, 2010, Hiroshima, Japan. 2010, Page (s): 3 - 7) on the one hand, a leakage current increase in the range of small drain-source voltages (see 4 of the said paper by M. Pfost) and a reduced dielectric strength (see 5 the said writing by M. Pfost). The charge carriers injected by the base contact (B) just do not only influence the parasitic transistor which serves as a temperature sensor (TS) (see FIG 4 the said font by M. Pfost), but also the adjacent DMOS transistor (DMOS) with its channel (chn).

This problem has already been recognized by other authors. For example, the DE102008023216A1 a method for measuring the operating temperature of MOS-controlled semiconductor power devices, wherein using the known temperature coefficient of electrical resistance of the gate electrode material, typically polycrystalline silicon, the electrical resistance of this material is monitored during operation of the device. For this purpose, this electrical resistance between two contact points on the gate electrode of a MOS transistor is measured by a measuring voltage superimposed on the gate voltage or a superimposed measuring current. This thus offers the possibility of measuring the temperature of the relevant MOS power transistor during operation. By a plurality of contact point pairs, the temperature measurement can be limited spatially resolved. Since the temperature measurement takes place directly in a component of the transistor, it is virtually instantaneous, which allows an immediate readjustment of the power by changing the gate voltage of the transistor.

A disadvantage of this prior art technique is that the change in resistance of the gate electrode material is z. is relatively small compared to the minimum temperature change to be detected. Furthermore, the effectiveness of this type of temperature measurement is limited by the use of salicidation processes, which are suitably introduced in the art for lowering parasitic resistances in polycrystalline silicon gate electrodes. In addition, the energization of the gate electrode leads to a change in the gate potential along the current flow and thus to a parasitic drive of the power transistor. Furthermore, the circuit options for a suitable control are limited and require complex circuits. For example, there is a direct relationship between current level and voltage drop, which comparatively much current is required for gate electrodes, which are low impedance due to the usual in the art silicidation.

From the publication "Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes With Polysilicon Diodes" by Ming-Dou Ker et. Al IEEE Transactions on Circuits to Systems II: Express Briefs Vol. 54, no. 1, January 2007 For example, a charge pump is known in which polysilicon diodes on an oxide are used as electrically isolated switches. However, these switches are not thermally optimally connected. Also, it has been found that there is a need for active devices that disclose greater sensitivity. This font and the pamphlets US 5 982 021 A . EP 2 323 165 A2 and US 214 / 0 131711 A1 9, a bipolar electronic component is collectively known, which is connected via electrically conductive silicided silicon with another bipolar electronic component made of polycrystalline silicon. Thus, a circuit of two or more electronic components is suggested from these documents, of which at least one is a bipolar electronic component made of polysilicon, wherein these two electronic components are electrically connected by an electrical line of electrically conductive slizidiertem silicon. The prior art thus suggests an electronic circuit manufactured in a CMOS process, which is manufactured from a common polycrystalline silicon layer. The prior art thus discloses diodes and electrical resistors which are produced in a CMOS process in polycrystalline silicon and which have an n-doped or p-doped region (n_poly_a, n_poly_b) and which ignore their wiring without them electrically isolated from other components.

From the prior art but no active components, but only passive components such as resistors and diodes are known. In addition, the components of the prior art are only insufficiently thermally coupled to the heat source to be controlled, here a MOS transistor.

Object of the invention

It is therefore an object of the invention to provide a device which has a greater temperature sensitivity and does not change the gate potential and thus does not change the electric field in the channel of the power transistor to be measured.

This object is achieved with a device according to claim 1 . 2 and 3 ,

Description of the basic invention

The claims are decisive for the claimed protection area.

The basic idea of the invention is, instead of the ohmic resistance of the gate electrode, to produce one or more PN junctions within a further, additional polycrystalline silicon-fabricated electrode (additional electrode), which is additionally electrically insulated and thermally conductively connected to the MOS transistor Thermo voltage of these PN junctions or the change in the electrical parameters of bipolar components, which are composed of these PN junctions, to use for the temperature measurement. Such devices may be simple PN diodes, chains of PN diodes, but also bipolar transistors and more complex components, such as four-layer diodes, so thyristors, etc. The thermoelectric voltage of an exemplary single such PN diode may then be differentially, for example, with a single reference PN junction, preferably at the PN junction in the additional electrode of a "cold" or predetermined or predetermined reference temperature, preferably identical to one another matched second MOS transistor, to be compared by a differential stage. Such a second transistor is also referred to below as a reference transistor. Matching in this disclosure are referred to as such electronic monolithic devices that are placed in the same layout with the same layout. Preferably, such components are composed of a plurality of small equal sub-components, whereby a matching with a different number of sub-components is achieved. However, this solution of the measurement with the aid of a matching reference PN junction in an additional electrode does not yet prevent the influencing of the local gate-substrate voltage of the power transistor and thus of the drain current through the measuring current (I _m ) in the additional electrode and the associated voltage drop in the additional electrode along the current flow of the measuring current (I _m ). Therefore, it is useful to such a temperature measuring device based on a PN diode, which is made in polycrystalline silicon (poly-silicon PN diode), in the immediate vicinity, but electrically isolated from the transistor and its gate electrode (G) place.

In contrast to the above-mentioned writings, a polysilicon PN diode dielectrically isolated from the original MOS gate and fabricated in the said additional electrode is used to determine the temperature change with high local and external potential via its forward voltage and / or temperature voltage determine temporal resolution. This is operated decoupled from the original gate network of power transistors in order to exclude any influence on the local gate-substrate voltage of the MOS line transistor. In combination with a calibration, for example in combination with a As already mentioned, a differential or even absolute temperature indication and thus a precise control are possible "cold" or reference temperature reference PN diode.

3 already showed the exemplary, simplified schematic layout of a conventional DMOS transistor. Here, (G) denotes the gate, (S) the source, and (D) the drain of the transistor. In the said prior art example, the transistor consisted of four drain contact fingers (D) between which were three slotted poly-silicon plates, the gate plates (G), which connected the gate (G) of the Transistors were formed and were typically electrically connected in another wiring, not shown. The gate poly plates (G) only partially overlapped the region (ACTI) in which only one gate oxide (GOX) covered the semiconductor, typically silicon. A certain part was above the thicker field oxide (FOX) and formed a field plate. The source contact (S) is located in the slot (SL) of the poly-silicon plate which forms the gate (G).

Such a transistor is for example in the DE4322548A1 described.

figure 5

A central strip of the DMOS transistor is split. ( 5 In these, preferably, the said PN diode (Poly_D) or another temperature measuring device (TS) is introduced. It is particularly advantageous if the temperature measuring devices (TS) are distributed uniformly over the surface of the MOS transistor to be controlled. In the exemplary case, only one poly-silicon PN diode (Poly_D) is introduced as a temperature measuring device (TS), which is contacted by means of several poly-silicon connections (Cont_A, Cont_K). Again 5 it can be seen, it is particularly advantageous if the MOS transistor has an approximately square shape with respect to all subtransistors and subtransistors. The shape of an octagon or a circular shape are also advantageous, though not drawn in the attached figures. As a result, a particularly high symmetry is achieved in each case. The exemplary symmetry lines (Sym1) are drawn by dashed lines. It has been shown in the context of the development of the invention that an electrically insulated temperature measuring device (TS) can disturb the thermal properties of such a MOS transistor and thus also its electrical properties. The purely electrical isolation of the temperature measuring device (TS, Poly_D) is therefore typically insufficient. An asymmetric placement of such a temperature measuring device (TS, Poly_D) within the MOS transistor can therefore lead to an inhomogeneous current density distribution in such a power MOS transistor and thus to a reduction of its maximum load capacity. Only such a symmetric placement leads to a minimal influence of the power MOS transistor by the temperature measuring device (TS, Poly_D), for example, the said poly-silicon PN diode (poly_D). A significant advantage of the device is the separation of the device from the gate potential of the gate electrode (G) of the MOS transistor and the lower disturbance in the transistor structure, which is typically to be expected by structures in the active region of the power devices. In the DE102008023216A1 it comes, as mentioned, by the current flow of the measuring current to a voltage drop on the gate (G) and thus to different gate-source voltages in the transistor channel (chn) of the MOS transistor. Such a modification of the current density distribution by the measurement current leads to complex interactions that are difficult to survey. An electrical decoupling coupled with good thermal coupling is therefore required, as it provides the device according to the invention. If the leads of the temperature measuring device (TS) executed symmetrical, so is the heat dissipation over this symmetrical with respect to the layout of the MOS transistor and disturbs the temperature density distribution in all subtransistors of the MOS transistor in the same way.

It has been found that the opening of a gate oxide window (Act_D, twd) below the poly-silicon PN diode (poly_D), which in this example of the 5 serves as a temperature measuring device (TS), to a very rapid temperature-moderate coupling of the poly-silicon PN diode (poly_D) to the substrate (Sub) or another in the substrate (Sub) manufactured component of the MOS transistor, for example, the N- Well (NWELL), so that thermal time constants smaller than 100ns could be observed. This thermally conductive and electrically insulating coupling of the temperature measuring device (TS) and here in particular, for example, the poly-silicon PN diode (poly_D) via a thin gate oxide (GOX), typically a thickness (d) of less than 200nm, better less than 100nm, better less than 50nm, better less than 20nm, better less than 10nm, is thus an essential part of the characterizing features of a possible embodiment of the invention. However, if the poly-silicon PN diode (Poly_D) is placed directly over the channel (chn) of the MOS transistor (TR), care should be taken that the capacitive voltage divider is diode-gate capacitance between the poly-silicon PN diode (poly_D), and the gate electrode (G) of the MOS transistor (TR) and the gate channel capacitance between the gate electrode (G) of the MOS transistor (TR) and the channel (chn ) of the MOS transistor (TR) is designed so that dynamic controls of the poly- Silicon PN diode (poly_D) in the respective application does not lead to a fluctuation of the drain or source current of the MOS transistor (TR) over a tolerable level in the respective application. If necessary, the person skilled in the art will carry out corresponding simulations and calculations beforehand and / or avoid as far as possible a triggering of the poly-silicon PN diode (poly_D) with signals above a conversion-specific cutoff frequency. By means of the described method, a high local resolution can typically be achieved in the measurement of different parts of the MOS transistor with a plurality of temperature measuring devices (TS) in the reasonable order of approximately 20 μm ² .

By using multiplexers, the temperature can be recorded and evaluated, for example, at several critical locations by means of a plurality of such poly-silicon PN diodes (Poly_D) or temperature measuring devices (TS). As already mentioned, each of the subtransistors can then be correspondingly 1 be individually readjusted.

figure 6

6 shows a more detailed image of the poly-silicon PN diode (poly_D). This is placed in this embodiment between the two halves of a split partial transistor so that the symmetry of the two halves or parts is preferably not disturbed, if possible. The 6 shows on the left the gate (G1) and the source (S1) of the left partial transistor. The 6 shows on the right the gate (G2) and the source (S2) of the right partial transistor. The two active areas (Act1, Act2) are also drawn. The left partial transistor half is terminated electrically by a first channel stopper implantation (PIMP1) with a p-doped region to the right of the poly-silicon PN diode (Poly_D). The right sub-transistor half is terminated by a second channel stopper implantation (PIMP2) with a p-doped region to the left to the poly-silicon PN diode (Poly_D) also electrically defined. In the middle between the spaced left and right sub-transistor halves is the poly-silicon PN diode (Poly_D), which is also spaced from both sub-transistor halves. In this example, the poly-silicon PN diode (poly_D) is produced in the polycrystalline silicon layer by etching as poly-substrate (PSD) of said polycrystalline silicon, in which in the same operation, the gate electrodes (G) from the same polycrystalline silicon material can be made. In terms of its mechanical structure, the poly-silicon PN diode (poly_D) is a gate electrode. However, the so-formed "transistor" of the poly-silicon PN diode (poly_D) has no drain and source contacts (see 7 ). According to the invention, however, an active region (ACTI_D) is provided in the center of the poly-silicon PN diode (Poly_D) to produce a temperature-conductive window (twd) in the field oxide (FOX). This gate oxide window (twd) in the surrounding thicker field oxide (FOX) serves, as stated, to couple the polycrystalline silicon material of the polysilicon PN diode (poly_D) with low heat capacity to the substrate (sub) of the surrounding transistor , In this polycrystalline silicon of the poly-substrate (PSD) of the poly-silicon PN diode (poly_D), an electronic component and / or another semiconductor sensor are now produced in particular by implantation and / or silicidation. In the exemplary embodiment of 6 this is the poly-silicon PN diode (poly_D). In the example, there are two contacts (Cont_A) on the anode side. These are surrounded by a P-type implantation region (PIMP), with which the p-type part of the poly-silicon PN diode (poly_D) is manufactured. In the course of the production process, silicidation (SBLO) is carried out by formation of electrically conductive titanium silicide in the region of the contacts (Cont_A) such that only a narrow strip of the P implantation region (PIMP) is not silicided in the direction of the cathode contacts (Cont_K). The N-doping is carried out with an N-implantation (NM) in the region of the cathode contacts (Cont_K). On the cathode side, the poly-silicon PN diode (Poly_D) is connected via these two cathode contacts (Cont_K). Also in the area of the cathode contacts (Cont_K) a silicidation (SBLO) is carried out to improve the conductivity, whereby this time a narrow n-doped strip in the direction of the anode contacts is not silicided electrically conductive with titanium silicide. Between the n- and p-doped region there is preferably an intrinsic or typically weakly n ^- doped polysilicon region. It has been found that this "i-region" lowers the leakage current of the silicon PN diode (poly_D). The use of such an i-region is therefore a preferred expression of a poly-silicon PN diode (poly_D). Preferably, the terminals of the poly-silicon PN diode (poly_D) in the figure 5 along the vertical line of symmetry (Sym1) led out of the MOS transistor, for example in metal. The poly-silicon PN diode (Poly_D) thus placed in the center of the power transistor to be regulated can thus function as a temperature measuring device (TS), without, like the devices of the prior art, the distribution of the electrostatic fields covering the drain. Control current through the transistor channels and / or disturb the symmetry of the temperature distribution.

figure 7

7 shows a simplified cross section through the silicon PN diode (poly_D). In fact, in the example shown here, this is due to the "i-region" used and a silicon PIN diode (poly_D). In the following, however, only a silicon PN diode (poly_D) is used, such silicon PIN diodes (poly_D) typically being included in the description. Above the cross section, the structure is off again 6 repeated without reference in supervision for better orientation. To the left and right of the thermal window (twd) formed by the gate oxide (GOX), with which the silicon PN diode (Poly_D) to the substrate or other transistor components, such as the N-well (NWELL), thermally conductive is attached, there is the thicker and thus more thermally insulating field oxide (FOX), as typically occurs for example in a LOCOS process. However, the structure can also be realized in a similar form in other CMOS processes, for example a shallow-trench process. On the gate oxide (GOX) and the field oxide (FOX) it is polycrystalline silicon strip of the silicon PN diode (poly_D) applied. This is here exemplified by a p-implantation and n-implantation and electrically structured by the local silicidation, for example with titanium silicide. In the example, it has the said first electrically conductive silicidation (sil_b) in the region of the cathode contact (Cont_K), which is electrically connected via a third line (A3). In addition, it has the said second electrically conductive silicidation (sil_a) also in the region of the anode contact (Cont_A), which is electrically connected via a fourth line (A4).

The first electrically conductive silicidation (sil_b) contacts the n-doped region (n_poly) within the polycrystalline silicon material of the poly-silicon PN diode (poly_D). The second electrically conductive silicidation (sil_a) similarly contacts the p-doped region (p_poly) within the polycrystalline silicon material of the poly-silicon PN diode (poly_D).

Between these two poly-silicon regions (n_poly, p_poly) is located in the polycrystalline silicon material of the poly-silicon PN diode (poly_D) an intrinsic or typically weakly doped, for example, weakly n-doped region (i_poly), as already explained, the Function is to minimize the leakage current of the poly-silicon PN diode (poly_D).

figure 8th

By a simple series connection of the poly-silicon PN diode (poly_D) in particular within a common polycrystalline silicon strip, the amplitude of the original measurement signal whose voltage is typically between 300mV and 700mV and the temperature-dependent signal component of typically only 2mV / K ° multiplied become. 8th shows the exemplary layout of such an element with two poly-silicon PN diodes (Poly_Da, Poly_Db). in the supervision. The two p ⁺ implants are now connected to a p ⁺ implantation (PIMP), which simultaneously generates the p ⁺ -doped anode of the second polysilicon PN diode (poly_Db). In manufacturing, however, this results in three isolated p-areas. The shading effect of the poly-substrate (PSD) and the rock oxide (FOX) causes the two p ⁺ -plants (PIMP1 and PIMP2) to remain electrically isolated.

The poly-substrate (PSD) lying above the field oxide is thereby also p ⁺ -doped and forms the p ⁺ -implantation region (PIMPb) for the second poly-silicon PN diode (poly_Db). However, this p ⁺ implantation area (PIMPb) is not shown separately. This p ⁺ implantation region (PIMPb), however, is electrically isolated from the substrate (Sub) by the field oxide (FOX) or the gate oxide (GOX) and thus from the power transistor and its subtransistors. The masks of the N-type dopants (NMa, NMb) and the silicidation mask (SBLOa, SBLOb) are now present separately for the two poly-silicon PN diodes (Poly_Da, Poly_Db). In addition, a very important silicidation of the polycrystalline silicon material takes place above the third resulting PN junction, thereby electrically bridging and shorting it. Without this measure, at least one PN transition would always be blocked. Of course, the first poly-silicon PN diode (Poly_Da) has its own P ⁺ implantation region (PIMPa). By this series connection of the first poly-silicon PN diode (poly_Da) and second poly-silicon PN diode (poly_Db), the temperature effect on the temperature voltage or the forward voltage or the forward current of the poly-silicon PN diode structure ( Poly_Da, poly_Db) doubled. Of course, more than the two exemplary diodes or only one diode can be provided. For example, in an extreme case, a division of all partial transistors along the axis of symmetry of 5 as in the middle subtransistor of 5 and a series connection of very many such poly-silicon PN diodes (Poly_Da, Poly_Db) in the manner presented.

It is also possible to separate the partial transistors in more than two places and to provide a plurality of such chains and / or measuring locations at different locations in such a transistor consisting of a plurality of partial transistors.

figure 9

9 shows a simplified cross section through the series connection of two silicon PN Diodes (Poly_Da, Poly_Db). Above is the structure once again 8th repeated without reference in supervision for better orientation. To the left and right of the thermal window (twd) formed by the gate oxide (GOX), to which the silicon PN diodes (Poly_Da, Poly_Db) are applied to the substrate (Sub) or another transistor components, such as the N-well ( NWELL), is again the thicker and thus more thermally insulating field oxide (FOX). On the gate oxide (GOX) and the field oxide (FOX), the polycrystalline silicon substrate (PSD) of the silicon PN diode (poly_D) is applied. This is again exemplary here, but now in other ways electrically structured by a p-implantation and an n-implantation as well as by the local silicidation, for example with titanium silicide. In the example, it again has the said first electrically conductive silicidation (sil_b) in the region of the cathode contact (Cont_K), which is electrically connected via a third line (A3). In addition, it has the said second electrically conductive silicidation (sil_a) also in the region of the anode contact (Cont_A), which is again electrically connected via a fourth line (A4). Unlike the previous example of 7 However, it now has a third silicided area (sil_m) which shorts the third parasitic PN junction. The first electrically conductive silicidation (sil_b) contacts the n-doped region (n_poly_b) of the second poly-silicon PN diode (Poly_Db) within the polycrystalline silicon material (PSD) of the second poly-silicon PN diode (Poly_Db). The second electrically conductive silicidation (sil_a) analogically contacts the p-doped region (p_poly_a) of the first poly-silicon PN diode (Poly_Da) within the polycrystalline silicon material (PSD) of the first poly-silicon PN diode (Poly_Da). Between the two poly-silicon regions (n_poly_b, p_poly_a), the poly-silicon material of the poly-silicon PN diode (poly_D) contains the p-doped poly-silicon region (p_poly_b) of the second poly-silicon PN diode (poly_Db) and the n-doped poly-silicon region (n_poly_a) of the first poly-silicon PN diode (Poly_Da). These collide directly and would normally lock when the other two PN junctions are poled in the flow direction. To prevent this, the polycrystalline silicon is silicided in this area so that these two poly-silicon areas (p_poly_b, n_poly_a) are electrically conductively connected to each other and preferably at the same time still n- and p-areas are not silicided.

As before, there are now two intrinsic or at least weakly doped, preferably weakly n-doped regions (i_poly_b, i_poly_a) between these p and n regions, which again have the function of minimizing the leakage currents of the two diodes.

figure 10

Until then, the temperature measuring device has been placed exclusively adjacent to the transistor to be controlled.

However, if the integrated circuit is fabricated in a process that provides for a plurality of superimposed polycrystalline silicon layers, it makes sense to use a second overlying polycrystalline layer for the fabrication of a poly-silicon PN diode (Poly_D) above the transistor to be controlled use.

10 shows such a transistor in cross section. Another element of the MOS transistor of the invention 10 is a second polycrystalline silicon electrode (poly_D), such as typically available in flash CMOS processes. 10 shows a MOS transistor according to the prior art 1 supplemented by the inventive poly-silicon PN diode (poly_D) in cross section. It has the source contact (S), the gate (G) and the drain contact (D). A thicker field oxide (FOX) and a thin gate oxide (GOX) isolate the gate electrode (G) from the channel (chn). The source (S) is connected via a source connecting line (A1) and the drain (D) via a drain connecting line (A2). In addition to the already existing gate (G), a second electrode (PSD) is located above the gate electrode (G) through an ONO stack (ONO). By ONO stacks is here understood a sequence which is vertical to the transistor surface to successive different dielectric insulating layers, which are designed to achieve a good electrical insulation. For the purposes of this disclosure, however, said ONO stack may consist of only a single layer. Typically, however, a sequence of SiO ₂ and Si ₃ N ₄ layers is chosen, which results in a dielectric strength greater than the maximum operating voltage (maximum drain-source voltage) of the transistor to be controlled, whereby a reliable isolation of the temperature measuring device, the poly-silicon PN diode (poly_D), opposite to the gate (G) of the MOS transistor is achieved. The thickness (d) of this layer is typically less than 800nm, better less than 400nm, better less than 200nm, better less than 100nm, better less than 50nm, better less than 20nm, better less than 10nm. It is obvious to the person skilled in the art that here a special thermal window (twd) and the associated photographic technology are not required for its realization. Due to the small spatial distance, the poly-silicon PN diode (poly_D, poly_D) is very well thermally coupled to the gate (G) and thus also coupled to the channel (chn) and the substrate of the MOS transistor. Will now be Measuring current fed into this poly-silicon PN diode (poly_D), so there is indeed a voltage drop and thus to the expression of an electric field along the poly-silicon PN diode (poly_D), but this electric field can not acting on the channel of the MOS transistor, because the electrostatic field of the poly-silicon PN diode (poly_D) by the electrically conductive gate electrode (G) of the MOS transistor with respect to the channel (chn) of the MOS transistor is shielded. It is therefore an essential step to place a shield between the poly-silicon PN diode (poly_D) and the channel of the MOS transistor, so that the electrostatic effect of the measuring current can no longer affect the current flow in the channel of the MOS transistor , The gate electrode (G) of the MOS transistor (TR) thus preferably shields the electric field of the poly-silicon PN diode (Poly_D) such that, in the intended use, the poly-silicon PN diode (Poly_D) the drain or source current of the MOS transistor (TR) does not change by more than 5% and / or not more than 2.5% and / or not more than 1%. Of course, it will be apparent to those skilled in the art that this arrangement does not necessarily require a poly-silicon PN diode (Poly_D) for temperature measurement. Rather, of course, the change in the electrical resistance of such a second additional, electrically inactive electrode can of course also be evaluated here, which is why the arrangement of the temperature measuring device (T _s ) in this way is already a separate feature of this invention. The advantage of this measuring method by means of an electrically isolated and thermally conductively connected electrical resistance compared to the method of measurement with a poly-silicon PN diode (poly_D) is above all the linearity of the resistors. In the context of the invention, it has been found that production as a metallic resistor from the said titanium silicide with approximately 20 mm / square is very advantageous here. A design as a poly-resistance is preferable, however, because then the amount of electricity to be used is much lower. The choice of resistance will depend on the actual application and availability of electrical energy.

It is, looking back on the above, another essential innovative step into the gate of a transistor, one or more bipolar devices, here to integrate said poly-silicon PN diode (poly_D) into a MOS power transistor in the form of 3D integration and these to use for the control of the MOS transistor itself.

Also, the method of resistance measurement by means of the additional polycrystalline silicon electrode analogous to the cross section of the 10 be combined with the measurement by means of a poly-silicon PN diode (poly_D), this according to the arrangement of the 10 and / or 5 and 6 can be placed. Thus, a combination of these measurements is possible.

figure 11

11 shows the cross section through a MOS transistor according to the invention with the temperature measuring device (TS) according to the invention, wherein the cross section through the MOS transistor according to the invention now perpendicular to the MOS transistor of the 10 lies. The current flow within the MOS transistor is thus perpendicular to the plane of the page, while the current flow in the MOS transistor in 10 took place across the page. The 11 shows the gate oxide (GOX) of the MOS transistor and electrically insulated by this against the substrate (Sub) and the N-well (NWELL), above its gate electrode (G), which at the same time by the gate oxide ( G) is thermally connected to the channel (CHN) of the MOS transistor. The gate electrode (G) is electrically insulated upwardly by said ONO stack (ONO). Thereupon is the polycrystalline silicon substrate (PSD) of the temperature measuring device (TS). In this polycrystalline silicon substrate (PSD), the PN diode chain is the 9 made with their elements. The corresponding description of 9 applies accordingly. Due to the small distance (d) of this ONO layer (ONO) of typically less than 800nm, better less than 400nm, better less than 200nm, better less than 100nm, better less than 50nm, better less than 20nm, better less than 10nm of The gate electrode (G) is a very good thermal connection of the temperature measuring device (TS, PSD), ie the chain of first poly-silicon PN diode (poly_Da) and second poly-silicon PN diode (poly_Db), to ensures the temperature of the gate electrode (G) and thus to the temperature in the channel (chn) of the MOS transistor. Of course, only one PN diode or more than two PN diodes can be manufactured in this way in the vicinity of the MOS transistor and thus to this thermally connected.

figure 12

12 shows a further exemplary alternative for the formation of the temperature sensor (TS) according to the invention. In the in the 12 As shown, this is a PNP transistor which, as before, fabricates the poly-silicon PN diode (Poly_D) as a poly-silicon PNP transistor (Poly_T) in the polycrystalline silicon substrate (PSD). The poly-silicon PNP transistor (Poly_T) has the two double contacts (Cont_E, Cont_c) already used in the poly-silicon PN diode (Poly_D). A first double contact (Cont_E) serves as an emitter contact. The second double contact (Cont_C) serves as a collector contact. Both contacts each contact a p-doped region (PIMPa, PIMPb) The base is designed as a lateral branch of the polycrystalline silicon substrate (PSD). This lateral branch serves as a supply line to the base from the additional base contact (Cont_B). In the example, the entire branch is n-doped. But it is also conceivable to make parts of this feed to silicided and thus more electrically conductive. The n-doped base (NM) is designed as narrow as possible in the region of the crossing of the current path from the emitter to the collector for the purpose of a good current amplification. As before, the poly-silicon PN diode (poly_D), this poly-silicon PNP transistor (poly_T) has a thermal window for thermal connection to the substrate. As temperature-dependent parameters of the poly-silicon PNP transistor (poly_T), it is possible to use, for example, the current gain, the forward resistance etc. of this poly-silicon PNP transistor (poly_T). Of course, poly-silicon NPN transistors and more complex bipolar devices are possible on this basis. It is obvious that in particular by silicided polycrystalline compounds more complex circuits of such polycrystalline-based devices are possible, wherein individual polycrystalline silicon resistors may be part of such circuits. These circuits can then be placed above the gates of power transistors. It is conceivable, for example, to use such circuits as sensors, for example for light, etc.

figure 13

13 shows the exemplary poly-silicon PNP transistor (poly_T) 12 in cross section. The two p-doped regions (p_poly_b, p_poly_a) are each again connected via a silicidation (sil_a, sil_b) to the respective line (A3, A4). In this example, these p-doped regions (p_poly_b, p_poly_a) are not brought up completely to the n-doped region (n_poly_a) of the base. In this example, there is one low or undoped area (i_poly_, i_poly_b) to the left and right of the base area (n_poly_a). Depending on the application, these undoped areas can be selected larger or smaller or omitted altogether.

figure 14

Simple circuits can be specified for the evaluation of the measured values of such a structure.

14 shows a simple example. For example, it is assumed that the transistor to be measured is a P-channel transistor. However, this and the following circuits can be easily changed by a skilled person into the corresponding circuits for an N-channel MOS transistor.

The transistor (TR) according to the invention has a temperature measuring device (TS) according to the invention, that is to say the resistor according to the invention and / or a poly-silicon PN diode (poly_D) according to the invention. Of course, a temperature measuring device may also be a bipolar transistor according to the invention.

If it is a poly-silicon PN diode (poly_D) according to the invention, this can be as in 5 be placed within the MOS transistor between the subtransistors and / or transistor parts or as in 10 above portions of the MOS transistor, typically within the oxide stack. In any case, the good thermal coupling, in particular by the ONO stack (ONO) or the thermal window (twd), is required. In the example of 14 the temperature measuring device, in this case the poly-silicon PN diode (Poly_D), is supplied with a measuring current (I _m ) and the resulting measuring voltage is supplied to two exemplary comparators (Cmp ₁ , Cmp ₂ ), each of which supplies this voltage with a first reference voltage (V _ref1 ) and a second reference _voltage (V _ref2 ) compare and thus, for example, generate two temperature _signaling (T ₁ , T ₂ ) for different temperatures, which can then be used for example inside and outside the associated integrated circuit.

figure 15

15 shows a possible, simple control system for an exemplary MOS transistor, which consists of several, here exemplified three, partial transistors (TR ₁ , TR ₂ , TR ₃ ). Typically, such subtransistors TR ₁ , TR ₂ , TR ₃ ) are made matching. Each of the exemplary three subtransistors (TR ₁ , TR ₂ , TR ₃ ), which may for example also be three subtransistors here, is associated in this example with a comparator (Cmp _{3_1} , Cmp _{3_ 2} , Cmp _{3_3} ), of which, however, in the 15 only the first comparator (Cmp _{3_1} ) is shown for better clarity. First, therefore, only the structure of the first comparator (Cmp _{3_1} ) of 15 part of the scheme. For the other two comparators (Cmp _{3_2} , Cmp _{3_3} ) and their wiring then what is said applies analogously.

The first temperature measuring device (D ₁ ) of the first partial transistor (TR ₁ ), for example a poly-silicon PN diode (Poly_D), is energized by a first current source associated with this temperature measuring device (D ₁ ) with a first measuring current (I _{m_1} ). The occurring voltage is determined by the first comparator (Cmp _{3_1} ) 15 with the reference voltage (V _ref ), which is typically the same for all the subtransistors (TR ₁ , TR ₂ , TR ₃ ). The associated first temperature signal (T _a1 ) of the first partial transistor (TR ₁ ) is supplied to the control (CTR), which adjusts the gates of the exemplary three partial transistors (TR ₁ , TR ₂ , TR ₃ ) in response to this signal. This can be done, for example, by changes in the control voltage amplitude or by temporary omission of the drive in the affected region of the transistor.

In a first approximation, the resistance of the first partial transistor (TR ₁ ) is increased by the control (CTR) when the power consumption of the first partial transistor (TR ₁ ) is too high and the first partial transistor (TR ₁ ) in an environment with an impressed drain -Source voltage is located. Likewise, in a first approximation, the resistance of the first subtransistor (TR ₁ ) is lowered when the power consumption of the first subtransistor (TR ₁ ) is too high and the first subtransistor (TR ₁ ) is in an impressed drain or source current environment , In between, there are hybrid forms that require a more complicated regulation, which is not dealt with here.

In this way, not only the first subtransistor (TR ₁ ) is regulated, but also the other subtransistors (TR ₂ , TR ₃ ), each of which in this example is a comparator (Cmp _{3_ 2} , Cmp _{3_3} ), a current source for the associated one Measuring current (I _{m_1} , I _{m_2} ), etc., so typically to each of these subtransistors (TR ₁ , TR ₂ , TR ₃ ) in each case a temperature signal (T _a1 , T _a2 , T _a3 ) of the corresponding subtransistor (TR ₁ , TR ₂ , TR ₃ ) is made available to the controller by the respective comparator (Cmp ₁ , Cmp ₂ , Cmp ₃ ). These control circuits for the second and third subtransistor (TR ₂ , TR ₃ ) are in the example of 15 , as already mentioned, not shown for the sake of clarity. These two partial transistors (TR ₂ , TR ₃ ) are in the example of 15 Of course, also controlled by the controller (CTR). The controller receives in the example A target signal, which corresponds to the gate signal of a transistor of the prior art in its effect and function as an external signal (soll).

Furthermore, the in 15 shown structure to be used in conjunction with a hysteresis-related comparator (Cmp ₁ , Cmp ₂ , Cmp ₃ ) to protect the MOS transistor (TR) from local overheating. In this simple application, the corresponding subtransistor (TR ₁ , TR ₂ , TR ₃ ) would be switched off above a temperature threshold proportional to a reference voltage (V _ref ) plus hysteresis and upon cooling below a second temperature threshold proportional to the reference voltage (V _ref ) minus said hysteresis activated again.

figure 16

16 shows a very simple way of implementing a control level. The desired signal is here as a control voltage (V _ctr ) a voltage-controlled current source, that is, for example, supplied within a current mirror. The current source is energized here by the temperature measuring device (D ₁ ), in this example again a poly-silicon diode as described above, with a measuring current (I _m ). The temperature measuring device is now directly connected to the source (S) of the exemplary p-channel MOS transistor (TR ₁ ). An optional amplifying resistor (R _s ) is connected in series with the temperature measuring device (D ₁ ). The gate potential of the MOS transistor (TR ₁ ) is taken between the current source and resistor (R _s ) and temperature measuring device (D ₁ ). Thus, the gate-source voltage and thus the conductivity state of the MOS transistor (TR ₁ ) is typically substantially by the current (I _m ) of the current source and thus by the control voltage (V _ctr ) on the one hand and the conductivity state of the temperature _{measuring device} (D ₁ ) on the other side. We now assume that the temperature measuring device is the poly-silicon PN diode (Poly_D). When the MOS transistor (TR ₁ ) becomes too hot, the conductivity of the poly-silicon PN diode (Poly_D) increases and the gate-source voltage becomes smaller. Thus, the resistance of the MOS transistor (TR ₁ ) increases. If the MOS transistor (TR ₁ ) is used in an environment in which the voltage across the MOS transistor (TR ₁ ) is impressed, the drain-source current and thus the converted in the MOS transistor (TR ₁ ) decreases electrical power.

In the reverse case of an impressed drain-source current of the transistor (TR ₁ ), the resistance of the MOS transistor (TR1) would increase. Due to the proportionality of power to resistance and the square of the flowing current, the circuit is in combination with others similar, parallel structures suitable to perform a power distribution.

Advantageously, the type of control can be off 16 can be used to distribute in integrated voltage regulators the current, and thus the power, within the driving MOS transistor (TR). The control voltage (V _ctr ) in this case is the output of a regulator which, via this control voltage (V _ctr ), has several parallel structures as in 16 similarly controls (see also 17 ). In this case, the individual MOS transistors or partial transistors (TR ₁ , TR ₂ , TR ₃ ) inherently self-regulate, without the higher-level controller _having to take this into account for specifying the control voltage (V _ctr ). The limits of the so-called safe Operating Area (SAO) can thus be maintained symmetrized.

figure 17

For all of these methods of temperature measurement, calibration and calibration on an equivalent "cold" matching structure or at least one cold matching temperature measurement device is always feasible. This is in 17 shown schematically.

The structure of 17 is similar to the 15 with the difference that now the reference voltage (V _ref ) is generated at the said "cool" matching structure with index "k". The measurement signal of the cool structure is thus the reference voltage (V _ref ). Of course, it makes sense to assemble larger MOS transistors (TR) from smaller subtransistors (TR ₁ , TR ₂ , TR ₃ ) and the reference voltage (V _ref ) by means of a single "cold" subtransistor (TR _k ) connected to the other Subtransistors (TR ₁ , TR ₂ , TR ₃ ) matched to win.

Alternatively, the information provided by the comparator (Cmp ₄ ) in 17 obtained information (T _sig ) are used to decide which of the partial transistors (TR ₁ , TR ₂ , TR ₃ ) has the lower temperature. On this basis, it can then be decided in the following by a suitable control over a power distribution between the partial transistors (TR ₁ , TR ₂ , TR ₃ ).

Advantages of the invention over the prior art

The device according to the invention can be manufactured without an additional mask in a typical standard CMOS process and thus causes no additional costs. It allows a spatially resolved rapid measurement of the temperature profile of MOS power transistors and thus a closer guidance of the same at their respective power limit, which allows the reduction of the IC area for these transistors and / or an increase in the maximum allowable power.

Summary of the disclosed features

The features of the invention are summarized again below. The scope claimed here follows from the section entitled "Claims" following this section.

Feature 1

• - wobei der MOS-Transistor (TR) zusammen mit mindestens einer Temperaturmessvorrichtung (TS, Poly_D, Poly_T, D₁, D₂, D₃) monolithisch auf einem Substrat (Sub) untergebracht ist und
• - wobei der MOS-Transistor (TR) aus einem oder mehreren Teiltransistoren (TR₁, TR₂, TR₃), insbesondere Transistorfingern, besteht und

gekennzeichnet dadurch,

• - dass das Messsignal (V_ist) mindestens einer Temperaturmessvorrichtung (TS, Poly_D, Poly_T, D₁, D₂, D₃) des MOS-Transistors (TR) mit dem Messsignal (V_ref) einer korrespondierenden Temperaturmessvorrichtung (D_k) eines matchenden Transistors (TR_k) oder matchenden Transistorteils oder matchenden Teiltransistoren durch Differenzbildung der beiden besagten Messsignale in einer Differenzbildungsvorrichtung, insbesondere in einem Komparator (Cmp₄), verglichen wird, wobei ein Differenzsignal (T_sig) erzeugt wird, und
• - dass das Differenzsignal (T_sig) zur Regelung des Drain- oder Source-Stromes durch diesen MOS-Transistor (TR) oder einen Teil des MOS-Transistors oder einen Teiltransistoren (TR₁, TR₂, TR₃) des MOS-Transistors (TR) und/oder des Spannungsabfalls über diesen MOS-Transistor (TR) oder einen Teil des MOS-Transistors oder einen Teiltransistoren (TR₁, TR₂, TR₃) des MOS-Transistors (TR) benutzt wird.

Method for regulating the temperature of a MOS transistor (TR), in particular a DMOS transistor,

• - Wherein the MOS transistor (TR) together with at least one temperature measuring device (TS, Poly_D, Poly_T, D ₁ , D ₂ , D ₃ ) is monolithically housed on a substrate (Sub) and
• - Wherein the MOS transistor (TR) consists of one or more subtransistors (TR ₁ , TR ₂ , TR ₃ ), in particular transistor fingers, and

characterized by

• - That the measuring signal (V _is ) at least one temperature measuring device (TS, Poly_D, Poly_T, D ₁ , D ₂ , D ₃ ) of the MOS transistor (TR) with the measuring signal (V _ref ) a corresponding temperature measuring device (D _k ) of a matchenden Transistors (TR _k ) or matching transistor part or matching subtransistors by subtracting the two said measurement signals in a difference formation device, in particular in a comparator (Cmp ₄ ) is compared, wherein a difference signal (T _sig ) is generated, and
• - That the difference signal (T _sig ) for controlling the drain or source current through this MOS transistor (TR) or a part of the MOS transistor or a partial transistors (TR ₁ , TR ₂ , TR ₃ ) of the MOS transistor ( TR) and / or the voltage drop across this MOS transistor (TR) or a part of the MOS transistor or a partial transistors (TR ₁ , TR ₂ , TR ₃ ) of the MOS transistor (TR) is used.

Characteristic 2

• - dass das Differenzsignal (T_sig) eine Hysterese aufweist.

Method according to feature 1 characterized,

• - That the difference _signal (T _sig ) has a hysteresis.

Feature 3

• - dass die Regelungskennlinie der elektrischen Verlustleistung (V_DS*I_D) des MOS-Transistors (TR) und/oder eines Teiltransistors (TR₁, TR₂, TR₃) in Abhängigkeit von der Temperatur seiner Gate-Elektrode (G) und/oder seines Kanals (chn) bezüglich einer steigenden Temperaturrampe gefolgt von einer fallenden Temperaturrampe eine Hysterese aufweist.

Method according to feature 1 or 2 characterized,

• - That the control characteristic of the electrical power loss (V _DS * I _D ) of the MOS transistor (TR) and / or a partial transistor (TR ₁ , TR ₂ , TR ₃ ) in dependence on the temperature of its gate electrode (G) and / / or its channel (chn) has a hysteresis with respect to a rising temperature ramp followed by a falling temperature ramp.

Characteristic 4

• - dass die Temperaturmessvorrichtungen (TS, Poly_D, Poly_T, D₁, D₂, D₃) gleichmäßig und symmetrisch über den MOS-Transistor (TR) und/oder eine Anordnung von Teiltransistoren (TR₁, TR₂, TR₃) verteilt sind und
• - dass der MOS-Transistor (TR) und/oder eine Anordnung von Teiltransistoren (TR₁, TR₂, TR₃) ohne Verdrahtung mindestens eine Spiegelsymmetrieachse (Sym1) aufweist und
• - dass die Temperaturmessvorrichtungen (TS, Poly_D, Poly_T, D₁, D₂, D₃) spiegelsymmetrisch bezüglich zumindest dieser einen Spiegelsymmetrieachse (Sym₁) oder auf dieser Symmetrieachse (Sym1) angeordnet sind.

Method according to one or more of the features 1 to 3 characterized,

• - the temperature measuring devices (TS, Poly_D, Poly_T, D ₁ , D ₂ , D ₃ ) are distributed uniformly and symmetrically over the MOS transistor (TR) and / or an arrangement of partial transistors (TR ₁ , TR ₂ , TR ₃ ) and
• - That the MOS transistor (TR) and / or an array of subtransistors (TR ₁ , TR ₂ , TR ₃ ) without wiring at least one mirror axis of symmetry (Sym1) and has
• - That the temperature measuring devices (TS, Poly_D, Poly_T, D ₁ , D ₂ , D ₃ ) are arranged mirror-symmetrically with respect to at least one of these mirror symmetry axis (Sym ₁ ) or on this symmetry axis (Sym1).

Feature 5

• - dass die Temperaturmessvorrichtung (TS) eine PN-Diode (Poly_D) insbesondere als temperaturempfindliches elektronisches Bauelement enthält.

Method according to one or more of the features 1 to 4 characterized,

• - That the temperature measuring device (TS) includes a PN diode (poly_D) in particular as a temperature-sensitive electronic component.

Characteristic 6

• - dass die PN-Diode (Poly_D) bezüglich der elektrischen Leitfähigkeit und der Beeinflussung von Teilen des MOS-Transistors (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A₁, A₂, chn, body) durch eine elektrische Isolation (ONO, GOX, twd) von diesen Teilen zum einen elektrisch isoliert ist und zum anderen thermisch leitend an mindestens eines dieser Teile (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A₁, A₂, chn, body) des MOS-Transistors (TR) angebunden ist.

Method according to feature 5 characterized,

• that the PN diode (poly_D) with respect to the electrical conductivity and the influence of parts of the MOS transistor (TR ₁ , TR ₂ , TR ₃ , S, D, G, BC, Sub, NWELL, A ₁ , A ₂ , Chn, body) by an electrical insulation (ONO, GOX, TWD) of these parts is electrically isolated on the one hand and on the other thermally conductive at least one of these parts (TR ₁ , TR ₂ , TR ₃ , S, D, G, BC , Sub, NWELL, A ₁ , A ₂ , chn, body) of the MOS transistor (TR) is connected.

Characteristic 7

• - dass die Temperaturmessvorrichtung (TS) mindestens einen Poly-Silizium-NPN-Bipolartransistor oder mindestens einen Poly-Silizium-PNO-Bipolartransistor (Poly_T) insbesondere als temperaturempfindliches elektronisches Bauelement enthält.

Method according to one or more of the features 1 to 4 characterized,

• - That the temperature measuring device (TS) contains at least one poly-silicon NPN bipolar transistor or at least one poly-silicon PNO bipolar transistor (Poly_T) in particular as a temperature-sensitive electronic component.

Characteristic 8

• - dass der Bipolartransistor (Poly_T) bezüglich der elektrischen Leitfähigkeit und der Beeinflussung von Teilen des MOS-Transistors (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A₁, A₂, chn, body) durch eine elektrische Isolation (GOX, ONO, twd) von diesen Teilen (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A1, A2, chn, body) des MOS-Transistors (TR) zum einen elektrisch isoliert ist und zum anderen thermisch leitend an mindestens eines dieser Teile (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A₁, A₂, chn, body) des MOS-Transistors (TR) angebunden ist.

Method according to feature 7 characterized,

• that the bipolar transistor (poly_T) with respect to the electrical conductivity and the influence of parts of the MOS transistor (TR ₁ , TR ₂ , TR ₃ , S, D, G, BC, Sub, NWELL, A ₁ , A ₂ , chn, body) by an electrical insulation (GOX, ONO, twd) of these parts (TR ₁ , TR ₂ , TR ₃ , S, D, G, BC, Sub, NWELL, A1, A2, chn, body) of the MOS transistor (TR) is electrically isolated on the one hand and on the other hand thermally conductive at least one of these parts (TR ₁ , TR ₂ , TR ₃ , S, D, G, BC, Sub, NWELL, A ₁ , A ₂ , chn, body) of the MOS transistor (TR) is connected.

Characteristic 9

• - dass die Temperaturmessvorrichtung (TS) einen halbleitenden Widerstand als temperaturempfindliches Element enthält, der bezüglich der elektrischen Leitfähigkeit und der Beeinflussung von Teilen (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A₁, A₂, chn, body) des MOS-Transistors (TR) durch eine elektrische Isolation (twd, GOX, ONO) von diesen Teilen zum einen elektrisch isoliert ist und zum anderen thermisch leitend an mindestens eines dieser Teile des MOS-Transistors (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A₁, A₂, chn, body) angebunden ist.

Method according to one or more of the features 1 to 5 characterized,

• in that the temperature measuring device (TS) contains a semiconducting resistor as a temperature-sensitive element, which with respect to the electrical conductivity and the influencing of parts (TR ₁ , TR ₂ , TR ₃ , S, D, G, BC, Sub, NWELL, A ₁ , A ₂ , Chn, body) of the MOS transistor (TR) by an electrical insulation (twd, GOX, ONO) of these parts is electrically isolated on the one hand and on the other thermally conductive at least one of these parts of the MOS transistor (TR ₁ , TR ₂ , TR ₃ , S, D, G, BC, Sub, NWELL, A ₁ , A ₂ , chn, body).

Feature 10

• - dass der Abstand zwischen mindestens einem Teil (PSD) der Temperaturmessvorrichtung (TS, Poly_D, Poly_T, D₁, D₂, D₃) und mindestens einem Teil (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A₁, A₂, chn, body) des MOS-Transistors (TR) weniger als 800nm oder weniger als 400nm oder weniger als 200nm oder weniger als 100nm oder weniger als 50nm oder weniger als 20nm oder weniger als 10nm beträgt und
• - dass insbesondere der zugehörige Abstandsbereich mit einem elektrisch isolierenden und thermisch leitenden Dielektrikum, insbesondere SiO₂ und/oder Si₃N₄ gefüllt ist und insbesondere alternierenden Schichten dieser beiden gefüllt ist.

Method according to one or more of the features 1 to 9 characterized,

• - That the distance between at least a part (PSD) of the temperature measuring device (TS, Poly_D, Poly_T, D ₁ , D ₂ , D ₃ ) and at least one part (TR ₁ , TR ₂ , TR ₃ , S, D, G, BC , Sub, NWELL, A ₁ , A ₂ , chn, body) of the MOS transistor (TR) is less than 800 nm or less than 400 nm or less than 200 nm or less than 100 nm or less than 50 nm or less than 20 nm or less than 10 nm and
• - That in particular the associated distance range with an electrically insulating and thermally conductive dielectric, in particular SiO ₂ and / or Si ₃ N _{4 is} filled and in particular alternating layers of these two is filled.

Feature 11

• - wobei der MOS-Transistor (TR) zusammen mit mindestens einer Temperaturmessvorrichtung (TS, Poly_D, Poly_T, D₁, D₂, D₃) monolithisch auf einem Substrat (Sub) untergebracht ist und
• - wobei der MOS-Transistor (TR) aus einem oder mehreren Teiltransistoren (TR₁, TR₂, TR₃) besteht.

dadurch gekennzeichnet,

• - dass eine Temperaturmessvorrichtung (TS, Poly_D, Poly_T, D₁, D₂, D₃) in polykristallinem Silizium (PSD) gefertigt ist, das elektrisch von den Teilen (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A₁, A₂, chn, body) des MOS-Transistors (TR) und insbesondere von der Gate-Elektrode (G) des MOS-Transistors (TR) durch eine elektrische Isolation (GOX, ONO, twd) isoliert ist und
• - dass ein elektrischer Parameter (insbesondere Stromdurchfluss, Spannungsabfall, Kapazität, elektrischer komplexer und/oder realer Widerstand und Leitwert) der Temperaturmessvorrichtung (TS, Poly_D, Poly_T, D₁, D₂, D₃) erfasst wird, der als Messwert dient oder aus dem ein solcher Messwert abgeleitet wird und
• - dass die Temperaturmessvorrichtung (TS, Poly_D, Poly_T, D₁, D₂, D₃) in einer thermischen Verbindung zu diesem MOS-Transistor (TR) oder zu einem Teil (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A₁, A₂, chn, body) dieses MOS-Transistors (TR) steht, die dadurch gekennzeichnet ist, dass der besagte elektrische Parameter der Temperaturmessvorrichtung (TS, Poly_D, Poly_T, D₁, D₂, D₃) von der Temperatur zumindest eines Teils (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A₁, A₂, chn, body) des MOS-Transistors (TR) und/oder eines Teiltransistors (TR₁, TR₂, TR₃) des MOS-Transistors (TR) abhängt.

Method for regulating the temperature of a MOS transistor (TR), in particular a DMOS transistor,

• - wherein the MOS transistor (TR) is monolithically housed on a substrate (Sub) together with at least one temperature measuring device (TS, Poly_D, Poly_T, D ₁ , D ₂ , D ₃ ) and
• - Wherein the MOS transistor (TR) consists of one or more subtransistors (TR ₁ , TR ₂ , TR ₃ ).

characterized,

• a temperature measuring device (TS, Poly_D, Poly_T, D ₁ , D ₂ , D ₃ ) is produced in polycrystalline silicon (PSD) which is electrically connected to the parts (TR ₁ , TR ₂ , TR ₃ , S, D, G, BC, Sub, NWELL, A ₁ , A ₂ , chn, body) of the MOS transistor (TR) and in particular of the gate electrode (G) of the MOS transistor (TR) by an electrical insulation (GOX, ONO, twd ) is isolated and
• - That an electrical parameter (in particular current flow, voltage drop, capacitance, electrical complex and / or real resistance and conductance) of the temperature measuring device (TS, Poly_D, Poly_T, D ₁ , D ₂ , D ₃ ) is detected, which serves as a measured value or off which such a measured value is derived and
• - That the temperature measuring device (TS, Poly_D, Poly_T, D ₁ , D ₂ , D ₃ ) in a thermal connection to this MOS transistor (TR) or to a part (TR ₁ , TR ₂ , TR ₃ , S, D, G, BC, Sub, NWELL, A ₁ , A ₂ , chn, body) of this MOS transistor (TR), which is characterized in that said electrical parameter of the temperature measuring device (TS, Poly_D, Poly_T, D ₁ , D ₂ , D ₃ ) from the temperature of at least one part (TR ₁ , TR ₂ , TR ₃ , S, D, G, BC, Sub, NWELL, A ₁ , A ₂ , chn, body) of the MOS transistor (TR) and / or a partial transistor (TR ₁ , TR ₂ , TR ₃ ) of the MOS transistor (TR) depends.

Feature 12

• - dass die Temperaturmessvorrichtungen (TS, Poly_D, Poly_T, D₁, D₂, D₃) gleichmäßig und symmetrisch über den MOS-Transistor (TR) verteilt sind und
• - dass der MOS-Transistor (TR) ohne Verdrahtung mindestens eine Spiegelsymmetrieachse (Sym1) aufweist und
• - dass die Temperaturmessvorrichtungen (TS, Poly_D, Poly_T, D₁, D₂, D₃) spiegelsymmetrisch bezüglich zumindest dieser einen Spiegelsymmetrieachse (Sym1) oder auf dieser Symmetrieachse (Sym1) angeordnet sind.

Method according to feature 11 characterized,

• - That the temperature measuring devices (TS, Poly_D, Poly_T, D ₁ , D ₂ , D ₃ ) are evenly and symmetrically distributed over the MOS transistor (TR) and
• - That the MOS transistor (TR) without wiring has at least one mirror symmetry axis (Sym1) and
• - That the temperature measuring devices (TS, Poly_D, Poly_T, D ₁ , D ₂ , D ₃ ) are arranged mirror-symmetrically with respect to at least one of these mirror symmetry axis (Sym1) or on this symmetry axis (Sym1).

Feature 13

• - dass die Temperaturmessvorrichtung (TS, Poly_D, Poly_T, D₁, D₂, D₃)
• - eine zusätzliche Poly-Silizium-Elektrode (PSD) des MOS-Transistors (TR) oder eines Teiltransistors (TR₁, TR₂, TR₃) ist und
• - dass die zusätzliche Poly-Silizium-Elektrode (PSD) von der Gate-Elektrode (G) des Transistors und anderen Teilen (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A₁, A₂, chn, body) des MOS-Transistors (TR) elektrisch isoliert ist.

Method according to one or more of the features 11 to 12 characterized,

• that the temperature measuring device (TS, Poly_D, Poly_T, D ₁ , D ₂ , D ₃ )
• - Is an additional poly-silicon electrode (PSD) of the MOS transistor (TR) or a partial transistor (TR ₁ , TR ₂ , TR ₃ ) and
• that the additional poly-silicon electrode (PSD) from the gate electrode (G) of the transistor and other parts (TR ₁ , TR ₂ , TR ₃ , S, D, G, BC, Sub, NWELL, A ₁ , A ₂ , Chn, body) of the MOS transistor (TR) is electrically isolated.

Feature 14

• - dass der differentielle oder absolute elektrische Widerstand und oder die differentielle oder absolute Leitfähigkeit der zusätzlichen Poly-Silizium-Elektrode (PSD) oder eine von einem von diesen Größen abhängige Größe durch einen Messstrom (I_m) oder eine Messspannung zumindest zeitweise während des Betriebs des MOS-Transistors (TR) erfasst wird.

Method according to feature 13 characterized,

• - That the differential or absolute electrical resistance and or the differential or absolute conductivity of the additional poly-silicon electrode (PSD) or a dependent of these variables size by a measuring current (I _m ) or a measuring voltage at least temporarily during the operation of MOS transistor (TR) is detected.

Feature 15

• - dass die Gate-Elektrode (G) des MOS-Transistors (TR) so ausgeformt ist, dass es den Kanal (chn) des MOS-Transistors (TR) gegenüber dem elektrischen Feld der zusätzlichen Poly-Silizium-Elektrode (PSD) abschirmt und
• - dass die Ansteuerung der zusätzlichen Poly-Silizium-Elektrode (PSD) so langsam erfolgt, dass ein kapazitives Übersprechen zwischen der zusätzlichen Poly-Silizium-Elektrode (PSD) und der Gate-Elektrode (G) des MOS-Transistors (TR) eine Drain- und/oder Source-Stromänderung des MOS-Transistors (TR) von nicht mehr als 5% und oder nicht mehr als 2,5% und/oder nicht mehr als 1% zur Folge hat.

Method according to feature 13 or 14 characterized,

• - That the gate electrode (G) of the MOS transistor (TR) is formed so that it shields the channel (chn) of the MOS transistor (TR) against the electric field of the additional poly-silicon electrode (PSD) and
• - That the control of the additional poly-silicon electrode (PSD) is so slow that a capacitive crosstalk between the additional poly-silicon electrode (PSD) and the gate electrode (G) of the MOS transistor (TR) has a drain - And / or source current change of the MOS transistor (TR) of not more than 5% and or not more than 2.5% and / or not more than 1% result.

Feature 16

• - dass eine Temperaturmessvorrichtung (TS, D₁, D₂, D₃) eine aus polykristallinem Silizium gefertigte Poly-Silizium-PN-Diode (Poly_D) oder Poly-Silizium-PIN-Diode (Poly_D) ist.

Method according to one or more of the features 11 to 12 characterized,

• - That a temperature measuring device (TS, D ₁ , D ₂ , D ₃ ) is made of polycrystalline silicon poly-silicon PN diode (poly_D) or poly-silicon PIN diode (poly_D).

Feature 17

• - dass die Poly-Silizium-PN-Diode (Poly_D) oder Poly-Silizium-PIN-Diode (Poly_D) von der Gate-Elektrode (G) des MOS-Transistors (TR) und anderen Teilen (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A₁, A₂, chn, body) des MOS-Transistors (TR) elektrisch isoliert ist.

Method according to feature 16 characterized,

• - That the poly-silicon PN diode (poly_D) or poly-silicon PIN diode (poly_D) from the gate electrode (G) of the MOS transistor (TR) and other parts (TR ₁ , TR ₂ , TR ₃ , S, D, G, BC, Sub, NWELL, A ₁ , A ₂ , chn, body) of the MOS transistor (TR) is electrically isolated.

Feature 18

• - dass die Poly-Silizium-PN-Diode (Poly_D) oder Poly-Silizium-PIN-Diode (Poly_D) von den elektrischen Komponenten (S, D, G, BC, Sub, NWELL, chn, body) des MOS-Transistors (TR), die im Substratmaterial (Sub) - insbesondere im Wafer-Material -, aus dem der MOS-Transistor (TR) gefertigt ist, selbst oder isoliert davon ausgebildet sind, insbesondere von den Source- (S) und Drain-(D) Kontakten und dem Kanal (chn) des MOS-Transistors (TR) und der p⁺-Implantation (body) (bei einem PNP-DMOS-Transistor eine n⁺-Implantation (body)) und der N-Wanne (NWELL) (bei einem PNP-DMOS-Transistor eine p-Wanne oder ein p-Substrat) und dem p⁺⁺-Wannenkontakt (BC) (bei einem PNP-DMOS-Transistor ein n⁺⁺-Wannenkontakt), abgesehen von der eigenen Verdrahtung innerhalb einer Verschaltung (16) elektrisch isoliert ist.

1Procedure according to characteristic 16 or 17 characterized,

• that the poly-silicon PN diode (poly_D) or poly-silicon PIN diode (poly_D) from the electrical components (S, D, G, BC, sub, NWELL, CHN, body) of the MOS transistor ( TR) formed in the substrate material (Sub) - especially in the wafer material - from which the MOS transistor (TR) is made, itself or isolated therefrom, in particular from the source (S) and drain (D) Contacts and the channel (chn) of the MOS transistor (TR) and the p ⁺ implantation (body) (in the case of a PNP-DMOS transistor an n ⁺ -implantation (body)) and the N-well (NWELL) (at a p-well or a p-type substrate) and the p ^{++ well} contact (BC) (in the case of a PNP-DMOS transistor, an n ^{++ well} contact), apart from its own wiring within an interconnect ( 16 ) is electrically isolated.

Feature 19

• - dass der elektrische differentielle oder absolute Leitwert oder Widerstand oder eine diesen entsprechende physikalische Größe der Poly-Silizium-PN-Diode (Poly_D) oder Poly-Silizium-PIN-Diode (Poly_D) durch einen Messstrom (I_m) oder eine Messspannung als elektrischer Parameter erfasst wird.

Method according to one or more of the features 16 to 18 characterized,

• - That the electrical differential or absolute conductance or resistance or a corresponding physical size of the poly-silicon PN diode (poly_D) or poly-silicon PIN diode (poly_D) by a measuring current (I _m ) or a measuring voltage as electrical Parameter is detected.

Feature 20

• - dass zumindest ein Teil der Gate-Elektrode (G) des MOS-Transistors (TR) so ausgeformt ist, dass sie den Kanal (chn) des MOS-Transistors (TR) gegenüber dem elektrischen Feld der Poly-Silizium-PN-Diode (Poly_D) bzw. Poly-Silizium-PIN-Diode (Poly_D) abschirmt und
• - dass die Ansteuerung der Poly-Silizium-PN-Diode (Poly_D) oder Poly-Silizium-PIN-Diode (Poly_D) so langsam erfolgt, dass ein kapazitives Übersprechen zwischen der Poly-Silizium-PN-Diode (Poly_D) (bzw. Poly-Silizium-PIN-Diode (Poly_D)) und der Gate-Elektrode (G) des MOS-Transistors (TR) eine Drain- oder Source-Stromänderung des MOS-Transistors (TR) von nicht mehr als 5% und oder nicht mehr als 2,5% und/oder nicht mehr als 1% zur Folge hat.

Method according to one or more of the features 16 to 18 characterized,

• in that at least a part of the gate electrode (G) of the MOS transistor (TR) is shaped such that it covers the channel (chn) of the MOS transistor (TR) with respect to the electric field of the polysilicon PN diode (FIG. Poly_D) or poly-silicon PIN diode (poly_D) shields and
• - That the control of the poly-silicon PN diode (poly_D) or poly-silicon PIN diode (poly_D) is so slow that a capacitive crosstalk between the poly-silicon PN diode (poly_D) (or poly Silicon PIN diode (Poly_D)) and the gate electrode (G) of the MOS transistor (TR), a drain or source current change of the MOS transistor (TR) of not more than 5% and or not more than 2.5% and / or not more than 1%.

Characteristic 21

• - dass eine Temperaturmessvorrichtung (TS, D₁, D₂, D₃) eine aus polykristallinem Silizium gefertigter Poly-Silizium-PNP-Transistor oder Poly-Silizium-NPN-Transistor (Poly_T) ist.

Method according to one or more of the features 11 to 12 characterized,

• - That a temperature measuring device (TS, D ₁ , D ₂ , D ₃ ) is made of polycrystalline silicon poly-silicon PNP transistor or poly-silicon NPN transistor (poly_T).

Feature 22

• - dass der Poly-Silizium-PNP-Transistor oder Poly-Silizium-NPN-Transistor (Poly_T) von der Gate-Elektrode (G) des MOS-Transistors (TR) und anderen Teilen (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A₁, A₂, chn, body) des MOS-Transistors (TR) elektrisch isoliert ist.

Method according to feature 21 characterized,

• - That the poly-silicon PNP transistor or poly-silicon NPN transistor (poly_T) of the gate electrode (G) of the MOS transistor (TR) and other parts (TR ₁ , TR ₂ , TR ₃ , S , D, G, BC, Sub, NWELL, A ₁ , A ₂ , chn, body) of the MOS transistor (TR) is electrically isolated.

Characteristic 23

• - dass der Poly-Silizium-PNP-Transistor oder Poly-Silizium-NPN-Transistor (Poly_T) von den elektrischen Komponenten (S, D, G, BC, Sub, NWELL, chn, body) des MOS-Transistors (TR), die im Substratmaterial (Sub) - insbesondere im Wafer-Material -, aus dem der MOS-Transistor (TR) gefertigt ist, selbst oder isoliert davon ausgebildet sind, insbesondere von den Source- (S) und Drain-(D) Kontakten und dem Kanal (chn) des MOS-Transistors (TR) und der p⁺-Implantation (body) (bei einem PNP-DMOS-Transistor eine n⁺-Implantation (body)) und der N-Wanne (NWELL) (bei einem PNP-DMOS-Transistor eine p-Wanne oder ein p-Substrat) und dem p⁺⁺-Wannenkontakt (BC) (bei einem PNP-DMOS-Transistor ein n⁺⁺-Wannenkontakt), abgesehen von der eigenen Verdrahtung innerhalb einer Verschaltung (16) elektrisch isoliert ist.

Method according to feature 21 or 22 characterized,

• that the poly-silicon PNP transistor or poly-silicon NPN transistor (poly_T) from the electrical components (S, D, G, BC, Sub, NWELL, CHN, body) of the MOS transistor (TR), formed in the substrate material (Sub) - in particular in the wafer material - from which the MOS transistor (TR) is made, itself or isolated therefrom, in particular from the source (S) and drain (D) contacts and Channel (chn) of the MOS transistor (TR) and the p ⁺ implantation (body) (in the case of a PNP-DMOS transistor an n ⁺ -implantation (body)) and the N-well (NWELL) (in the case of a PNP DMOS transistor a p-well or a p-type substrate) and the p ^{++ well} contact (BC) (in the case of a PNP-DMOS transistor, an n ^{++ well} contact), apart from its own wiring within an interconnection ( 16 ) is electrically isolated.

Characteristic 24

• - dass der elektrische differentielle oder absolute Leitwert oder Widerstand oder eine diesen entsprechende physikalische Größe des Poly-Silizium-PNP-Transistor oder Poly-Silizium-NPN-Transistor (Poly_T) durch einen Messstrom (I_m) oder eine Messspannung in einem oder mehreren Arbeitspunkten des Poly-Silizium-PNP-Transistors oder Poly-Silizium-NPN-Transistors (Poly_T) als elektrischer Parameter erfasst wird.

Method according to one or more of the features 21 to 23 characterized,

• - in that the electrical differential or absolute conductance or resistance or a physical variable corresponding thereto of the poly-silicon PNP transistor or poly-silicon NPN transistor (Poly_T) is determined by a measurement current (I _m ) or a measurement voltage at one or more operating points of the Poly-silicon PNP transistor or poly-silicon NPN transistor (poly_T) is detected as an electrical parameter.

Characteristic 25

• - dass zumindest ein Teil der Gate-Elektrode (G) des MOS-Transistors (TR) so ausgeformt ist, dass sie den Kanal (chn) des MOS-Transistors (TR) gegenüber dem elektrischen Feld de Poly-Silizium-PNP-Transistors oder Poly-Silizium-NPN-Transistors (Poly_T) abschirmt, und
• - dass die Ansteuerung des Poly-Silizium-PNP-Transistors oder Poly-Silizium-NPN-Transistors (Poly_T) so langsam erfolgt, dass ein kapazitives Übersprechen zwischen dem Poly-Silizium-PNP-Transistor oder Poly-Silizium-NPN-Transistor (Poly_T)auf der einen Seite und der Gate-Elektrode (G) des MOS-Transistors (TR) auf der anderen Seite eine Drain- oder Source-Stromänderung des MOS-Transistors (TR) von nicht mehr als 5% und oder nicht mehr als 2,5% und/oder nicht mehr als 1% zur Folge hat.

Method according to one or more of the features 21 to 24 characterized,

• - That at least a portion of the gate electrode (G) of the MOS transistor (TR) is formed so that the channel (CHN) of the MOS transistor (TR) opposite the electric field of the poly-silicon PNP transistor or Poly-silicon NPN transistor (Poly_T) shields, and
• - That the control of the poly-silicon PNP transistor or poly-silicon NPN transistor (poly_T) is so slow that a capacitive crosstalk between the poly-silicon PNP transistor or poly-silicon NPN transistor (poly_T ) on the one side and the gate electrode (G) of the MOS transistor (TR) on the other side, a drain or source current change of the MOS transistor (TR) of not more than 5% and or not more than 2 , 5% and / or not more than 1%.

Feature 26

• - einem oder mehreren, insbesondere parallel oder quadratisch zueinander angeordneten Teiltransistoren (TR₁, TR₂, TR₃) und
• - mindestens einer Symmetrieachse (Sym1) gekennzeichnet dadurch,
• - dass zumindest einer der besagten Teiltransistoren (TR₁) durch die Temperaturmessvorrichtung (TS) unterbrochen oder gekürzt gegenüber mindestens einem anderen Teiltransistor(TR₂, TR₃) ist und
• - dass die Temperaturmessvorrichtung (TS) gegenüber den elektrischen Komponenten des MOS-Transistors (S, D, G, BC, Sub, NWELL, chn, body), die im Substratmaterial (Sub) - insbesondere im Wafer-Material -, aus dem der MOS-Transistor (TR) gefertigt ist, selbst oder isoliert davon ausgebildet sind, insbesondere von den Source- (S) und Drain- (D) Kontakten und dem Kanal (chn) des MOS-Transistors (TR) und der p⁺-Implantation (body) (bei einem PNP-DMOS-Transistor eine n⁺-Implantation (body)) und der N-Wanne (NWELL) (bei einem PNP-DMOS-Transistor eine p-Wanne oder ein p-Substrat) und dem p⁺⁺-Wannenkontakt (BC) (bei einem PNP-DMOS-Transistor ein n⁺⁺-Wannenkontakt), abgesehen von der eigenen Verdrahtung innerhalb einer Verschaltung (16) elektrisch isoliert ist und
• - mit diesem MOS-Transistor (TR) oder Teilen (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A₁, A₂, chn, body) dieses MOS-Transistors (TR) thermisch leitend thermisch verbunden ist.

MOS transistor (TR) in particular for an integrated circuit with

• - One or more, in particular parallel or square to each other arranged subtransistors (TR ₁ , TR ₂ , TR ₃ ) and
• at least one symmetry axis (Sym1) characterized by
• - That at least one of said subtransistors (TR ₁ ) by the temperature measuring device (TS) is interrupted or shortened against at least one other subtransistor (TR ₂ , TR ₃ ) and
• - That the temperature measuring device (TS) relative to the electrical components of the MOS transistor (S, D, G, BC, Sub, NWELL, chn, body), in the substrate material (Sub) - in particular in the wafer material -, from the MOS transistor (TR) is made, itself or isolated therefrom, in particular of the source (S) and drain (D) contacts and the channel (chn) of the MOS transistor (TR) and the p ⁺ implantation (body) (in a PNP-DMOS transistor an n ⁺ implant (body)) and the N-well (NWELL) (in a PNP-DMOS transistor a p-well or a p-substrate) and the p ^{+ +} -Wannkontakt (BC) (in the case of a PNP-DMOS transistor, an n ⁺⁺ -well contact), apart from the own wiring within an interconnection ( 16 ) is electrically isolated and
• with this MOS transistor (TR) or parts (TR ₁ , TR ₂ , TR ₃ , S, D, G, BC, Sub, NWELL, A ₁ , A ₂ , chn, body) of this MOS transistor (TR) thermally conductive thermally connected.

Feature 26b

• - dass symmetrisch zu der Symmetrieachse (Sym1) und/oder auf dieser sich zumindest eine Temperaturmessvorrichtung (TS) befindet.

MOS transistor (TR) in particular for an integrated circuit by feature 26 Characterized,

• - That at least one temperature measuring device (TS) is located symmetrically to the axis of symmetry (Sym1) and / or on this.

Characteristic 27

• - dass die Temperaturmessvorrichtung (TS) eine Poly-Silizium-PN-Diode (Poly_D) oder eine Poly-Silizium-PIN-Diode (Poly_D) oder ein Poly-Silizium-PNP-Transistor (Poly_T) oder ein Poly-Silizium-NPN-Transistor ist und
• - dass die Temperaturmessvorrichtung (TS) gegenüber den elektrischen Komponenten (S, D, G, BC, Sub, NWELL, chn, body) des MOS-Transistors (TR), die im Substratmaterial (Sub) - insbesondere im Wafer-Material -, aus dem der MOS-Transistor (TR) gefertigt ist, selbst oder isoliert davon ausgebildet sind, insbesondere von den Source- (S) und Drain-(D) Kontakten und dem Kanal (chn) des MOS-Transistors (TR) und der p⁺-Implantation (body) (bei einem PNP-DMOS-Transistor eine n⁺-Implantation (body)) und der N-Wanne (NWELL) (bei einem PNP-DMOS-Transistor eine p-Wanne oder ein p-Substrat) und dem p⁺⁺-Wannenkontakt (BC) (bei einem PNP-DMOS-Transistor ein n⁺⁺-Wannenkontakt), abgesehen von der eigenen Verdrahtung innerhalb einer Verschaltung (16) elektrisch isoliert ist und
• - mit diesem MOS-Transistor (TR) oder Teilen (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A₁, A₂, chn, body) dieses MOS-Transistors (TR) thermisch leitend thermisch verbunden ist.

Temperature measuring device (TS) within an integrated circuit for use in, or in operative connection with, a MOS transistor (TR) of the integrated circuit for sensing the temperature of one or more MOS transistors (TR) during operation, in particular one of the features 26 or 26b characterized by

• the temperature measuring device (TS) has a poly-silicon PN diode (poly_D) or a poly-silicon PIN diode (poly_D) or a poly-silicon PNP transistor (poly_T) or a poly-silicon NPN Transistor is and
• that the temperature measuring device (TS) relative to the electrical components (S, D, G, BC, Sub, NWELL, CHn, body) of the MOS transistor (TR), in the substrate material (Sub) - in particular in the wafer material -, from which the MOS transistor (TR) is made, itself or isolated therefrom, in particular from the source (S) and drain (D) contacts and the channel (chn) of the MOS transistor (TR) and the p ⁺ Implantation (body) (in a PNP-DMOS transistor an n ⁺ implantation (body)) and the N-well (NWELL) (in the case of a PNP-DMOS transistor a p-well or a p-substrate) and the p ^{++ well} contact (BC) (in the case of a PNP DMOS transistor, an n ^{++ well} contact), apart from its own wiring within an interconnection ( 16 ) is electrically isolated and
• with this MOS transistor (TR) or parts (TR ₁ , TR ₂ , TR ₃ , S, D, G, BC, Sub, NWELL, A ₁ , A ₂ , chn, body) of this MOS transistor (TR) thermally conductive thermally connected.

Characteristic 28

• - dass das polykristalline Silizium (PSD) der Temperaturmessvorrichtung (TS) bei der Fertigung der Temperaturmessvorrichtung (TS) zusammen mit dem polykristallinen Silizium einer Gate-Elektrode (G) des MOS-Transistors (TR) zu zumindest einem Zeitpunkt eine gemeinsame polykristalline Siliziumschicht bildete.

Temperature measuring device (TS) according to feature 27
characterized,

• - That the polycrystalline silicon (PSD) of the temperature measuring device (TS) in the manufacture of the temperature measuring device (TS) together with the polycrystalline silicon of a gate electrode (G) of the MOS transistor (TR) at least one time a common polycrystalline silicon layer formed.

Characteristic 29

• - dass der Abstand (d) des polykristallinen Siliziums (PSD) der Temperaturmessvorrichtung (TS) zu einem Teil (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A₁, A₂, chn, body) des MOS-Transistors (TR) weniger als 200nm oder weniger als 100nm oder weniger als 50nm, oder weniger als 20nm oder weniger als 10nm beträgt.

Temperature measuring device (TS) according to feature 27 or 28
characterized,

• - That the distance (d) of the polycrystalline silicon (PSD) of the temperature measuring device (TS) to a part (TR ₁ , TR ₂ , TR ₃ , S, D, G, BC, Sub, NWELL, A ₁ , A ₂ , chn , body) of the MOS transistor (TR) is less than 200 nm or less than 100 nm or less than 50 nm, or less than 20 nm or less than 10 nm.

Feature 30

• - dass der Abstand (d) des polykristallinen Siliziums (PSD) der Temperaturmessvorrichtung (TS) zu dem Substratmaterial (Sub), insbesondere dem Wafer-Material, in dem die halbleitenden und einkristallinen Teile (S, D, G, BC, Sub, NWELL, chn, body) des MOS-Transistors (TR) gefertigt sind, insbesondere zu dem Substrat (Sub), weniger als 800nm oder weniger als 400nm oder weniger als 200nm oder weniger als 100nm oder weniger als 50nm oder weniger als 20nm oder weniger als 10nm beträgt.

Temperature measuring device (TS) according to feature 27 or 28
characterized,

• - That the distance (d) of the polycrystalline silicon (PSD) of the temperature measuring device (TS) to the substrate material (Sub), in particular the wafer material in which the semiconducting and monocrystalline parts (S, D, G, BC, Sub, NWELL , chn, body) of the MOS transistor (TR), in particular to the substrate (Sub), less than 800 nm or less than 400 nm or less than 200 nm or less than 100 nm or less than 50 nm or less than 20 nm or less than 10 nm is.

Characteristic 31

• - dass das polykristalline Silizium (PSD) der Temperaturmessvorrichtung (TS) von dem Substratmaterial (Sub), insbesondere dem Wafer-Material, in dem die halbleitenden und einkristallinen Teile (S, D, G, BC, Sub, NWELL, chn, body) des MOS-Transistors (TR) gefertigt sind, insbesondere von dem Substrat (Sub),
• - durch ein Gate-Oxid (GOX) elektrisch isoliert ist und/oder
• - insbesondere durch ein Dielektrikum elektrisch isoliert ist, dessen Dicke weniger als 200nm oder weniger als 100nm oder weniger als 50nm oder weniger als 20nm oder weniger als 10nm beträgt.

Temperature measuring device (TS) according to feature 30
characterized,

• that the polycrystalline silicon (PSD) of the temperature measuring device (TS) of the substrate material (Sub), in particular the wafer material in which the semiconducting and monocrystalline parts (S, D, G, BC, Sub, NWELL, chn, body) of the MOS transistor (TR), in particular of the substrate (Sub),
• - Is electrically insulated by a gate oxide (GOX) and / or
• - Is electrically insulated in particular by a dielectric whose thickness is less than 200nm or less than 100nm or less than 50nm or less than 20nm or less than 10nm.

Characteristic 32

• - dass mindestens ein bipolares elektronisches Bauelement (Poly_D, Poly_T) in einem der Bauteile (TR₁, TR₂, TR₃, G, BC, PSD, Sub, NWELL, A₁, A₂) des MOS-Transistors (TR),
  1. a. in unmittelbarer Nähe eines Bauteiles (TR₁, TR₂, TR₃, S, D, G, BC, Sub, NWELL, A₁, A₂, chn, body) des MOS-Transistors (TR) oder
  2. b. insbesondere in der Nähe einer Gate-Elektrode (G) des MOS-Transistors (TR) oder
  3. c. insbesondere innerhalb des Materials einer der Gate-Elektroden (G) des MOS-Transistors (TR)
     • - aus polykristallinem Silizium (PSD) thermisch mit diesem MOS-Transistor (TR) verbunden gefertigt ist,
     • - wobei Nähe in den Fällen a) und b) einen Abstand (d) von weniger als 800nm oder weniger als 400nm oder weniger als 200nm oder weniger als 100nm oder weniger als 50nm oder weniger als 20nm oder weniger als 10nm zwischen dem bipolaren elektronischen Bauelement (Poly_D, Poly_T) und einem Bauteil (TR1, TR2, TR3, S, D, G, BC, Sub, NWELL, A1, A2, chn, body) des MOS-Transistors (TR) bedeutet.

MOS transistor (TR), in particular for an integrated circuit
characterized by

• at least one bipolar electronic component (Poly_D, Poly_T) in one of the components (TR ₁ , TR ₂ , TR ₃ , G, BC, PSD, Sub, NWELL, A ₁ , A ₂ ) of the MOS transistor (TR),
  1. a. in the immediate vicinity of a component (TR ₁ , TR ₂ , TR ₃ , S, D, G, BC, Sub, NWELL, A ₁ , A ₂ , chn, body) of the MOS transistor (TR) or
  2. b. in particular in the vicinity of a gate electrode (G) of the MOS transistor (TR) or
  3. c. in particular within the material of one of the gate electrodes (G) of the MOS transistor (TR)
     • made of polycrystalline silicon (PSD) thermally connected to this MOS transistor (TR),
     • in the cases a) and b), a distance (d) of less than 800 nm or less than 400 nm or less than 200 nm or less than 100 nm or less than 50 nm or less than 20 nm or less than 10 nm between the bipolar electronic component ( Poly_D, poly_T) and a component (TR1, TR2, TR3, S, D, G, BC, sub, NWELL, A1, A2, chn, body) of the MOS transistor (TR) means.

Characteristic 33

• - dass der MOS-Transistor (TR) in einem CMOS-Prozess mit zwei polykristallinen Siliziumlagen gefertigt ist und
• - dass eine Gate-Elektrode (G) des MOS-Transistors (TR) in einer ersten polykristallinen Siliziumlage gefertigt ist und
• - dass das bipolare elektronische Bauelement (Poly_D, Poly_T) in einer zweiten polykristallinen Siliziumlage gefertigt ist.

MOS transistor (TR) according to feature 32
characterized by

• - That the MOS transistor (TR) is made in a CMOS process with two polycrystalline silicon layers and
• - That a gate electrode (G) of the MOS transistor (TR) is made in a first polycrystalline silicon layer, and
• - That the bipolar electronic component (poly_D, poly_T) is made in a second polycrystalline silicon layer.

Characteristic 34

• - dass das bipolare elektronisches Bauelement (Poly_D) in einem ersten positiven Abstand (a) von der source-seitigen Kante der Gate-Elektrode (G) des MOS-Transistors (TR) gefertigt ist und in einem positiven zweiten Abstand (c) von der drain-seitigen Kante der Gate-Elektrode (G) des MOS-Transistors (TR) gefertigt ist und
• - dass die Gate-Elektrode (G) des MOS-Transistors (TR) das elektrische Feld des bipolaren elektronischen Bauelements (Poly_D, Poly_T) so abschirmt, dass bei dem bestimmungsgemäßen Gebrauch des bipolaren elektronischen Bauelements (Poly_D, Poly_T) der Drain- oder Source-Strom des MOS-Transistors (TR) sich um nicht mehr als 5% und oder nicht mehr als 2,5% und/oder nicht mehr als 1% ändert.

34. MOS transistor (TR) according to feature 33
characterized,

• - in that the bipolar electronic component (poly_D) is manufactured at a first positive distance (a) from the source-side edge of the gate electrode (G) of the MOS transistor (TR) and at a positive second distance (c) from the drain side edge of the gate electrode (G) of the MOS transistor (TR) is manufactured and
• - That the gate electrode (G) of the MOS transistor (TR) shields the electric field of the bipolar electronic component (poly_D, poly_T) so that in the intended use of the bipolar electronic component (poly_D, poly_T) of the drain or source Current of the MOS transistor (TR) does not change by more than 5% and / or not more than 2.5% and / or not more than 1%.

Feature 35

• - dass das bipolare elektronisches Bauelement (Poly_D) in einem CMOS-Prozess in polykristallinem Silizium gefertigt ist und
• - dass es zumindest einen n-dotierten Bereich (n_poly_a, n_poly_b) aufweist und
• - dass es zumindest einen p-dotierten Bereich (p_poly_a, p_poly_b) aufweist und
• - dass ein Stromfluss bei Anlegen einer Spannung von dem p-dotierten Bereich (p_ploy_a, p_poly_b) in den n-dotierten Bereich (n_poly_a, n_poly_b) möglich ist und
• - dass das Bauelement bei Nichtberücksichtigung seiner Verdrahtung ohne diese elektrisch isoliert gegenüber anderen Bauelementen ist.

35. Bipolar electronic device (Poly_D, Poly_T)
characterized,

• - That the bipolar electronic component (poly_D) is made in a CMOS process in polycrystalline silicon, and
• - That it has at least one n-doped region (n_poly_a, n_poly_b) and
• - That it has at least one p-doped region (p_poly_a, p_poly_b) and
• - That a current flow upon application of a voltage from the p-doped region (p_ploy_a, p_poly_b) in the n-doped region (n_poly_a, n_poly_b) is possible, and
• - That the component without taking into account its wiring without this is electrically isolated from other components.

Feature 36

• - dass es zumindest einen schwach oder undotierten Bereich (i_poly_a, i_poly_b) aufweist, wobei schwach dotiert bedeutet, dass die Dotierung in diesem Bereich schwächer als in dem n-dotierten Bereich (n_poly_a, n_poly_b) oder dem p-dotierten Bereich (p_poly_a, p_poly_b) ist.

Bipolar electronic component (Poly_D, Poly_T) according to feature 35
characterized,

• that it has at least one weak or undoped region (i_poly_a, i_poly_b), where weakly doped means that the doping is weaker in this region than in the n-doped region (n_poly_a, n_poly_b) or the p-doped region (p_poly_a, p_poly_b ).

Characteristic 37

• - dass ein schwach oder undotierter Bereich (i_poly_a, i_poly_b) zwischen mindestens einem n-dotierten Bereich (n_poly_a, n_poly_b) und mindestens einem p-dotierten Bereich (p_poly_a, p_poly_b) angeordnet ist, wobei die Dotierung des n-dotierten Bereichs (n_poly_a, n_poly_b) oder des p-dotierten Bereichs (p_poly_a, p_poly_b) höher ist als die des schwach oder undotierter Bereichs (i_poly_a, i_poly_b).

Bipolar electronic component (Poly_D, Poly_T) according to one or more of the features 35 to 36 , characterized,

• a weak or undoped region (i_poly_a, i_poly_b) is arranged between at least one n-doped region (n_poly_a, n_poly_b) and at least one p-doped region (p_poly_a, p_poly_b), the doping of the n-doped region (n_poly_a, n_poly_b) or the p-doped region (p_poly_a, p_poly_b) is higher than that of the weak or undoped region (i_poly_a, i_poly_b).

Characteristic 38

• - dass es sich um eine Poly-Silizium-PN-Diode (Poly_D) handelt.

Bipolar electronic component (poly_D) according to one or more of the features 35 to 37
characterized,

• - That it is a poly-silicon PN diode (poly_D).

Characteristic 39

• - dass es sich um eine Poly-Silizium-PIN-Diode (Poly_D) handelt.

Bipolar electronic component (poly_D) according to one or more of the features 35 to 38
characterized,

• - That it is a poly-silicon PIN diode (poly_D).

Feature 40

• - dass es sich um einen Poly-Silizium-NPN-Transistor (einen NPN-Transistor) oder
• - dass es sich um einen Poly-Silizium-PNP-Transistor (einen PNP-Transistor) (Poly_T) handelt.

Bipolar electronic component (Poly_T) according to one or more of the features 35 to 39
characterized,

• that it is a poly-silicon NPN transistor (an NPN transistor) or
• that it is a poly-silicon PNP transistor (a PNP transistor) (poly_T).

Feature 41

• - dass es über - insbesondere mit Titansilizid - elektrisch leitfähiges silizidiertes Silizium angeschlossen ist.

Bipolar electronic component (Poly_D, Poly_T) according to one or more of the features 35 to 38
characterized,

• - That it is connected via - in particular with titanium silicide - electrically conductive silicided silicon.

Feature 42

• - dass es über - insbesondere mit Titansilizid - elektrisch leitfähiges silizidiertes Silizium mit mindestens einem weiteren elektronischen Bauelement auf der Basis polykristallinen Siliziums verbunden ist.

Bipolar electronic component (Poly_D, Poly_T) according to one or more of the features 35 to 41
characterized,

• - That it is connected via - in particular with titanium silicide - electrically conductive silicided silicon with at least one further electronic component based on polycrystalline silicon.

Characteristic 43

• - dass es über - insbesondere mit Titansilizid - elektrisch leitfähiges silizidiertes Silizium mit mindestens einem weiteren bipolaren elektronischen Bauelement (Poly_Db) entsprechend einem oder mehreren der Merkmale 35 bis 42 elektrisch verbunden ist.

Bipolar electronic component (poly_Da) according to one or more of the features 35 to 42
characterized,

• in that it comprises - in particular with titanium silicide - electrically conductive silicided silicon with at least one further bipolar electronic component (Poly_Db) in accordance with one or more of the features 35 to 42 electrically connected.

Feature 44

• - dass es über ein thermisches Fenster (twd) thermisch mit dem Substrat (Sub) eines MOS-Transistors (TR) oder einem in einem solchen Substrat (Sub) gefertigten Teil eines solchen MOS-Transistors (TR) (S, D, G, BC, NWELL, chn, body) verbunden ist und
• - dass das thermische Fenster (twd)
  • ○ durch ein Gate-Oxid (GOX) elektrisch isolierend gebildet wird und/oder
  • ○ durch ein Dielektrikum gebildet wird, dass das elektrisch isolierend ist und dessen Dicke weniger als 200nm oder weniger als 100nm oder weniger als 50nm oder weniger als 20nm oder weniger als 10nm beträgt.

Bipolar electronic component (Poly_D, Poly_T, D1, D2, D3) according to one or more of the features 35 to 43
characterized,

• in that it is thermally thermally connected to the substrate (Sub) of a MOS transistor (TR) or a part of such a MOS transistor (TR) (S, D, G) made in such a substrate (Sub) via a thermal window (twd) BC, NWELL, chn, body) and
• - that the thermal window (twd)
  • Is formed by a gate oxide (GOX) electrically insulating and / or
  • ○ is formed by a dielectric that is electrically insulating and its thickness is less than 200nm or less than 100nm or less than 50nm or less than 20nm or less than 10nm.

Feature 45

• - dass das bipolare elektronische Bauelement (Poly_Da) oberhalb der Gate-Elektrode (G) eines MOS-Transistors (TR) gefertigt ist, wenn das Substrat (Sub) unten angeordnet wird oder ist.

Bipolar electronic component (poly_Da) according to one or more of the features 35 to 44
characterized,

• - That the bipolar electronic component (poly_Da) is made above the gate electrode (G) of a MOS transistor (TR) when the substrate (Sub) is arranged or is below.

Feature 46

• - Dass der Schaltkreis aus zumindest zwei elektronischen Bauelementen besteht, von denen mindestens eines ein Bipolares elektronisches Bauelement (Poly_Da) entsprechend einem oder mehreren der Merkmale 35 bis 45 ist und
• - dass diese beiden elektronischen Bauelemente durch mindestens eine elektrische Leitung aus -insbesondere mittels Titansilizid - elektrisch leitend slizidiertem Silizium elektrisch verbunden sind.

Electronic circuit manufactured in a CMOS process,
characterized,

• - That the circuit consists of at least two electronic components, of which at least one bipolar electronic component (poly_Da) according to one or more of the features 35 to 45 is and
• - That these two electronic components are electrically connected by at least one electrical line made of - in particular by means of titanium silicide - electrically conductive slizidiertem silicon.

Characteristic 47

• - dass der Schaltkreis aus einer gemeinsamen polykristallinen Siliziumschicht gefertigt ist.

Electronic circuit, manufactured in a CMOS process, according to feature 46
characterized,

• - That the circuit is made of a common polycrystalline silicon layer.

Feature 48

• - dass das zweite elektronische Bauteil ein elektrischer Widerstand ist, der in dem CMOS-Prozess in polykristallinem Silizium gefertigt ist und
• - dass es einen n-dotierten oder p-dotierten Bereich (n_poly_a, n_poly_b) aufweist
• - dass dieses zweite elektronische Bauelement bei Nichtberücksichtigung seiner Verdrahtung ohne diese elektrisch isoliert gegenüber anderen Bauelementen ist.

Electronic circuit fabricated in a CMOS process, according to one or more of the features 46 to 47
characterized,

• - That the second electronic component is an electrical resistance, which is made in the CMOS process in polycrystalline silicon and
• that it has an n-doped or p-doped region (n_poly_a, n_poly_b)
• - That this second electronic component, ignoring its wiring without this is electrically isolated from other components.

Characteristic 49

• - dass das zweite elektronische Bauteil ein bipolares Bauelement entsprechend einem oder mehreren der Merkmale 35 bis 45 ist.

Electronic circuit fabricated in a CMOS process, according to one or more of the features 46 to 48
characterized,

• - That the second electronic component is a bipolar device according to one or more of the features 35 to 45 is.

Claims (3)

Bipolar electronic component (Poly_T), characterized in that the bipolar electronic component (poly_T) is manufactured in a CMOS process in polycrystalline silicon and that it has at least one n-doped region (n_poly_a, n_poly_b) and that it has at least one has p-doped region (p_poly_a, p_poly_b) and • that a current flow when applying a voltage from the p-doped region (p_ploy_a, p_poly_b) in the n-doped region (n_poly_a, n_poly_b) is possible, and • that the component without regard to its wiring without these is electrically isolated from other components, and • that it is a poly-silicon NPN transistor or • that it is a poly-silicon PNP transistor (poly_T). Bipolar electronic component (Poly_D, Poly_T), characterized in that • the bipolar electronic component (poly_D) is manufactured in a CMOS process in polycrystalline silicon and • that it has at least one n-doped region (n_poly_a, n_poly_b) and that it at least one p-doped region (p_poly_a, p_poly_b) and • that a current flow upon application of a voltage from the p-doped region (p_ploy_a, p_poly_b) in the n-doped region (n_poly_a, n_poly_b) is possible and that the device disregarding its wiring without it is electrically isolated from other components and • that it thermally via a thermal window (twd) with the substrate (Sub) of a MOS transistor (TR) or in such a substrate (Sub) manufactured part of such MOS transistor (TR) (S, D, G, BC, NWELL, chn, body) and • that the thermal window (twd) a. is formed by an electrically insulating gate oxide (GOX) and / or b. is formed by a dielectric such that it is electrically insulating and its thickness is less than 200 nm or less than 100 nm or less than 50 nm or less than 20 nm or less than 10 nm. Bipolar electronic component (poly_Da) characterized in that • the bipolar electronic component (poly_Da) is manufactured in a CMOS process in polycrystalline silicon and • that it has at least one n-doped region (n_poly_a, n_poly_b) and that it has at least one Having a p-type region (p_poly_a, p_poly_b), and • that a current flow when applying a voltage from the p-doped region (p_ploy_a, p_poly_b) in the n-doped region (n_poly_a, n_poly_b) is possible and that the component is disregarded its wiring is electrically isolated from other components without it, and • the bipolar electronic component (poly_Da) is made above the gate electrode (G) of a MOS transistor (TR) when the substrate (sub) is placed at the bottom.

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