DE102014003697A1 - Systeme, Vorrichtungen und Verfahren zur Nullsetzung von Bits in einem Datenelement - Google Patents

Systeme, Vorrichtungen und Verfahren zur Nullsetzung von Bits in einem Datenelement Download PDF

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Publication number
DE102014003697A1
DE102014003697A1 DE102014003697.9A DE102014003697A DE102014003697A1 DE 102014003697 A1 DE102014003697 A1 DE 102014003697A1 DE 102014003697 A DE102014003697 A DE 102014003697A DE 102014003697 A1 DE102014003697 A1 DE 102014003697A1
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DE
Germany
Prior art keywords
source
operand
bits
bit
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE102014003697.9A
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German (de)
English (en)
Inventor
Elmoustapha Ould-Ahmed-Vall
Robert Valentine
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE102014003697A1 publication Critical patent/DE102014003697A1/de
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
DE102014003697.9A 2013-03-15 2014-03-13 Systeme, Vorrichtungen und Verfahren zur Nullsetzung von Bits in einem Datenelement Pending DE102014003697A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/840,669 US9207942B2 (en) 2013-03-15 2013-03-15 Systems, apparatuses,and methods for zeroing of bits in a data element
US13/840,669 2013-03-15

Publications (1)

Publication Number Publication Date
DE102014003697A1 true DE102014003697A1 (de) 2014-09-18

Family

ID=50634779

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102014003697.9A Pending DE102014003697A1 (de) 2013-03-15 2014-03-13 Systeme, Vorrichtungen und Verfahren zur Nullsetzung von Bits in einem Datenelement

Country Status (7)

Country Link
US (2) US9207942B2 (enExample)
JP (1) JP5753603B2 (enExample)
KR (1) KR101635856B1 (enExample)
CN (1) CN104133660A (enExample)
DE (1) DE102014003697A1 (enExample)
GB (1) GB2514885B (enExample)
IN (1) IN2014CH00953A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230027561A (ko) * 2021-08-19 2023-02-28 삼성전자주식회사 전자 장치 및 전자 장치의 메모리 제로화 방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5207132A (en) 1991-10-16 1993-05-04 Textron Inc. Elliptical lobed drive system
US5446912A (en) 1993-09-30 1995-08-29 Intel Corporation Partial width stalls within register alias table

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1587656A (enExample) * 1968-08-01 1970-03-27
US4785393A (en) * 1984-07-09 1988-11-15 Advanced Micro Devices, Inc. 32-Bit extended function arithmetic-logic unit on a single chip
JPS61103241A (ja) * 1984-10-27 1986-05-21 Nec Corp 情報処理装置
JPH02299082A (ja) * 1989-05-12 1990-12-11 Fujitsu Ltd 可変長データを処理するプロセッサ
US5201056A (en) * 1990-05-02 1993-04-06 Motorola, Inc. RISC microprocessor architecture with multi-bit tag extended instructions for selectively attaching tag from either instruction or input data to arithmetic operation output
US5268858A (en) * 1991-08-30 1993-12-07 Cyrix Corporation Method and apparatus for negating an operand
US6128725A (en) * 1997-01-24 2000-10-03 Texas Instruments Incorporated Microprocessor with an instruction for setting or clearing a bit field
US20040054877A1 (en) * 2001-10-29 2004-03-18 Macy William W. Method and apparatus for shuffling data
JP3857614B2 (ja) * 2002-06-03 2006-12-13 松下電器産業株式会社 プロセッサ
JP2006127460A (ja) * 2004-06-09 2006-05-18 Renesas Technology Corp 半導体装置、半導体信号処理装置、およびクロスバースイッチ
US8417921B2 (en) * 2008-08-15 2013-04-09 Apple Inc. Running-min and running-max instructions for processing vectors using a base value from a key element of an input vector
US9003170B2 (en) * 2009-12-22 2015-04-07 Intel Corporation Bit range isolation instructions, methods, and apparatus
US20120078597A1 (en) * 2010-09-27 2012-03-29 Infosys Technologies Limited Mobile device with a modeling platform
US20120185670A1 (en) * 2011-01-14 2012-07-19 Toll Bret L Scalar integer instructions capable of execution with three registers
US20120254593A1 (en) * 2011-04-01 2012-10-04 Jesus Corbal San Adrian Systems, apparatuses, and methods for jumps using a mask register
EP4250101A3 (en) * 2011-04-01 2024-01-03 Intel Corporation Vector friendly instruction format and execution thereof
US9411592B2 (en) * 2012-12-29 2016-08-09 Intel Corporation Vector address conflict resolution with vector population count functionality

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5207132A (en) 1991-10-16 1993-05-04 Textron Inc. Elliptical lobed drive system
US5446912A (en) 1993-09-30 1995-08-29 Intel Corporation Partial width stalls within register alias table

Also Published As

Publication number Publication date
IN2014CH00953A (enExample) 2015-05-08
KR20140113579A (ko) 2014-09-24
JP2014182800A (ja) 2014-09-29
KR101635856B1 (ko) 2016-07-05
GB2514885A (en) 2014-12-10
GB201404575D0 (en) 2014-04-30
US20140281400A1 (en) 2014-09-18
GB2514885B (en) 2015-10-28
US9207942B2 (en) 2015-12-08
JP5753603B2 (ja) 2015-07-22
CN104133660A (zh) 2014-11-05
US20160092226A1 (en) 2016-03-31

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