DE102013208142A1 - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a case (1), an input matching circuit (4) and an output matching circuit (5) in the case (1), and a plurality of transistor chips (6) between the input matching circuit (4) and the output matching circuit (5) in the case (Fig. 1). Each transistor chip 6 includes a rectangular semiconductor substrate 8 having long sides and short sides shorter than the long sides, and a gate electrode 9, a drain electrode 10, and a source electrode 11 on the semiconductor substrate 8 ). The gate electrode (9) includes a plurality of gate fingers (9a) disposed along the long sides of the semiconductor substrate (8) and a gate pad (9b) connected in common to the plurality of gate fingers (9a) and connected via a gate Wire (12) is connected to the input matching circuit (4). The drain electrode (10) is connected to the output matching circuit (5) via a wire (13). The long sides of the semiconductor substrates (8) of the plurality of transistor chips (6) are oblique to an input / output direction from the input matching circuit (4) to the output matching circuit (5).

Description

The present invention relates to a semiconductor device capable of improving an output without increasing its package size and causing deterioration of its characteristics and reliability.

High-output semiconductor devices (semiconductor devices with high output power) must amplify an input RF signal and output a power of several watts to several hundreds of watts. The gate width of transistors used for such semiconductor devices must be several mm to several hundred mm. Transistors with such a large gate width must be fitted into housings that are only several mm to several tens of mm in size. Thus, one to four or so of transistor chips having an array of several tens to one hundred or so of gate fingers having a gate width (gate finger length) of several tens of μm to several hundreds of mm are arranged in a package.

In known semiconductor devices, a plurality of transistor chips are arranged in a row so that their input sides and output sides each point in the same direction. In addition, a semiconductor device has also been proposed in which chips are arranged in front of or behind one another (see, for example, US Pat. JP 2007-274181 A ).

Further, in a transistor chip in which a plurality of gate fingers are arranged in a row, a line length from one gate pad to each gate finger varies from one finger to the other, causing phase differences. Therefore, an idea has been proposed that a plurality of gate fingers are arranged in a V-shape so that the line lengths from the gate pad to the respective gate fingers are equalized (see, for example, FIG. JP 61-104674 A ). This makes it possible to reduce phase differences and achieve high gain.

To increase the output power, the gate width must be increased. However, the number of chips that can be arranged and the side width of each chip of a semiconductor device in which a plurality of transistor chips are arranged in a row are limited by the side width of their case. Therefore, increasing the number of chips or increasing the side width of each chip increases the side width of the package, resulting in an increase in cost. Further, when chips are arranged in front of or behind each other, only ends of the chips can overlap each other to avoid wire contact, which prevents the package size from being sufficiently reduced.

For increasing the gate width without increasing the package size, further, the length of each gate finger (unit gate width) can be increased or the finger pitch can be decreased to increase the number of fingers. However, increasing the length of the gate fingers results in a reduction in gain. Further, decreasing the finger spacing may cause heat to concentrate, resulting in an increase in the channel temperature during operation. As a result, the characteristics or the reliability deteriorate.

When a plurality of gate fingers are arranged in a row in a side direction, heat generation during operation is concentrated on a rectangular area in which the fingers are arranged. On the other hand, when the plurality of gate fingers are arranged in a V-shape, the heat generation area expands. Since the gate fingers at ends of the transistor cells are located adjacent to each other at the boundary to the adjacent transistor cell, heat is concentrated at the cell boundary. Further, since the line lengths from the gate pad to the respective gate fingers must be balanced, the overlapping area between adjacent gate fingers can not be further reduced. For this reason, a heat concentration can not be sufficiently reduced, leading to an increase in temperature and a deterioration of properties or reliability.

In view of the above-described problems, the object of the present invention is to provide a semiconductor device capable of improving the output without increasing its package size or causing deterioration of its characteristics and reliability.

The object is achieved by a semiconductor device according to claim 1, 7 or 8. Further developments of the invention are specified in the subclaims.

The semiconductor device includes a housing, an input matching circuit and an output matching circuit in the housing, and a plurality of transistor chips between the input matching circuit and the output matching circuit in the housing. Each transistor chip includes a rectangular semiconductor substrate having long sides and short sides shorter than the long sides, and a gate electrode, a drain electrode, and a source electrode on the semiconductor substrate. The gate electrode includes a plurality of gate fingers disposed along the long sides of the semiconductor substrate, and a gate pad, which is commonly connected to the plurality of gate fingers and over a wire is connected to the input matching circuit. The drain electrode is connected to the output matching circuit via a wire. The long sides of the semiconductor substrates of the plurality of transistor chips are oblique to an input / output direction from the input matching circuit to the output matching circuit.

The present invention makes it possible to improve the output without increasing the package size or causing it to deteriorate in characteristics and reliability.

Further features and advantages of the invention will become apparent from the description of embodiments with reference to the accompanying drawings.

1 FIG. 10 is a plan view of a semiconductor device according to a first embodiment of the present invention. FIG.

2 is a sectional view taken along a line I-II in FIG 1 ,

3 is an enlarged plan view of the transistor chip of 1 ,

4 FIG. 10 is a plan view of the transistor chip of the first embodiment. FIG.

5 FIG. 10 is a plan view of a semiconductor device according to a comparative example. FIG.

6 FIG. 10 is a plan view of a transistor chip of the comparative example. FIG.

7 FIG. 10 is a plan view of a first modification example of the transistor chip of the first embodiment. FIG.

8th FIG. 10 is a plan view of a second modification example of the transistor chip of the first embodiment. FIG.

9 FIG. 12 is a plan view of a semiconductor device according to a second embodiment of the present invention. FIG.

10 is an enlarged plan view of the transistor chip of 9 ,

11 FIG. 10 is a plan view of a semiconductor device according to a third embodiment of the present invention. FIG.

12 is an enlarged detail of the top view of 11 ,

13 FIG. 10 is an enlarged fragmentary plan view of a semiconductor device according to a fourth embodiment of the present invention. FIG.

With reference to the figures, a semiconductor device according to the embodiments of the present invention will be described. The same components are denoted by the same reference numerals and their description will not be repeated.

1 FIG. 10 is a plan view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a sectional view taken along a line I-II in FIG 1 , An RF input connector 2 for inputting an RF signal and an RF output terminal 3 for outputting an RF signal are on opposite sides of a substantially rectangular in plan view housing 1 provided. An input matching circuit 4 and an output matching circuit 5 are in the case 1 provided and in each case with the RF input terminal and the RF output terminal 3 connected. A plurality of transistor chips 6 are in the housing between the input matching circuit 4 and the output matching circuit 5 1 provided. The upper surface of the housing 1 is with a lid 7 covered.

3 is an enlarged plan view of the transistor chip in FIG 1 , 4 FIG. 10 is a plan view of the transistor chip of the first embodiment. FIG. Each transistor chip 6 contains a rectangular semiconductor substrate 8th with long sides and short sides that are shorter than the long sides, as well as a gate electrode 9 , a drain electrode 10 and a source electrode 11 on the semiconductor substrate 8th are arranged.

The gate electrode 9 has a plurality of gate fingers 9a along the long sides of the semiconductor substrate 8th are arranged consecutively, and a gate pad 9b , which work together with the majority of gate fingers 9a connected is. The drain electrode 10 has a number of drain fingers 10a along the long sides of the semiconductor substrate 8th are arranged consecutively, and a drain pad 10b that with the majority of drain fingers 10a is connected together. The source electrode 11 has a plurality of source fingers 11a along the long sides of the semiconductor substrate 8th are arranged consecutively, and a source terminal surface 11b that with the majority of source fingers 11a is connected together. The gate pad 9b is over a gold wire 12 with the input matching circuit 4 connected, and the drain pad 10b the drain electrode 10 is about one gold wire 13 with the output matching circuit 5 connected.

A chip coupling gate interface 9c which is connected to the gate electrode is disposed near the short side. The chip coupling gate pads 9c adjacent transistor chips 6 are over a gold wire 14 connected with each other.

In the present embodiment, the long sides of the semiconductor substrates 8th the plurality of transistor chips 6 obliquely (diagonally) with respect to an input / output direction from the input matching circuit 4 to the output matching circuit 5 , This includes the input matching circuit 4 and the output matching circuit 5 each one pattern, whereby an adjustment is made for each transistor cell in the chip, and these patterns are wired for each cell and combined in a tournament form. Therefore, even if the plurality of transistor chips 6 are arranged obliquely, the chips are combined for each cell within the chip, while maintaining the symmetry. A chip combination while maintaining the symmetry is also possible.

Next, the effects of the present invention will be described in comparison with a comparative example.

5 FIG. 10 is a plan view of a semiconductor device according to a comparative example. FIG. 6 FIG. 12 is a plan view of the transistor chip of the comparative example. FIG. In the comparative example, four transistor chips 6 with a size of 3.2 mm × 0.56 mm arranged in a row so that their respective input and output sides are directed in the same direction.

In contrast, in the present embodiment, the four transistor chips 6 obliquely arranged at an angle of 45 ° with respect to the input / output direction. This makes it possible to increase the chip size in the longitudinal direction to (3.2 - 0.56 / √2) × √2 mm = 3.97 mm without increasing the case size. As a result, the present embodiment can increase the number of fingers without changing the length (unit gate width) of the gate fingers or the pitch of the fingers, and can improve the output power by about 24% as compared with the comparative example. Thus, the present invention can improve the output without increasing the package size or causing the characteristics and the reliability to deteriorate.

7 FIG. 10 is a plan view of a first modification example of the transistor chip of the first embodiment. FIG. Compared with the chip in 4 In the first embodiment, the chip size and the lateral direction and the number of gate fingers 9a the same, and the length (unit gate width) of each gate finger 9a is smaller. Compared with the chips of Comparative Example in 6 This makes it possible to increase the number of gate fingers 9a increase while the length of each gate finger 9a is reduced and the same total gate width is achieved. Therefore, the gain can be improved while maintaining the same output as the comparative example.

8th FIG. 10 is a plan view of a second modification example of the transistor chip of the first embodiment. FIG. Compared with the chip of the first embodiment in FIG 4 are the chip size in the side direction and the lengths (unit gate widths) of each gate finger 9a same, but the number of gate fingers 9a is smaller. Compared with the chip of the comparative example in FIG 6 This makes it possible to increase the distance between the gate fingers 9a while the same unit gate width, the same number of gate fingers 9a and the same total gate width is preserved. Therefore, it is possible to improve the heat dissipation with the same output as in the comparative example.

To adjacent transistor chips 6 via the chip coupling gate interface 9c The majority of transistor chips must be connected 6 be arranged in a zigzag structure in the present embodiment. If the chips do not need to be coupled, the plurality of transistor chips 6 also be arranged obliquely in the same orientation.

9 FIG. 12 is a plan view of a semiconductor device according to a second embodiment of the present invention. FIG. 10 is an enlarged plan view of the transistor chip of 9 , The shape of the transistor chips is not a normal rectangle, but a parallelogram. The short sides of the semiconductor substrates 8th the plurality of transistor chips 6 are parallel to the input / output direction.

If the rectangular transistor chip 6 with chip coupling connection pads 9c provided at the ends of the chip, the area of the area in which the gate fingers sink decreases 9a are arranged. In contrast, the present embodiment enables the chip coupling gate pad 9c in the gaps between the chips, and thereby the area of the area in which the gate fingers can be extended 9a are arranged. Therefore, the output power can be further improved without increasing the case size.

The semiconductor substrate 8th of the transistor chip 6 is made of SiC, and a GaN-based HEMT is provided thereon. When doing so Semiconductor substrate 8th in a direction different from the plane azimuth, a crack may be generated along the plane azimuth when a stress is applied to a chip end. Thus, a substrate of a hexagonal crystal whose plane azimuth is a 60 ° direction is used, and when the long side cleavage planes are <-1100> and <1-100>, the short side is 60 ° with respect to the long side is inclined and is cut along the gap planes <-1010> and <10-10> or the gap planes <0-110> and <01-10>. Thereby, it is possible to suppress the generation of cracks when a stress is applied.

A high output power is required in particular for a power amplifier of an MMIC. Therefore, the semiconductor device according to the first or second embodiment is particularly effective when applied to an output stage of an MMIC. As a semiconductor chip 6 , its semiconductor substrate 8th is made of SiC, has a high withstand voltage and a high maximum allowable current density, the chip can be downsized. Using these miniaturized chips also makes it possible to miniaturize a semiconductor device containing these chips. Further, since the chip has a high heat resistance, cooling fins of the heat sink can be downsized, and a water cooling portion can be replaced by an air cooling system, which further enables downsizing of the semiconductor device. Further, since the chip has a low power loss and has a high efficiency, a semiconductor device can be provided with high efficiency.

11 FIG. 10 is a plan view of a semiconductor device according to a third embodiment of the present invention. FIG. 12 is an enlarged detail of the top view of 11 , This semiconductor device is an MMIC having an input-stage transistor region that amplifies an input signal and an output-stage transistor region that further amplifies the output signal.

A plurality of transistor cells 15 are on a semiconductor substrate 8th arranged. In every transistor cell 15 are a plurality of gate fingers 9a arranged obliquely next to each other in a rectangular shape. At the border between neighboring transistor cells 15 are the gate fingers 9a at the ends of the transistor cells offset from each other. This prevents heat from being concentrated at the cell boundary and prevents deterioration of properties and reliability caused by temperature rise. According to the result of simply calculating the thermal resistance using a simulation, the present invention can compare the thermal resistance value with a device in which a plurality of gate fingers 9a in a side direction in a row, by about 20% decrease.

With such excellent heat dissipation, it is possible to reduce the finger spacing, increase the number of fingers, and increase the overall gate width without changing the thermal resistance per gate width. Thus, it is possible to improve the output without effecting an increase in package size or deterioration in properties and reliability.

In the present embodiment, the array is gate fingers 9a changed for each cell, but the field may be changed for each plurality of cells, or the field may be changed several times within a cell.

13 FIG. 10 is an enlarged fragmentary plan view of a semiconductor device according to a fourth embodiment of the present invention. FIG. As in the third embodiment, a plurality of transistor cells 15 on a semiconductor substrate 8th arranged. A plurality of gate fingers 9a are gradually offset from each other in the finger direction, and the offset direction becomes in the middle of the transistor cell 15 vice versa, leaving the gate fingers 9a arranged in a V-shape.

The cable length of a gate pad 9b to the gate finger 9a in the middle is larger than the line length from the gate pad 9b to a gate finger 9a at the end. Such an elongated arrangement of the plurality of gate fingers 9a in V-shape reduces the overlapping area between adjacent gate fingers 9a compared to the V-shaped arrangement, where the line lengths from the gate pad 9b to the respective gate fingers 9a they are the same. For this reason, the heat concentration can be sufficiently reduced.

With such excellent heat dissipation, it is possible to control the pitch of the gate fingers 9a to reduce the number of gate fingers and increase the total gate width without changing the thermal resistance per gate width. Thus, it is possible to improve the output without increasing the case size and without causing deterioration in properties and reliability.

Further, it is also possible to reduce the finger spacing and reduce the unit gate width without changing the chip size and the total gate width. This makes it possible to improve the gain without increasing the package size and without causing deterioration of the characteristics and the reliability.

In the present embodiment, the offset direction becomes the gate finger 9a in the cell center is changed in the opposite direction, but the offset direction can be reversed every plurality of cells, or it can be reversed several times within a cell. The period of reversal of the offset direction can be flexibly changed depending on the layout of the entire MMIC, which enables a design with a high degree of freedom.

Further, in the third and fourth embodiments, the source terminal surface 11b also disposed on the drain side to reduce a source inductance, but the source terminal surface 11b can also be arranged only on the gate side, without a source terminal surface 11b to arrange on the drain side. Further, a combination of the construction of the third or fourth embodiment or the apparatus of the first or second embodiment makes it possible to further improve the output.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• JP 2007-274181 A [0003]
• JP 61-104674A [0004]

Claims (8)

Semiconductor device with a housing ( 1 ), an input matching circuit ( 4 ) and an output matching circuit ( 5 ) in the housing ( 1 ) and a plurality of transistor chips ( 6 ) between the input matching circuit ( 4 ) and the output matching circuit ( 5 ) in the housing ( 1 ), each transistor chip ( 6 ) a rectangular semiconductor substrate ( 8th ) with long sides and short sides that are shorter than the long sides, and a gate electrode ( 9 ), a drain electrode ( 10 ) and a source electrode ( 11 ) on the semiconductor substrate ( 8th ), the gate electrode ( 9 ) a plurality of gate fingers ( 9a ) along the long sides of the semiconductor substrate ( 8th ) are arranged, and a gate pad ( 9b ) associated with the plurality of gate fingers ( 9a ) is connected together and which is connected via a wire ( 12 ) with the input matching circuit ( 4 ), the drain electrode ( 10 ) over a wire ( 13 ) with the output matching circuit ( 5 ) and the long sides of the semiconductor substrates ( 8th ) of the plurality of transistor chips ( 6 ) obliquely to an input / output direction from the input matching circuit ( 4 ) to the output matching circuit ( 5 ) are. A semiconductor device according to claim 1, wherein each semiconductor chip ( 6 ) a chip coupling gate pad ( 9c ) connected to the gate electrode ( 9 ) and located near the short side, the die coupling pads ( 9c ) of adjacent semiconductor chips ( 6 ) over a wire ( 14 ) and the short sides of the semiconductor substrates ( 8th ) of the plurality of transistor chips are parallel to the input / output direction. A semiconductor device according to claim 2, wherein the short sides are arranged along the gap planes of the semiconductor substrate ( 8th ) lie. Semiconductor device according to Claim 3, in which the semiconductor substrate ( 8th ) is made of SiC and the short sides are inclined at 60 ° to the long sides. A semiconductor device according to any one of claims 1 to 4, wherein a plurality of transistor cells ( 15 ) on the semiconductor substrate ( 8th ) are arranged, the plurality of gate fingers ( 9a ) in each transistor cell ( 15 ) are arranged obliquely in a straight line form and the gate fingers ( 9a ) at the ends of adjacent transistor cells ( 15 ) at a boundary between the adjacent transistor cells ( 15 ) are offset from each other. A semiconductor device according to any one of claims 1 to 5, wherein the plurality of gate fingers ( 9a ) are arranged in a V-shape and a line length from the gate pad ( 9b ) to a gate finger ( 9a ) in the middle is longer than a line length from the gate pad ( 9b ) to a gate finger ( 9a ) at the end. Semiconductor device having a semiconductor substrate ( 8th ) and a plurality of transistor cells ( 15 ) on the semiconductor substrate ( 8th ), each transistor cell ( 15 ) a plurality of gate fingers ( 9a ), which are arranged obliquely in a straight line form, and the gate fingers ( 9a ) at the ends of adjacent transistor cells ( 15 ) at a boundary between the adjacent transistor cells ( 15 ) are offset from each other. Semiconductor device having a semiconductor substrate ( 8th ) and a plurality of transistor cells ( 15 ) on the semiconductor substrate ( 8th ), each transistor cell ( 15 ) a plurality of gate fingers ( 9a ), which are arranged obliquely in a straight line shape, and a gate pad ( 9b ) associated with the plurality of gate fingers ( 9a ) and a line length from the gate pad (FIG. 9b ) to a gate finger ( 9a ) in the middle is longer than a line length from the gate pad ( 9b ) to a gate finger ( 9a ) at the end.

Images