DE102013113061A1 - Semiconductor devices and methods for their manufacture - Google Patents

Abstract

According to one embodiment of the present invention, a semiconductor device has a semiconductor chip (50) with a first side and an opposite second side and a chip contact point (150) which is arranged on the first side of the semiconductor chip (50). A dielectric casing (20) is arranged over the semiconductor chip (50). The dielectric casing (20) has a plurality of openings (80) above the chip contact point (150). A connection contacts the semiconductor chip (50) through the plurality of openings (80) at the chip contact point (150).

Description

The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods for their manufacture.

Semiconductor devices are used in a variety of electronic and other applications. Semiconductor devices include, but are not limited to, integrated circuits or discrete devices formed on semiconductor wafers by depositing one or more types of in-situ films of material over the semiconductor wafers and patterning the thin films of material to form integrated circuits.

The semiconductor devices are typically packaged within a ceramic or plastic body to protect the semiconductor devices from physical damage or corrosion. The encapsulation also supports the electrical contacts required to connect a semiconductor device, also referred to as a die or chip, to other devices outside the package. Many different types of encapsulation are available depending on the type of semiconductor device and the intended use of the semiconductor device being encapsulated. Typical encapsulation features such. As the dimensions of the device, the number of pin numbers, etc., among other open standards before the Joint Electron Devices Engineering Council (JEDEC) correspond. Encapsulation may also be referred to as semiconductor device mounting or simply mounting.

According to an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a die pad disposed on the first side of the semiconductor chip. A dielectric cladding is disposed over the semiconductor chip. The dielectric cladding has a plurality of openings over the die pad. A connection contacts the semiconductor chip through the plurality of openings at the die pad.

In one embodiment, the device may further comprise an encapsulation material which is arranged around the first semiconductor chip, wherein the first connection is arranged in the encapsulation material. In yet another embodiment, the device may further include a conductive plate, wherein the first semiconductor chip is disposed over the conductive plate, wherein the dielectric cladding is disposed over the conductive plate, and wherein the encapsulating material is disposed over the dielectric cladding. In yet another embodiment, the device may further include a conductive plate, wherein the first semiconductor chip is disposed over the conductive plate, wherein the encapsulation material is disposed over the conductive plate. In yet another embodiment, the device may further include: a second die pad located on the first side of the first semiconductor die; a plurality of second openings disposed in the dielectric panel over the second die pad; and a second connection contacting the first semiconductor chip through the plurality of second openings at the second die pad. In yet another embodiment, the device may further include: a second semiconductor chip, the second semiconductor chip having a first side and an opposite second side; a second die pad disposed on the first side of the second semiconductor die, the dielectric cover disposed over the second die, and wherein the dielectric liner has a plurality of second openings over the second die pad; and a second connection contacting the second semiconductor chip through the plurality of second openings at the second die pad. In yet another embodiment, the device may further comprise a conductive plate, wherein the first semiconductor chip and the second semiconductor chip are arranged above the conductive plate.

According to an alternative embodiment of the present invention, a semiconductor device comprises a semiconductor chip having a first side and an opposite second side and a semiconductor chip Chip pad, which is arranged on the first side of the semiconductor chip on. The die pad has a plurality of openings. A connection contacts the semiconductor die through the plurality of openings at the die pad.

In one embodiment, the device may further comprise an encapsulation material which is arranged around the first semiconductor chip, wherein the first connection is arranged in the encapsulation material. In yet another embodiment, the device may further include a conductive plate, wherein the first semiconductor chip is disposed over the conductive plate, wherein the encapsulation material is disposed over the conductive plate. In yet another embodiment, the device may further include: a second die pad located on the first side of the first semiconductor die; a plurality of second openings disposed in the second die pad; and a second connection contacting the first semiconductor chip through the plurality of second openings at the second die pad. In yet another embodiment, the device may further include: a second semiconductor chip having a first side and an opposite second side; a second die pad located on the first side of the second semiconductor die, the second die pad having a plurality of second openings; and a second connection contacting the second semiconductor chip through the plurality of second openings at the second die pad. In yet another embodiment, the device may further comprise a conductive plate, wherein the first semiconductor chip and the second semiconductor chip are arranged above the conductive plate. In yet another embodiment, the device may further include spacers disposed about sidewalls of the plurality of first openings of the first die pad.

According to an alternative embodiment of the present invention, a method of forming a semiconductor device comprises providing a semiconductor chip having a first side and an opposite second side, and attaching the second side of the semiconductor chip to a conductive plate. The semiconductor chip has a chip pad on the first side. However, a dielectric cladding is formed on the semiconductor chip. A portion of the dielectric cladding over the first die pad is patterned. An encapsulation material is formed over the semiconductor chip. A connection is formed by the encapsulation material and by the structured part of the dielectric cladding with the chip pad.

In one embodiment, forming the connection may include attaching a wire. In yet another embodiment, forming the connection may include: forming a connection opening in the encapsulation material to expose the patterned portion of the dielectric cladding; and filling the connection opening with a conductive material. In yet another embodiment, forming the connection opening may include removing the exposed structured portion of the dielectric cover after forming the connection opening. In yet another embodiment, forming the connection opening may include using a pulsed laser process. In yet another embodiment, attaching the second side of the first semiconductor chip to the conductive plate may include the use of a soldering process or a pressure-sensitive adhesive. In yet another embodiment, the conductive plate may be a chip island of a leadframe. In yet another embodiment, forming the dielectric cladding over the first semiconductor chip and patterning the portion of the dielectric cladding over the first die pad may include: forming a first layer over the first semiconductor chip; Patterning the first layer to expose the first die pad; Depositing a second layer over the first layer and the exposed first die pad; and patterning the second layer to expose portions of the first die pad. In yet another embodiment, the method may further include forming an imide layer over the second layer prior to forming the encapsulating material. In yet another embodiment, the method may further include forming an imide layer prior to forming the encapsulating material.

According to an alternative embodiment of the present invention, a method of forming a semiconductor device includes providing a semiconductor chip having a first side and an opposite second side, and attaching the second side of the semiconductor chip to a conductive plate. The semiconductor chip has a chip pad on the first side. A portion of the die pad is patterned to form openings in the die pad. The method further includes forming an encapsulating material over the first semiconductor chip and forming a connection through the encapsulating material and the openings of the first die pad.

In one embodiment, the forming of the connection may include: forming a connection opening in the encapsulation material; and filling the connection opening with a conductive material. In yet another embodiment, forming the connection may include attaching a wire. In yet another embodiment, forming the connection opening may include using a pulsed laser process. In yet another embodiment, attaching the second side of the first semiconductor chip to the conductive plate may include the use of a soldering process or a pressure-sensitive adhesive. In yet another embodiment, the conductive plate may be a chip island of a leadframe. In yet another embodiment, the method may further include forming an imide layer prior to forming the encapsulating material.

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

1 , the 1A - 1C a semiconductor device according to an embodiment of the present invention, wherein 1A FIG. 10 illustrates a cross-sectional view of the semiconductor device while FIG 1B FIG. 4 illustrates a sectional plan view of the semiconductor device and FIG 1C represents a plan view;

2 , the 2A - 2I Fig. 12 illustrates a semiconductor device during various stages of fabrication in accordance with embodiments of the present invention;

3 , the 3A - 3E Figure 4 illustrates a semiconductor device during various stages of processing according to an alternative embodiment of the invention;

4 , the 4A - 4F a semiconductor device during manufacture according to an alternative embodiment of the present invention;

5 , the 5A - 5B Fig. 10 illustrates an alternative embodiment of the present invention in which the plurality of apertures are spaced in the die pad, facilitating the formation of spacers;

6 , the 6A - 6C Fig. 10 illustrates a semiconductor device in various stages of manufacture in accordance with an alternative embodiment of the present invention;

7 , the 7A - 7E a semiconductor device during manufacture according to an alternative embodiment of the present invention;

8th , the 8A - 8D a semiconductor device during manufacture according to an alternative embodiment of the present invention;

9 , the 9A - 9D 1, a semiconductor device according to an embodiment of the present invention;

10 , the 10A - 10E 1, a semiconductor device according to an embodiment of the present invention, wherein the patterned dielectric clad forms segmented pad contacts, wherein 10A FIG. 10 is a cross-sectional view after wafer plane processing; FIG. 10B - 10D represent the corresponding plan view of the chip pad and 10E the cross-sectional view of the semiconductor device after the formation of the contact connection represents;

11 , the 11A - 11D 1, illustrating a semiconductor device according to an embodiment of the present invention, in which the patterned dielectric cladding is lifted off during the formation of the opening for the contact connection, wherein 11A FIG. 10 is a cross-sectional view after wafer plane processing; FIG. 11B - 11C represent the corresponding plan view of the chip pad and 11D the cross-sectional view of the semiconductor device after the formation of the contact connection represents;

12 , the 12A - 12E , a semiconductor device according to an embodiment of the present invention, wherein a dielectric cladding having two layers is used to form a patterned dielectric cladding, wherein 12A FIG. 10 is a cross-sectional view after wafer plane processing; FIG. 12B - 12D represent the corresponding plan view of the chip pad and 12E the cross-sectional view of the semiconductor device after the formation of the contact connection represents;

13 , the 13A - 13D 1, which illustrates a semiconductor device according to an alternative embodiment of the present invention, wherein a two-layered dielectric cladding is used to form a patterned dielectric cladding 13A FIG. 10 is a cross-sectional view after wafer plane processing; FIG. 13B - 13C represent the corresponding plan view of the chip pad and 13D the cross-sectional view of the semiconductor device after the formation of the contact connection represents;

14 , the 14A - 14E 1, a semiconductor device according to an embodiment of the present invention, wherein each substructure is coupled to a patterned chip pad with an underlying contact hole, wherein 14A FIG. 10 is a cross-sectional view after wafer plane processing; FIG. 14B - 14D represent the corresponding plan view of the chip pad and 14E the cross-sectional view of the semiconductor device after the formation of the contact connection represents;

15 , the 15A - 15D , a semiconductor device according to an embodiment of the present invention, wherein the patterned chip pad is coupled by an outer edge, wherein 15A FIG. 10 is a cross-sectional view after wafer plane processing; FIG. 15B - 15C the represent appropriate plan view of the chip pad and 15D the cross-sectional view of the semiconductor device after the formation of the contact connection represents; and

16 , the 16A - 16D 1, a semiconductor device according to an alternative embodiment of the present invention, wherein the patterned die pad is coupled by an outer edge, wherein 16A FIG. 10 is a cross-sectional view after wafer plane processing; FIG. 16B - 16C represent the corresponding plan view of the chip pad and 16D the cross-sectional view of the semiconductor device after the formation of the contact connection represents.

Corresponding numerals and characters in the various figures generally refer to corresponding parts unless otherwise specified. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

The manufacture and use of various embodiments will be discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that may be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways of making and using the invention and do not limit the scope of the invention.

A structural embodiment of the invention will be described using FIG 1 described. Alternative structural embodiments of the present invention are made using 2G . 2H . 3E . 4F . 5B . 6C . 7E . 8D and 9 - 16 described. A method of manufacturing the semiconductor device is made using 2 described. Alternative embodiments for manufacturing the semiconductor device are described using 3 . 4 . 5 . 6 . 7 . 8th . 10 - 16 described.

1 , the 1A - 1C 1 illustrates a semiconductor device according to an embodiment of the present invention. 1A FIG. 12 illustrates a cross-sectional view of the semiconductor device during FIG 1B FIG. 4 illustrates a sectional plan view of the semiconductor device and FIG 1C represents a top view.

Regarding 1A For example, the semiconductor device may be a semiconductor module 1 with a semiconductor chip 50 be.

In various embodiments, the semiconductor chip 50 comprise an integrated circuit chip or a discrete device. In one or more embodiments, the semiconductor chip 50 a logic chip, a memory chip, an analog chip, a composite signal chip, a discrete device and combinations thereof, such as. As a system on a chip have. The semiconductor chip 50 can be different types of active and passive devices such. As diodes, transistors, thyristors, capacitors, inductors, resistors, optoelectronic devices, sensors, microelectromechanical systems and others.

In various embodiments, the semiconductor chip 50 on a conductive substrate 10 attached. The conductive substrate 10 has copper in one embodiment. In other embodiments, the conductive substrate 10 a metal material, which may include conductive metals and their alloys, on the conductive substrate 10 may also have an intermetallic material when conductive. The conductive substrate 10 may in one embodiment comprise a lead frame. In an embodiment, the conductive substrate 10 For example, have a chip island, over which the semiconductor chip 50 can be attached. In further embodiments, as with reference to 7 can be described, the conductive substrate 10 have one or more chip islands, over which one or more chips may be attached.

In further alternative embodiments, the substrate 10 not be conductive. In these embodiments, the electrical contact is with the substrate 10 obsolete.

In various embodiments, multiple different or identical chips may be used 50 on the substrate 10 be attached by various means.

In various embodiments, the semiconductor chip 50 be formed on a silicon substrate. In other embodiments, the semiconductor chip 50 alternatively be formed on silicon carbide (SiC). In an embodiment, the semiconductor chip 50 at least partially formed on gallium nitride (GaN).

In various embodiments, the semiconductor chip 50 a power semiconductor device, which in one embodiment may be a discrete device. In one embodiment, the semiconductor chip 50 a device with two connections such. As a PIN diode or a Schottky diode. In one or more embodiments, the semiconductor chip 50 a device with three connections such. A power metal-insulator-semiconductor field effect transistor (MISFET), a junction field effect transistor (JFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT) or a thyristor.

In various embodiments the semiconductor chip 50 a thickness less than 100 μm. In alternative embodiments, the semiconductor chip 50 a thickness less than 50 μm. In alternative embodiments, the semiconductor chip 50 a thickness that is less than 20 microns.

In various embodiments, the semiconductor chip 50 a thickness between about 10 microns and about 100 microns. In alternative embodiments. has the semiconductor chip 50 a thickness between about 10 microns and about 30 microns. In further alternative embodiments, the semiconductor chip 50 a thickness between about 30 microns and about 40 microns.

The semiconductor chip 50 is in various embodiments in an encapsulating material 20 embedded. In various embodiments, the encapsulating material 20 a dielectric material and in one embodiment may have a mold compound. In one or more embodiments, the encapsulating material 20 have an imide. In other embodiments, the encapsulating material 20 comprise one or more of a polymer, a copolymer, a biopolymer, a fiber-impregnated polymer (e.g., carbon or glass fibers in a resin), a particle-filled polymer, and other organic materials. In one or more embodiments, the encapsulating material 20 a sealant that is not formed using a mold compound, and materials such. As epoxy resins and / or silicones on. In various embodiments, the encapsulating material 20 consist of any suitable thermosetting, thermoplastic, thermosetting material or a laminate. The material of the encapsulating material 20 may include fillers in some embodiments. In one embodiment, the encapsulating material 20 an epoxy material and a filler with small particles of glass or other electrically insulating mineral filling materials such as alumina or organic fillers.

In various embodiments, the encapsulating material 20 a thickness of about 20 microns to about 100 microns. In alternative embodiments, the encapsulating material 20 a thickness of about 50 microns to about 80 microns. In further alternative embodiments, the encapsulating material 20 a thickness of about 20 microns to about 50 microns. Alternatively, in some embodiments, a thinner encapsulating material 20 be used. In such embodiments, the encapsulating material 20 a thickness of about 10 microns to about 20 microns.

The semiconductor module 1 has several contact points in some embodiments 90 for mounting the semiconductor module 1 over a printed circuit board. As an illustration, the multiple contact points 90 a first contact point 91 , a second contact point 92 and a third contact point 93 that together the contacts for the semiconductor chip 50 make up.

The second contact point 92 the multiple contact points 90 and the third contact point 93 the multiple contact points 90 can with a front side of the semiconductor chip 50 be coupled. The second contact point 92 and the third contact point 93 are for example with chip contact points 150 on the semiconductor chip 50 coupled. In various embodiments, the plurality of contact points 90 with the second contact point 92 and the third contact point 93 with the chip pads 150 using contact connections 80 coupled. The contact connections 80 are inside the encapsulating material 20 arranged.

The first contact point 91 the multiple contact points 90 can with a backside of the semiconductor chip 50 be coupled. In one or more embodiments, the first contact point 91 for example, using one or more contact holes 85 through the encapsulating material contained in the encapsulating material 20 are arranged to be coupled.

In various embodiments, the contact points form 90 a redistribution layer. Of course, multiple levels of redistribution layers may be present in the package on both sides of the substrate 10 be educated.

In various embodiments, the contact connections 80 with the semiconductor chip 50 coupled through a structured layer, as in 1A shown. Every contact connection 80 is through segments of the dielectric cladding 15 coupled. The structured layer in one embodiment has a patterned dielectric cladding 15 on. The dielectric lining 15 may comprise a nitride in one or more embodiments. In other embodiments, the dielectric cladding 15 other dielectric materials such. For example, oxide, silicon carbide, silicon oxynitride, hafnium oxide, alumina, other high dielectric constant materials, other low dielectric constant materials, polyimide, and other organic materials.

In the illustrated embodiment, the panel is 15 only over the semiconductor chip 50 educated. However, in some alternative embodiments, the trim is 15 both above the semiconductor chip 50 as well as the substrate 10 educated. As in 1B In one embodiment, the patterned layer forms multiple trenches in the dielectric cladding 15 that the semiconductor chip 50 covered. In alternative In embodiments, the structured layer forms a plurality of squares or columns or circles.

2 , the 2A - 2I 1 illustrates a semiconductor device during various stages of manufacture in accordance with embodiments of the present invention.

Regarding 2A becomes a semiconductor chip 50 on a substrate 10 attached. In various embodiments, the in 2 described processes for each semiconductor chip can be performed sequentially or in alternative embodiments, a plurality of semiconductor devices using a strip or substrate 10 be formed with a plurality of conductive plates. Alternatively, the substrate 10 comprise a polymer substrate.

In various embodiments, the semiconductor chip 50 comprise an integrated circuit chip or a discrete device. The semiconductor chip 50 has several chip pads 150 on a first side of the semiconductor chip 50 on. In some embodiments, the semiconductor chip 50 also contact points on the opposite second side of the semiconductor chip 50 exhibit. The semiconductor chip 50 For example, it may be a discrete vertical device with contact points on both sides.

The semiconductor chip 50 can be formed within a semiconductor wafer and singulated. In various embodiments, the semiconductor wafer is thinned before or after the singulation process. In various embodiments, therefore, the semiconductor chip 50 a thickness of about 10 μm to about 100 μm, and in one embodiment about 30 μm to 50 μm.

In various embodiments, the semiconductor chip 50 on the substrate 10 be attached using a soldering process. In one or more embodiments, the semiconductor chip 50 on the substrate 10 attached using a diffusion bonding process.

In various embodiments, the semiconductor chip 50 on the substrate 10 using a die attach layer 11 be attached, which may be insulating in one embodiment. In some embodiments, the die attach layer may 11 may be conductive, for example, may have a nanoleitfähige paste. In alternative embodiments, the die attach layer is 11 a solderable material, the die attach layer 11 For example, in one embodiment, it may be applied to the semiconductor chip 50 applied and to the substrate 10 be soldered.

In an alternative embodiment, the die attach layer 11 a polymer such as. For example, a cyanide ester or an epoxy material and may have silver particles. In one embodiment, the die attach layer 11 are applied as conductive particles in a polymer matrix to form a composite material after curing. In an alternative embodiment, a conductive nanopaste such. B. a silver nanopaste are applied. In another embodiment, the die attach layer 11 alternatively a solder such. As a lead-tin material, on. In various embodiments, any suitable conductive adhesive material may be coated with metals or metal alloys, such as metals. For example, aluminum, titanium, gold, silver, copper, palladium, platinum, nickel, chromium or nickel vanadium may be used to form the die attach layer 11 train.

The die attach layer 11 can in controlled amounts under the semiconductor chip 50 be issued. A die attach layer 11 with a polymer may be cured at about 125 ° C to about 200 ° C while a die attach layer 11 solder-based at 250 ° C to about 350 ° C can be cured. Using the die attach layer 11 becomes the semiconductor chip 50 on the substrate 10 attached, which in one embodiment may be a chip island of a lead frame.

Regarding 2 B becomes a disguise 15 above the substrate 10 on the semiconductor chip 50 deposited. In various embodiments, the fairing 15 a nitride material. In alternative embodiments, the fairing 15 have an oxide. In further embodiments, the fairing 15 have other suitable materials, such as. Silicon oxynitride, hafnium oxide, silicon carbide, organic dielectric materials and others. In other embodiments, the fairing 15 just above the chip 50 arranged.

In various embodiments, the fairing 15 using a vapor deposition process such. Chemical vapor deposition, physical vapor deposition, plasma enhanced physical vapor deposition, including high density plasma or atomic layer deposition processes. In other embodiments, an organic material is deposited by spray, pressure, or spin-on processes. In various embodiments, the Thickness of the cladding 15 after deposition, about 100 nm to about 300 nm. In alternative embodiments, the thickness of the cladding is 15 after deposition, about 1 nm to about 40 nm. In one or more embodiments, the thickness of the cladding is 15 after deposition, about 5 nm to about 20 nm. In one or more embodiments, the thickness of the cladding is 15 after deposition about 40 nm to about 100 nm.

The costume 15 is structured as in 2C and 2D shown. 2C is a top view while 2D is a cross-sectional view. In one or more embodiments, the trim is 15 above the substrate 10 removed or above the substrate 10 structured.

Regarding 2D becomes the fairing 15 in various embodiments in an area above the semiconductor chip 50 structured. In one or more embodiments, the trim is 15 directly above the chip contact point 150 structured, with the several openings 60 be formed by segments of the panel 15 are separated ( 2C ). In some embodiments, the semiconductor chip 50 through several openings 60 in disguise 15 be tested for functionality. In one or more embodiments, the plurality of openings 60 , which are separated by segments with a length of about 10 microns, about 2 microns to 10 microns. In other embodiments, the dielectric segments have an extension in a direction of 5 μm to 20 μm. Likewise, the several openings 60 Openings with a dimension of about 2 microns to about 10 microns. In other embodiments, the openings 60 a dimension in a direction of 5 to 20 microns.

As in next 2E is an encapsulating material 20 over the (or more) semiconductor chip 50 applied and partially encloses the semiconductor chip 50 , In one embodiment, the encapsulating material 20 using a molding process such. B. molding, a transfer molding process, injection molding, granule molding, powder molding, liquid molding and printing processes such. B. stencil or screen printing applied.

In various embodiments, the encapsulating material comprises 20 a dielectric material as previously with reference to 1 described. In one embodiment, the encapsulating material 20 an imid. The encapsulating material 20 can be cured, ie, subjected to a thermal process to harden, thus form, the hermetic seal, which the semiconductor chip 50 protects.

In various embodiments, the encapsulating material 20 have a thickness of about 20 microns to about 70 microns and in one embodiment from about 50 microns to about 100 microns.

Regarding 2F be several contact openings 70 within the encapsulating material 20 educated. The contact openings 70 extend from the upper surface of the encapsulating material 20 to the chip contact point 150 , Multiple vias may also be located within the encapsulant 20 to the substrate 10 be formed. The via vias may extend from the top surface of the encapsulant 20 to the substrate 10 to the opposite bottom surface of the encapsulating material 20 and through the disguise 15 extend.

In one or more embodiments, the plurality of contact openings 70 and the plurality of via holes are formed using a laser process. For example, a laser drill can be used to encapsulate the material 20 to structure. In one embodiment, a pulsed carbon dioxide laser may be used for laser drilling. In another embodiment, the laser drilling may include an Nd: YAG laser. In an alternative embodiment, the plurality of contact openings 70 and the plurality of via holes are formed according to a conventional lithography process using, for example, a plasma etching process.

In various embodiments, the plurality of contact openings 70 a maximum diameter of less than 200 microns. The multiple contact openings 70 have a maximum diameter of less than 80 microns in one or more embodiments. The multiple contact openings 70 In one embodiment, they have a maximum diameter of less than 300 μm. The multiple contact openings 70 In various embodiments, have a maximum diameter of about 50 microns to about 150 microns.

Regarding 2G become the multiple contact openings 70 and filling the plurality of via holes with a conductive material.

As in next 2G shown, can be a metal panel 81 within the multiple contact openings 70 and the plurality of through-hole openings are formed. The metal panel 81 can the multiple openings 60 in the dielectric cladding 15 fill in some embodiments. Alternatively, the metal panel 81 the multiple contact openings 70 line. The metal panel 81 may comprise a diffusion barrier material and may also have a seed layer for subsequent electroplating or electroless plating. As an example, the metal panel 81 in one embodiment a stack of metals, metal nitrides (eg TiN, TaN) followed by a seed layer (eg Cu). In another embodiment, only one seed layer can be deposited.

The metal panel 81 For example, in one embodiment, it may be deposited using sputter deposition. In one embodiment, the metal panel 81 using high frequency magnetron sputtering (RF magnetron sputtering). In alternative embodiments, the metal panel 81 have a layer of Ta, TaN, W, WN, WCN, WSi, Ti, WTi, TiN and / or Ru as examples. The seed layer may be conformally deposited over the diffusion barrier material using, for example, a plasma gas phase sputtering (PVD) or metal organic chemical vapor deposition (MOCVD) process. In various embodiments, the seed layer comprises the same material as the material to be deposited using an electroplating or electroless plating process. The seed layer has copper in one embodiment. In another embodiment, the seed layer may be deposited by means of a conductive polymer.

A conductive filler 82 gets into the multiple contact holes 70 and filling the plurality of via holes. In various embodiments, the conductive filler becomes 82 using an electrochemical deposition process such. B. electroplating deposited. Alternatively, the conductive filler material 82 be deposited using an electroless deposition process.

In one or more embodiments, the conductive filler material may be 82 Copper, aluminum and other such have. In other embodiments, the conductive filler material may be 82 Tungsten, titanium, tantalum, ruthenium, nickel, cobalt, platinum, gold, silver and other such materials. In various embodiments, the conductive filler is 82 a material that can be electrodeposited. After depositing the conductive filler 82 thus becomes a conductive layer 86 above the encapsulating material 20 educated. This layer 86 forms conductive pads and a redistribution layer to allow electrical routing between different chips.

In an alternative embodiment, a wire may pass through the plurality of contact openings 70 be inserted and attached, for example, using a soldering process to form a Drahtbondstelle.

As in next 2H is shown, the conductive filler 82 structured to contact connections 80 and form openings through the substrate. The contact connections 80 thus become within the multiple contact openings 70 formed while contact holes through the substrate within the plurality of through-hole openings are formed. In various embodiments, the conductive filler material may be 82 be patterned using an etching process after a lithographic process.

2I represents an alternative embodiment in which the substrate 10 a strip such. B. comprises a lead frame strip. As a result, a plurality of semiconductor chips are attached and processed simultaneously. Consequently, a strip of semiconductor components is formed, which can be mechanically singulated, for example. One or more chips 50 can be attached to each segment of the strip to form a multi-chip package.

Further processing may also proceed in various embodiments, which may include forming backside and front side redistribution layers.

3 , the 3A - 3E 1 illustrates a semiconductor device during various stages of processing according to an alternative embodiment of the invention.

Regarding 3A In contrast to the previous embodiment in this embodiment, the panel 15 structured into smaller segments. In other words, in this embodiment, the plurality of openings 60 spaced closer than in the 2 described embodiments.

3B and 3C provide the semiconductor device after forming the encapsulating material 20 represents. 3B represents a top view while 3C represents a cross-sectional view.

3D FIG. 15 illustrates the semiconductor device after the formation of the contact openings. As in FIG 3D are shown, several contact openings 70 in the encapsulating material 20 educated. Unlike the in 2 described previous embodiment, the panel 15 containing the multiple openings 60 forms, removed, while the multiple contact openings 70 be formed. The laser drilling of the encapsulating material 20 For example, the fairing 15 remove. Alternatively, a wet etching process, which is used around the plurality of contact openings 70 after the laser drilling process to clean the cladding 15 take off. As in 3E Consequently, the contact connections can be represented 80 the chip pads 150 contact directly. In other words, unlike the previous embodiment, the contact connections make contact 80 the semiconductor chip 50 directly through a large opening in the panel 15 ,

4 , the 4A - 4F 1 illustrates a semiconductor device during manufacture in accordance with an alternative embodiment of the present invention.

In this embodiment, the chip pads are 150 self segmented. In this embodiment, the metal layer M4 and the contact hole layer V4 may be formed by a double damascene process or a contact hole and a single damascene process. In another embodiment, the metal layer M4 and the contact hole layer V4 may be formed by a pattern plating process.

Regarding 4A becomes a segmented chip pad 150 over a substrate 110 educated. In the substrate 110 Active devices may be formed. A set of metallization layers 130 is above the substrate 110 arranged, which in various embodiments may have one or more levels of metal lines and contact holes. The metallization layer 130 For example, in one embodiment, it may have ten or more metal levels. In another embodiment, the layer 130 have three metal layers. In another embodiment, the metallization layer 130 have four or more metal levels. The metallization layer 130 In one embodiment, various devices may be within the semiconductor chip 50 couple. In another embodiment, the metallization layer forms 130 Contacts with different areas of a discrete semiconductor device.

In various embodiments, the die pad is 150 with active devices in the substrate 110 such as B. a first device 105 coupled. The first action 105 For example, in various embodiments, it may be a transistor, a capacitor, a diode, a thyristor, and other devices. The chip contact point 150 In one embodiment, it may be an upper metallization layer of multi-level metallization. Several metal lines and contact holes, which are inside the metallization layer 130 can be arranged, the active devices in the substrate 110 with the chip pad 150 couple.

4A illustrates a four-level metallization having a first contact hole plane V1, a first metal plane M1, a second contact hole plane V2, a second metal plane M2, a third contact hole plane V3, a third metal plane M3, a fourth contact hole plane V4 connected to the chip pad 150 In one embodiment, the die pad is 150 a metal level at the top metal level of the semiconductor chip 50 is trained.

Each metallization plane may have a dielectric layer between the planes. A first dielectric layer 131 between the levels, for example, above the substrate 110 deposited. A second dielectric layer between the planes is over the first dielectric layer 131 deposited between the levels. A third dielectric layer 133 between the planes is above the second dielectric layer 132 deposited between the levels. A fourth dielectric layer 134 between the levels is above the third dielectric layer 133 deposited between the levels. A fifth dielectric layer 135 between the planes is above the fourth dielectric layer 134 deposited between the levels.

The dielectric layers between the planes may be separated by etch stop cladding. A first etch stop panel 121 is, for example, between the first and second dielectric layers 131 and 132 deposited between the levels. A second etch stop panel 122 is between the second and third dielectric layers 132 and 133 deposited between the levels. Likewise, a third etch stop fairing 123 between the third and fourth dielectric layers 133 and 134 deposited between the levels.

In the illustrated embodiments, the conductive features that form the metal lines and vias (eg, in M1, V1, M2, V2, M3, V3) are formed using a dual damascene process. In alternative embodiments, the conductive features may be formed using a damascene process or a combination of single and dual damascene processes.

Each conductive feature can be a metal cladding 102 have, which may have multiple layers. The metal panel 102 For example, in some embodiments, a first metal cladding 152 and a second metal panel 154 exhibit. The first metal panel 152 may be a diffusion barrier while the second metal cladding 154 may be a germ layer

As in 4A shown, points the chip pad 150 several contact point openings 170 on. 4B FIG. 12 is a plan view showing that the plurality of pad openings 170 within the chip pad 150 are distributed. Each chip contact point 150 can be a matrix of multiple contact point openings 170 exhibit. 4B For illustration only, three rows and five columns are shown. In various embodiments, more than ten openings may be within the die pad 150 be formed, which is the matrix of the plurality of contact point openings 170 form. 4B also shows that adjacent chip pads 150 may have similar openings. Each contact sub-contact point 150 can be connected either through contact holes V4 with the lower metal layer M3 (eg. 14 ) or by an electrical connection to the metal 4 (eg 15 - 16 ) be electrically connected.

4C FIG. 12 illustrates a cross-sectional view of the semiconductor device after forming a cladding and encapsulation material according to an embodiment of the present invention. FIG.

An optional fairing 15 is over the chip pad 150 formed, followed by the formation of an encapsulating material 20 as described in previous embodiments. The costume 15 can be omitted in various embodiments. In some embodiments, the fairing 15 only over the semiconductor chip 50 be trained as in 8th and 9 described. The costume 15 can act as a conformal panel over the multiple pad openings 170 be formed. Alternatively, the fairing 15 completely or partially the multiple contact point openings 170 to fill.

4D FIG. 12 illustrates a cross-sectional view of the semiconductor device after forming the contact openings according to an embodiment of the present invention. FIG.

As described in previous embodiments, contact openings 70 within the encapsulating material 20 educated. The contact openings 70 may be formed after a lithography process, for example, using an anisotropic etch process. Alternatively, the contact openings 70 using a Abschmelzprozesses such. B. a laser ablation process can be formed. The costume 15 after the removal of the encapsulating material 20 can be removed using a wet etching process.

In other embodiments, the fairing 15 on the contact point surface 150 removed at the wafer level.

4E and 4F FIG. 12 illustrates a cross-sectional view of the semiconductor device after filling the contact openings with a conductive material according to an embodiment of the present invention. FIG. 4F FIG. 12 is an enlarged cross-sectional view of FIG 4E shown semiconductor device.

Regarding 4E become contact openings 70 filled with a conductive material that has a metal cladding 81 ( 4F ) and a conductive filler 82 may have, as described in previous embodiments. The metal panel 81 may have a diffusion barrier (diffusion barrier) and a seed layer. The conductive filler 82 For example, it can be filled using a plating process.

As in 4F shown, the conductive filler material 82 the contact openings 70 (in 4D shown) and the plurality of contact point openings 170 (in the enlarged view of 4A shown) fill. Alternatively, in some embodiments, only the metal shroud 81 the multiple contact point openings 170 to fill. Advantageously, in this embodiment, the contact connection 80 a locking structure, resulting in improved adhesion to the chip pad 150 leads.

5 , the 5A - 5B 2 illustrates an alternate embodiment of the present invention in which the plurality of apertures in the die pad are spaced, facilitating the formation of spacers.

5A FIG. 12 illustrates a cross-sectional view of the semiconductor device after forming contact holes according to an embodiment of the present invention. FIG.

In this embodiment, the previous processing may be as described with respect to FIG 4A - 4D described. However, in some embodiments, the plurality of openings 170 the chip contact point 150 be spaced. The multiple contact openings 70 For example, by using a laser process through the encapsulating material 20 be formed through. However, the laser process can use the exposed cladding 15 Do not remove, which can then be removed using a wet etching process. In this embodiment, an anisotropic etch process is used to form the cladding 15 to remove what spacers 16 around the side walls of the plurality of contact hole openings 170 the chip contact point 150 leaves.

Regarding 5B become the multiple contact point openings 170 and the more contact openings 70 filled with a conductive material as described in previous embodiments. The subsequent processing can proceed as in conventional machining.

6 , the 6A - 6C 1 illustrates a semiconductor device according to various stages of manufacture according to an alternative embodiment of the present invention.

6A and 6B illustrate a semiconductor device after forming a plurality of pad openings with a die pad opening according to an embodiment of the present invention. 6A represents a cross-sectional view while 6B represents a top view.

In this embodiment, the chip pad is 150 partially segmented. Only part of the fifth dielectric layer 135 between levels, for example, after opening the chip pad 150 etched. The etching of the exposed fifth dielectric layer 135 For example, between the planes may be timed to stop before the underlying fourth etch stop fairing 124 is reached. Consequently, the plurality of contact point openings 170 in the chip pads 150 flatter than in previous embodiments of the invention.

However, since the dielectric layer 135 much thinner than the distance between the sub-pads 150 , becomes the dielectric layer 135 between the pads by either pad-level wafer-level or by the laser drilling process. Thus, in this embodiment, the final structure is similar to that in FIG 4 illustrated final structure.

With reference next 6C becomes the conductive filler 82 deposited as described in previous embodiments. Subsequent processing continues as previously described in previous embodiments.

7 , the 7A - 7E 1 illustrates a semiconductor device during manufacture in accordance with an alternative embodiment of the present invention.

In this embodiment, the panel 15 deposited during the wafer manufacturing process. After completing the metallization levels with the chip pads 150 becomes a disguise 15 over the wafer 100 deposited. This advantageously becomes a wafer level process prior to singulation of the wafer 100 into individual chips 50 carried out. Therefore, a single process can be the panel 15 as a cover over the wafer 100 deposit.

In further embodiments, an optional thick passivation layer may be formed over the pad area on a wafer plane and opened. An imide layer may be formed over the passivation layer and may cover the pad area during the assembly process. The imide layer over the pad area can be removed during the formation of the opening of the chip connection. Such alternative embodiments are disclosed in further embodiments of 10 - 16 described.

With reference next 7B becomes the fairing 15 structured to multiple openings 60 train. The costume 15 In one embodiment, it may be patterned using conventional lithography processes.

Regarding 7C becomes the wafer 100 isolated, to individual semiconductor chips 50 form over the substrate 100 be arranged as before with respect to 3 described.

Subsequent editing may be with reference to 2 follow described processing. As in next 7D is thus an encapsulating material 20 over the (or more) semiconductor chip (s) 50 applied and partially encloses the semiconductor chip 50 , Multiple contact openings 70 become inside the encapsulating material 20 educated.

With reference next 7E become the multiple contact openings 70 and filling the plurality of via holes with a conductive material. A metal panel 81 can within the multiple contact openings 70 and the plurality of through-hole openings are formed. A conductive filler 82 gets into the multiple contact holes 70 and filling the plurality of via holes. The conductive filler 82 is structured to contact connections 80 and form openings through the substrate.

8th , the 8A - 8D 1 illustrates a semiconductor device during manufacture in accordance with an alternative embodiment of the present invention.

Similar to the in 7 described embodiment and in contrast to for reference to 2 and 3 described embodiments, in this embodiment, the panel 15 formed during wafer plane processing.

Regarding 8A In contrast to the previous embodiment in this embodiment, the panel 15 structured into smaller segments. In other words, in this Embodiment and similar to that using 3 described embodiment, the plurality of openings 60 spaced closer than in the 2 and 7 described embodiments.

8B provides the semiconductor device after singulation of the wafer 100 and attaching the singulated semiconductor chip 50 on a substrate 10 represents.

8C provides the semiconductor device after forming the encapsulating material 20 and the plurality of contact openings 70 as in 8C are shown, several contact openings 70 in the encapsulating material 20 educated. Unlike the in 2 and 7 described previous embodiment, the panel 15 containing the multiple openings 60 forms, removed, while the multiple contact openings 70 be formed.

As in next 8D shown, the contact connections 80 directly the chip contact points 150 to contact. In other words, in contrast to the previous embodiments of 2 and 7 can the contact connections 80 the semiconductor chip 50 contact directly.

9 , the 9A - 9D 1 illustrates a semiconductor device according to an embodiment of the present invention.

Embodiments of the present invention may be applied to multiple chips in various embodiments. Consequently, the semiconductor module 1 more than one semiconductor chip 50 exhibit. As an illustration only, there are only two semiconductor chips 50 in 9 shown.

Regarding 9A become semiconductor chips 50 over a substrate 10 arranged, which may be a lead frame or other frame. The semiconductor chips 50 can have multiple chip pads 150 on one side and backside contacts 151 on the other side. The backside contacts 151 can with the substrate 10 be coupled using a conductive bond, which in one embodiment may be a solder bond. The substrate 10 can with a first side of the semiconductor device using contact holes 85 be coupled by the encapsulating material. Furthermore, the plurality of chip pads 150 with external contact points through contact connections 80 be coupled.

9B FIG. 12 illustrates another alternative embodiment in which the semiconductor chips 50 over electrically separated substrates 10 , For example, over a first chip island and a second chip island of a lead frame, are arranged.

9C represents an alternative embodiment of 9A in which the paneling 15 during wafer level processing. Therefore, the disguise 15 not over the substrate 10 arranged.

Likewise 9D an alternative embodiment of 9B in which the paneling 15 during wafer level processing. Therefore, the disguise 15 not over the substrate 10 arranged.

10 - 16 illustrate further embodiments of the present invention and illustrate only the semiconductor device after the completion of the wafer level processes and after the completion of the assembly process. For the sake of brevity, the intermediate stages that may follow the previous embodiments will not be described.

10 , the 10A - 10E 1 illustrates a semiconductor device according to an embodiment of the present invention in which the patterned dielectric cladding forms segmented pad contacts. 10A FIG. 12 is a cross-sectional view after wafer plane processing; FIG. 10B - 10D represent the corresponding plan view of the chip pad and 10E illustrates the cross-sectional view of the semiconductor device after the formation of the contact connection.

In this embodiment, a polyimide layer is used 210 over the structured dielectric panel 15 educated. The polyimide layer 210 may be omitted in some embodiments, such as in FIG 7 shown.

As in the top view of 10B - 10D shown, the structured dielectric cladding 15 be formed as rectangular areas, circular areas or multiple lines.

10E provides the semiconductor device after forming an encapsulating material 20 and a chip connection 80 through the encapsulating material 20 dar. The polyimide layer 210 over the pad area may during formation of the opening for the chip connection 80 be removed. For example, a laser drilling process may be performed by the encapsulating material 20 through and into the polyimide layer 210 progress.

11 , the 11A - 11D 1 illustrates a semiconductor device according to an embodiment of the present invention in which the patterned dielectric cladding is lifted off during the formation of the contact connection opening. 11A FIG. 12 is a cross-sectional view after wafer plane processing; FIG. 11B - 11C make the appropriate Top view of the chip contact point and 11D illustrates the cross-sectional view of the semiconductor device after the formation of the contact connection.

Similar to 3 or 8th In this embodiment, the segmented or patterned dielectric cladding 15 during the subsequent processing lifted. The textured dielectric panel 15 For example, during the formation of the opening for the chip connection 80 away.

In the 11 illustrated embodiment includes the additional polyimide layer 210 , which may be optional, for example as in 3 or 8th not shown.

12 , the 12A - 12E 1 illustrates a semiconductor device according to an embodiment of the present invention in which a two layer dielectric cladding is used to form a patterned dielectric cladding. 12A FIG. 12 is a cross-sectional view after wafer plane processing; FIG. 12B - 12D represent the corresponding plan view of the chip pad and 12E illustrates the cross-sectional view of the semiconductor device after the formation of the contact connection.

In this embodiment, the patterned dielectric cladding 15 a first layer 15A and a second layer 15B include. The first shift 15A can be removed from above the die pad area and a second layer 15B can be separated. The second layer 15B is then structured. As a result, the other areas of the chip are protected by a thick passivation layer.

As described in previous embodiments, the polyimide layer 210 although in 12 shown, may be optional, and may be omitted in other alternative embodiments. Alternatively, the polyimide layer 210 be removed from above the contact point surface.

13 , the 13A - 13D FIG. 2 illustrates a semiconductor device according to an alternative embodiment of the present invention, wherein a two layer dielectric cladding is used to form a patterned dielectric cladding. 13A FIG. 12 is a cross-sectional view after wafer plane processing; FIG. 13B - 13C represent the corresponding plan view of the chip pad and 13D illustrates the cross-sectional view of the semiconductor device after the formation of the contact connection.

Although this embodiment is similar to the previous embodiment and a first layer 15A and a second layer 15B includes, in this embodiment, the second layer 15B completely removed during the etching to form the opening for the chip connection. As in previous embodiments, the polyimide layer 210 can be omitted or can only be removed over the contact patch area.

14 , the 14A - 14E 1 illustrates a semiconductor device according to an embodiment of the present invention in which each sub-structure having a patterned chip contact pad is coupled to an underlying contact hole. 14A FIG. 12 is a cross-sectional view after wafer plane processing; FIG. 14B - 14D represent the corresponding plan view of the chip pad and 14E illustrates the cross-sectional view of the semiconductor device after the formation of the contact connection.

This embodiment is similar to that with reference to FIG 4 described embodiment. In contrast to 4 However, in this embodiment, each is a structured chip pad 150 coupled to an underlying metal line of the uppermost metal level through a contact hole plane. The contact holes are separated by a dielectric layer between the metal (IMD). In contrast to the embodiment of 4 Consequently, there is the possibility of higher contact resistance (eg due to misalignments) of the chip connection 80 mitigated.

As in 14A is a dielectric cladding 15 over the structured chip pad 150 educated. An optional polyimide layer 210 can over the dielectric cladding 15 be educated. Alternatively, the polyimide layer 210 only be removed from above the contact patch surface. As in next 14E As shown, the semiconductor device is encapsulated in an encapsulating material 20 and forming a chip connection 80 capsuled.

15 , the 15A - 15D 1 illustrates a semiconductor device according to an embodiment of the present invention in which the patterned die pad is coupled by an outer edge. 15A FIG. 12 is a cross-sectional view after wafer plane processing; FIG. 15B - 15C represent the corresponding plan view of the chip pad and 15D illustrates the cross-sectional view of the semiconductor device after the formation of the contact connection.

In contrast to the previous embodiment of 14 In this embodiment, each of the sub-structures of the chip pad is 150 coupled together by an outer section. The chip contact points 150 For example, they are structured as multiple lines that may have been coupled together by another section (eg. 15C ). As in previous embodiments, the polyimide layer 210 can be omitted or can only be removed over the contact patch area.

15D provides the semiconductor device after forming the chip connection 80 through the encapsulating material 20 through.

16 , the 16A - 16D 1 illustrates a semiconductor device according to an alternative embodiment of the present invention in which the patterned die pad is coupled by an outer edge. 16A FIG. 12 is a cross-sectional view after wafer plane processing; FIG. 16B - 16C represent the corresponding plan view of the chip pad and 16D illustrates the cross-sectional view of the semiconductor device after the formation of the contact connection.

This embodiment is similar to 15 and has an outer edge portion, which is the partial structures of the structured chip pad 150 couples, up. However, this embodiment also has a two-ply cladding, as previously described in U.S. Patent Nos. 4,912,355 12 and 13 described on. As in previous embodiments, the polyimide layer 210 can be omitted or can only be removed over the contact patch area.

Although this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments as well as other embodiments of the invention will be apparent to those skilled in the art upon reference to the specification. As an explanation, the in 1 - 16 described embodiments may be combined with each other in various embodiments. Therefore, it is intended that the appended claims encompass any such modifications or embodiments,

Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be changed while remaining within the scope of the present invention.

Moreover, the scope of the present application should not be limited to the specific embodiments of the process, machine, manufacture, composition, means, methods, and steps described in the specification. As one of ordinary skill in the art readily recognizes from the disclosure of the present invention, processes, machines, manufacture, compositions, means, methods, or steps that exist or are to be developed later may perform substantially the same function or substantially achieve the same result as the corresponding embodiments described herein, used in accordance with the present invention. Accordingly, it is intended that the appended claims within their scope have such processes, machines, manufacture, compositions, means, methods, or steps.

Claims (27)

A semiconductor device, comprising: a first semiconductor chip ( 50 ) having a first side and an opposite second side; a first chip pad ( 150 ) located on the first side of the first semiconductor chip ( 50 ) is arranged; a dielectric lining ( 20 ) located above the first semiconductor chip ( 50 ), wherein the dielectric cladding ( 20 ) a plurality of first openings ( 80 ) over the first chip pad ( 150 ) having; and a first connection connecting the first semiconductor chip ( 50 ) through the plurality of first openings ( 80 ) through at the first chip pad ( 150 ) contacted. The device of claim 1, further comprising an encapsulation material surrounding the first semiconductor chip ( 50 ), wherein the first connection is arranged in encapsulation material. The device of claim 2, further comprising a conductive plate, wherein the first semiconductor chip ( 50 ) is arranged above the conductive plate, wherein the dielectric lining ( 20 ) is disposed over the conductive plate, and wherein the encapsulating material over the dielectric cladding ( 20 ) is arranged. The device of claim 2, further comprising a conductive plate, wherein the first semiconductor chip ( 50 ) is disposed over the conductive plate, wherein the encapsulating material is disposed over the conductive plate. The device of any one of claims 1 to 4, further comprising: a second chip pad ( 92 ) located on the first side of the first semiconductor chip ( 50 ) is arranged; a plurality of second openings formed in the dielectric cladding ( 20 ) are disposed over the second die pad; and a second connection connecting the first semiconductor chip ( 50 ) is contacted by the plurality of second openings at the second die pad. The device of one of claims 1 to 5, further comprising: a second semiconductor chip, the second semiconductor chip having a first side and an opposite second side; a second chip pad ( 91 ) disposed on the first side of the second semiconductor chip, wherein the dielectric cladding ( 20 ) is disposed over the second chip, and wherein the dielectric cladding ( 20 ) has a plurality of second openings above the second die pad; and a second connection contacting the second semiconductor chip through the plurality of second openings at the second die pad; wherein the device preferably further comprises a conductive plate, wherein the first semiconductor chip ( 50 ) and the second semiconductor chip are disposed over the conductive plate. A semiconductor device, comprising: a first semiconductor chip ( 50 ) having a first side and an opposite second side; a first chip pad ( 150 ) located on the first side of the first semiconductor chip ( 50 ), wherein the first chip pad ( 150 ) a plurality of first openings ( 80 ) having; and a first connection connecting the first semiconductor chip ( 50 ) through the plurality of first openings ( 80 ) through at the first chip pad ( 150 ) contacted. The device of claim 7, further comprising an encapsulation material surrounding the first semiconductor chip ( 50 ), wherein the first compound is disposed in the encapsulating material. Apparatus according to claim 7 or 8, further comprising a conductive plate, wherein the first semiconductor chip ( 50 ) is disposed over the conductive plate, wherein the encapsulating material is disposed over the conductive plate. Apparatus according to any one of claims 7 to 9, further comprising: a second die pad (10); 91 ) located on the first side of the first semiconductor chip ( 50 ) is arranged; a plurality of second openings disposed in the second die pad; and a second connection connecting the first semiconductor chip ( 50 ) through the plurality of second openings at the second die pad ( 91 ) contacted. The device of any one of claims 7 to 10, further comprising: a second semiconductor chip having a first side and an opposite second side; a second chip pad ( 91 ) disposed on the first side of the second semiconductor chip, the second die pad having a plurality of second openings; and a second connection contacting the second semiconductor chip through the plurality of second openings at the second die pad; wherein the device preferably further comprises a conductive plate, wherein the first semiconductor chip ( 50 ) and the second semiconductor chip are disposed over the conductive plate. Apparatus according to any one of claims 7 to 11, further comprising spacers formed around side walls of the plurality of first openings (10). 80 ) of the first chip pad ( 150 ) are arranged. A method of forming a semiconductor device, the method comprising: providing a first semiconductor chip ( 50 ) having a first side and an opposite second side; Attaching the second side of the first semiconductor chip ( 50 ) on a conductive plate, wherein the first semiconductor chip ( 50 ) a first chip pad ( 150 ) on the first side; Forming a dielectric lining ( 20 ) over the first semiconductor chip ( 50 ); Structuring a part of the dielectric lining ( 20 ) over the first chip pad ( 150 ); Forming an encapsulation material over the first semiconductor chip ( 50 ); and forming a bond through the encapsulating material and the structured one; Part of the dielectric lining ( 20 ) through to the first chip pad ( 150 ). The method of claim 13, wherein forming the connection comprises attaching a wire. The method of claim 13, wherein forming the connection comprises: forming a connection opening ( 80 ) in the encapsulating material ( 20 ) to the structured part of the dielectric lining ( 20 ) uncover; and filling the connection opening with a conductive material; wherein, preferably, forming the connection opening removes the exposed structured portion of the dielectric cover (10). 20 ) after forming the connection opening ( 80 ) having; and / or wherein preferably the formation of the connection opening ( 80 ) has the use of a pulsed laser process. The method of any one of claims 13 to 15, wherein attaching the second side of the first semiconductor chip ( 50 ) has on the conductive plate the use of a soldering process or a pressure-sensitive adhesive. The method of any one of claims 13 to 16, wherein the conductive plate is a chip island of a leadframe. A method according to any one of claims 13 to 17, wherein forming the dielectric cladding ( 20 ) over the first semiconductor chip ( 50 ) and the structuring of the part of the dielectric lining ( 20 ) over the first chip pad ( 150 ) Comprise: forming a first layer over the first semiconductor chip ( 50 ); Patterning the first layer to the first chip pad ( 150 ) uncover; Depositing a second layer over the first layer and the exposed first die pad ( 150 ); and patterning the second layer to include portions of the first die pad ( 150 ). The method of any of claims 13 to 18, further comprising forming an imide layer over the second layer prior to forming the encapsulating material. The method of any one of claims 13 to 19, further comprising forming an imide layer prior to forming the encapsulating material. A method of forming a semiconductor device, the method comprising: providing a first semiconductor chip ( 50 ) having a first side and an opposite second side; Attaching the second side of the first semiconductor chip ( 50 ) on a conductive plate, wherein the first semiconductor chip ( 50 ) a first chip pad ( 150 ) on the first side; Structuring a portion of the first die pad ( 150 ) to openings ( 80 ) in the first chip pad ( 150 ) to train; Forming an encapsulation material over the first semiconductor chip ( 50 ); and forming a connection through the encapsulating material and the openings ( 80 ) of the first chip pad ( 150 ). The method of claim 21, wherein forming the connection comprises: forming a connection opening ( 80 ) in the encapsulating material ( 20 ); and filling the connection opening ( 80 ) with a conductive material. The method of claim 21 or 22, wherein forming the connection comprises attaching a wire. Method according to one of claims 21 to 23, wherein the forming of the connection opening ( 80 ) has the use of a pulsed laser process. The method of any one of claims 21 to 24, wherein attaching the second side of the first semiconductor chip ( 50 ) has on the conductive plate the use of a soldering process or a pressure-sensitive adhesive. The method of any one of claims 21 to 25, wherein the conductive plate is a chip island of a leadframe. The method of any of claims 21 to 26, further comprising forming an imide layer prior to forming the encapsulating material.

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