DE102013101441A1 - Memory system transfers error address detected by test apparatus to memory device, and stores detected error address in non volatile memory device - Google Patents

Abstract

The memory system has a memory device (200) with a non volatile memory device that is provided with a matrix array structure. A test apparatus (100) e.g. semiconductor chip is provided for testing the memory device. An error address detected by the test apparatus is transferred to the memory device, and is stored in the non volatile memory device. An error address memory is controlled by a control unit. Independent claims are included for the following: (1) a method for operating test apparatus; and (2) a method for operating memory device.

Description

BACKGROUND

area

Embodiments of the inventive concept relate to a memory system, and more particularly to a method and apparatus for repairing a memory cell by testing the memory device having a non-volatile memory device using a test device and a system including the device.

Description of the Prior Art

A semiconductor chip is fabricated in accordance with a semiconductor manufacturing process and is then tested in the form of a wafer, die, or package using test equipment. Through the test, a defective section or a defective chip can be sorted out. If some memory cells of a semiconductor chip are defective, the semiconductor chip is repaired by restoring such defective memory cells.

Recently, after a process for manufacturing a semiconductor chip such as Dynamic Random Access Memory (DRAM) has become finer and finer, errors are much more likely to occur during the manufacturing process. Likewise, even if no error is detected during an initial test period, an error may occur during operation of a chip. To solve this problem, various test methods and devices have been developed.

SHORT VERSION

Embodiments of the inventive concept provide a test device for reliably repairing a memory cell.

Embodiments of the inventive concept also provide a test method for reliably repairing a memory cell.

Embodiments of the inventive concept also contemplate a memory system having a test device and a method for reliably repairing a memory cell.

The technical tasks of the inventive concept are not limited to the above disclosure. Other objects may become apparent to those skilled in the art from the following description.

In accordance with one aspect of the inventive concept, a memory system comprises a memory device having a nonvolatile memory device having a matrix array structure of at least NxM, where N and M each denote an integer equal to or greater than 2 ; and a test device configured to test the memory device. An error address detected by the test apparatus is transmitted to the storage device and is stored in the non-volatile storage device.

In an embodiment, the test device may comprise a semiconductor chip.

In one embodiment, the semiconductor chip may include an error correcting code (ECC) engine, and the nonvolatile memory device may include an anti-fuse array having a matrix array structure of at least NxM, where N and M each denote an integer equal to or greater than 2.

In one embodiment, the semiconductor chip may include a built-in self test (BIST) unit, and the nonvolatile memory device may include an anti-fuse array having a matrix array structure of at least NxM, where N and M each denote an integer equal to or greater than 2.

In one embodiment, the BIST unit may be connected to the ECC machine.

In one embodiment, the semiconductor chip may include an error correcting code (ECC) engine or built-in self test (BIST) unit and an error address memory configured to the fault address.

In one embodiment, the fault address memory may be controlled by a controller.

In one embodiment, the semiconductor chip may include an Error Correcting Code (ECC) engine or built-in self test (BIST) unit, an error address memory, an address output unit, a control output unit, a data buffer and a control unit.

In one embodiment, the control output unit may control the operation of the ECC engine or the BIST unit, the error address memory, the data buffer and the control unit.

In an embodiment, the semiconductor chip may be included in a memory controller and connected to a central processing unit (CPU).

In one embodiment, the CPU may provide a test command for the storage device.

In one embodiment, the test command may include a test start command, a test end command, or an error address transfer command.

In one embodiment, the test device may be included in a test kit.

In one embodiment, the test equipment may include a pattern generator, a probe card, and a socket.

In one embodiment, the nonvolatile memory device may include an anti-fuse arrangement having a matrix array structure of at least NxM, where N and M each denote an integer equal to or greater than two.

In one embodiment, the memory system may further include a temporary fault address memory configured to store the fault address.

In one embodiment, the error address may be stored in the anti-fuse arrangement under the control of the controller.

In one embodiment, the controller may be activated in response to a mode enable signal received from a decoder unit.

In one embodiment, the control unit controls the error address to be written or read to or from the anti-fuse device and a verification result to be transmitted outside the memory device.

In one embodiment, the anti-fuse arrangement may be connected to a repair address memory configured to store the error address, the repair address memory may be connected to a comparison unit configured to address the error address with an external address and the comparison unit may be connected to a multiplexer configured to select one of the error address and the external address.

In accordance with one aspect of the inventive concept, a memory device comprises a temporary error address memory for provisionally storing the error address; a non-volatile memory device having a matrix arrangement structure of at least N × M to store the error address, wherein N and M each denote an integer equal to or greater than 2; and a control unit configured to control transmission of the error address stored in the provisional error address memory to the nonvolatile memory device.

In one embodiment, the nonvolatile memory device may include an anti-fuse arrangement.

In one embodiment, to determine whether the error address is being accurately written, the controller may check the error address to be read from the anti-fuse array and a verification result to be transmitted outside the memory device.

In one embodiment, the control unit may control the anti-fuse arrangement to be scanned or programmed.

In one embodiment, the anti-fuse arrangement may be connected to a repair address memory configured to store the error address, the repair address memory may be connected to a comparison unit configured to address the error address with an external address and the comparison unit may be connected to a multiplexer configured to select one of the error address and the external address.

In one embodiment, the temporary error address memory may be connected to an address buffer configured to receive an external address.

In one embodiment, the controller may be activated in accordance with a mode enable signal generated by a decoder unit.

In one embodiment, the decoding unit may be connected to the address buffer and a control buffer configured to receive a control signal.

In accordance with another aspect of the inventive concept, a test device includes an error correcting code (ECC) circuit configured to detect and correct an error bit; an error address memory which is configured to store an error address of the error bit; and a control unit configured to control the error address to be stored in the error address memory and to be externally transmitted in accordance with a test command.

In an embodiment, the ECC circuit may be connected to a data buffer configured to receive the error bit.

In one embodiment, the test command may include a test start command, a test end command, or an error address transfer command.

In one embodiment, the ECC circuit may include a built-in self test (BIST) unit.

In one embodiment, the test device may be included in a memory controller or memory controller and connected to a central processing unit (CPU).

In one embodiment, the test device may be included in a test kit.

In one embodiment, the test equipment may further include a pattern generator, a probe card, and a socket.

In accordance with another aspect of the inventive concept, a method of operating a test device to transmit an error address includes detecting the error address using an error correcting code (ECC) circuit; storing the error address in an error address memory; entering an error address transfer mode according to a test command; transmitting a transmission signal having a mode register setting command; and transmitting the error address.

In one embodiment, the error address may be detected by an ECC machine or built-in self test (BIST) unit.

In one embodiment, the transmit signal may further include a write command and a chip select signal.

In one embodiment, the test instruction may include a command instructing to start the transmission of the error address, or a command instructing to terminate the transmission of the error address, and is given by a central processing unit (CPU).

In accordance with another aspect of the inventive concept, a method of operating a memory device to write a fault address to the memory device includes receiving the fault address according to a mode register setting command; storing the error address in a temporary error address memory; and storing the error address in a nonvolatile memory device having a matrix array structure of at least N × M, where N and M each denote an integer equal to or greater than 2.

In one embodiment, before the error address is stored in the nonvolatile memory device, the method may further include checking a memory location of the nonvolatile memory device.

In one embodiment, after the error address is stored in the nonvolatile memory device, the method may further comprise reading the stored error address.

In one embodiment, after the stored error address is read, the method may further include transmitting a verification result in series or in parallel outwards indicating a state of the read error address.

In accordance with another aspect of the inventive concept, a method of operating a test device to transmit a fault address to a memory device comprises detecting the fault address by an error correction code (ECC) circuit; storing the error address in an error address memory; entering an error address transfer mode according to a test command; transmitting a transmission signal having a mode register setting command; transmitting the error address; receiving the error address in accordance with the mode register setting signal; storing the error address in a temporary error address memory; and storing the error address in a nonvolatile memory device having a matrix array structure of at least N × M, where N and M each denote an integer equal to or greater than 2.

In one embodiment, before the error address is stored in the non-volatile memory device, the method may continue Check a storage space of the nonvolatile memory device.

In accordance with another aspect of the inventive concept, a memory system includes a test device configured to provide test data for a memory device; and the storage device having a built-in self-test (BIST) unit configured to test the storage device; and a nonvolatile memory device having a matrix array structure of at least N × M, wherein N and M each denote an integer equal to or greater than 2. An error address generated by testing the memory device by the BIST unit is stored in the nonvolatile memory device.

In one embodiment, the nonvolatile memory device may include an anti-fuse arrangement having a matrix array structure of at least NxM, where N and M each denote an integer equal to or greater than two.

In one embodiment, the memory device may further include at least two error address register arrangements configured to temporarily store the error address.

In one embodiment, the BIST unit may transmit the error address to the at least two error address storage registers according to an error flag.

In one embodiment, the error generation flag is replaceable by a pre-charge command.

Brief description of the drawings

The foregoing and other features and advantages of the inventive concepts will become apparent from the more particular description of preferred embodiments of the inventive concepts illustrated in the accompanying drawings, in which like reference numerals refer to like parts throughout the several views. The drawings are not necessarily to scale, emphasis instead being placed upon an illustration of the principles of the inventive concepts. In the drawings:

1 - 4 are conceptual representations of storage systems in accordance with embodiments of the inventive concept;

5 Fig. 10 illustrates a circuit block of a test device in accordance with an embodiment of the inventive concept;

6A FIG. 10 is a diagram illustrating a system-on-chip (SOC) system having a test device therein in accordance with an embodiment of the inventive concept; FIG.

6B Fig. 10 is a diagram illustrating a test equipment using a test apparatus in accordance with an embodiment of the inventive concept;

7 Fig. 10 illustrates a circuit block of a memory device in accordance with an embodiment of the inventive concept;

8th Fig. 10 is a diagram illustrating a nonvolatile memory device in accordance with an embodiment of the inventive concept;

9 illustrates a structure of a module in accordance with an embodiment of the inventive concept;

10 and 11 10 are timing diagrams illustrating a timing when an error address is transmitted in accordance with an embodiment of the inventive concept;

12 FIG. 13 is a timing chart illustrating a timing when a verification result is transmitted in parallel in accordance with an exemplary embodiment of the inventive concept; FIG.

13 FIG. 13 is a table illustrating verification results to be transmitted in parallel in accordance with an exemplary embodiment of the inventive concept; FIG.

14 FIG. 10 is a timing chart illustrating a timing when transmitting verification results in accordance with an exemplary embodiment of the inventive concept; FIG.

15 FIG. 13 is a table illustrating verification results to be transmitted in series in accordance with an exemplary embodiment of the inventive concept; FIG.

16 and 17 FIG. 5 are timing diagrams illustrating a method of operating a test device in accordance with an exemplary embodiment. FIG Embodiment of the inventive concept illustrate;

18 FIG. 10 is a conceptual diagram of a memory system in accordance with another exemplary embodiment of the inventive concept; FIG.

19 Fig. 10 illustrates a circuit block of a memory device in accordance with another embodiment of the inventive concept;

20 and 21 13 are timing diagrams illustrating an operation of a memory device in accordance with an exemplary embodiment of the inventive concept;

22 FIG. 10 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the inventive concept; FIG.

23 Fig. 12 is a diagram illustrating optical connections of a memory system in accordance with an exemplary embodiment of the inventive concept;

24 FIG. 13 illustrates layered through silicon via (TSV) chips to which a memory system in accordance with an exemplary embodiment of the inventive concept is applied; FIG.

25 illustrates various interfaces of a memory system in accordance with an exemplary embodiment of the inventive concept; and

26 and 27 FIGURES are diagrams illustrating system interconnections of a memory system in accordance with exemplary embodiments of the inventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various embodiments will now be described more fully with reference to the accompanying drawings, in which some embodiments are shown. However, the inventive concept may be embodied in various forms and should not be construed as limited to the embodiments discussed herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the inventive concept to those skilled in the art. In the drawings, like reference numerals designate like elements, and the sizes and relative sizes of layers and regions may be exaggerated for clarity.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting to the present inventive concept. As used herein, the singular forms "one" and "the" are intended to encompass the plural forms as well, unless the context clearly indicates otherwise. It will further be understood that the words "pointing to" and / or "having" when used in this specification specify the presence of said features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms such as those defined in commonly used dictionaries are to be interpreted as having the meaning consistent with their meaning in the context of the relevant area, and will not be idealized or overly formal sense, unless expressly so defined herein.

The 1 - 4 are conceptual representations of storage systems in accordance with embodiments of the inventive concept.

Referring to 1 For example, a memory system has a testing device 100 and a storage device 200 on. The test device 100 A control signal having an error address transmits a command instructing the storage device 200 to operate, and data DQ. Although not shown, the test device may 100 be contained in a memory controller or a memory control device or a test equipment. The storage device 200 has a dynamic random access memory (DRAM), which is a volatile memory. Alternatively, the storage device 200 a non-volatile memory such as a magnetoresistive RAM (MRAM), a resistive RAM (Resistive RAM), a phase change RAM (PRAM = Phase Change RAM) or a NAND flash memory. The storage device 200 includes a nonvolatile memory device having an anti-fuse arrangement. The nonvolatile memory device is used to store the error address. The nonvolatile memory device may include an MRAM, an RRAM, a PRAM, a NAND flash memory, or the like. The storage device 200 operates in accordance with the control signal and transmits the data DQ to the test device 100 ,

Referring to 2 has a test device 100 an Error Correcting Code (ECC) engine. The ECC engine detects an error bit and an error address from data DQ derived from a memory device 200 and corrects the error bit. The storage device 200 has an anti-fuse arrangement and stores the error address, which is from the test device 100 Will be received. An error memory cell is repaired based on the stored error address.

Referring to 3 has a test device 100 a built-in self-test (BIST) unit on. The BIST unit tests the test device 100 or the storage device 200 , To the storage device 200 test data is generated, and to the storage device 200 transfer. An error memory cell is detected by writing the test data to a memory cell and then reading the test data from the memory cell. An error address, which is the address of the failed memory cell or failed memory cell, temporarily becomes in the test device 100 and then becomes the storage device 200 transfer. The transmitted error address is stored in an anti-fuse arrangement to repair the fault memory cell.

Referring to 4 has a test device 100 a BIST unit and an ECC machine. A storage device 200 is tested using the BIST unit, and an error address is placed in an anti-fuse array which is in the memory device 200 is stored. The error address, which is the address of an error bit, which occurs during operation of the memory device 200 occurs is detected using the ECC machine and is in the anti-fuse arrangement of the memory device 200 saved. When the storage device 200 not working, the storage device can 200 be tested using the BIST unit according to a test command given by a central processing unit (CPU). While the storage device 200 works, the error address can be detected using the ECC machine.

5 illustrates a circuit block of a test device 100 in accordance with an embodiment of the inventive concept.

Referring to 5 has the test device 100 an error address memory 110 , an ECC machine (or BIST unit) 120 , a control unit 130 , an address output buffer 140 , a control output unit 150 and an input / output (I / O) data buffer 160 on. The error address memory 110 stores an error address ADD 141 , which through the ECC machine (or BIST unit) 120 is detected. The error address memory 110 may be implemented as a register, static random access memory (SRAM), or nonvolatile memory. The address output buffer 140 is with the error address memory 110 connected and transmits the error address ADD 141 to the storage device 200 , The control output unit 150 transmits a control signal 151 which has a read command, a write command, a pre-load command, a mode register setting command, and the like, to the memory device 200 , The control output unit 150 is connected to and controlled by a control unit 130 , The I / O data buffer 160 is through the control unit 130 controls and receives or transmits input / output (I / O) data. The I / O data only likes test data for testing the storage device 200 exhibit. Data from the storage device 200 will be received to the ECC machine (or BIST unit) 120 via the I / O data buffer 160 transfer. The control unit 130 is with the ECC machine (or BIST unit) 120 , the error address memory 110 , the address output unit 140 , the control output buffer 150 and the I / O data buffer 160 connected. The control unit 130 receives a test command from a CPU. The test command may include a test start command, a test end command, a command commanding to start the transmission of the error address ADD, and an instruction commanding to terminate the transmission of the error address ADD. The error address ADD 141 , which through the ECC machine (or BIST unit) 120 is detected is controlled so that they are in the error address memory 110 stored according to the received test command. Likewise, the transmission of the error address ADD 141 and the control signal 151 using the address output unit 140 and the control output unit 150 controlled.

6A FIG. 13 is an illustration showing a system-on-chip (SOC) system. FIG. 1100 which illustrates a test device 100 in it Having agreement with an embodiment of the inventive concept.

Referring to 6A assigns the SOC 1100 a CPU 1120 , a memory controller or a memory controller 1110 and an interface 1130 on. The memory controller 1100 has the test device 100 on. The test device 100 has an ECC machine (or BIST unit) 120 , an error address memory (FAM = Fail Address Memory) 110 , a control unit, etc. on which elements of the test device 100 , what a 5 is illustrated. The memory controller 1110 is with the CPU 1120 connected to a test command Com from the CPU 1120 to recieve. The test command Com may include a test start command, a test end command, a command commanding to start transmission of an error address, and an instruction commanding to stop transmission of the error address. An error address, a control signal and data become the memory device 200 over the interface 1130 transfer.

6B is a representation of what a test equipment 1200 which is a test device 100 used in accordance with an embodiment of the inventive concept.

Referring to 6B has the test equipment 1200 the test device 100 , a pattern producer 1210 , a probe card 1220 and a socket or a female connector 1230 on. The pattern producer 1210 generates various test data for the test storage device 200 , The inspection card 1220 contacts a test pad of the memory device 200 directly via a test needle to transfer the test data. The socket or the socket 1230 fixes the storage device 200 during a test of the storage device 200 ,

7 illustrates a circuit block of a memory device 200 in accordance with an embodiment of the inventive concept.

Referring to 7 has the storage device 200 an address buffer 210 , a control buffer 220 , a data buffer 230 , a decoding unit 240 , a repair address register 250 , a comparison unit 251 , a multiplexer (Mux) 252 , a temporary error address memory 260 , a control unit 270 , an anti-fuse arrangement 280 , which is a nonvolatile memory device, and a memory cell array 290 on.

An error address is sent via the address buffer 210 is received and temporarily in the temporary error address memory 260 saved. The temporary error address memory 260 may be implemented as a register arrangement, an SRAM or a nonvolatile memory. The decoding unit 240 receives a control signal via the control buffer 220 performs decoding and generates a mode enable signal. The control signal includes a read command, a write command, a pre-charge command, a mode register setting signal, and the like. The control unit 270 is activated in accordance with the mode enable signal and stores the error address in the anti-fuse array 280 , which is a nonvolatile memory device. The control unit 270 samples the stored error address to verify that the error address is accurately programmed. A result of the programming (verification result) becomes the test apparatus 100 transmitted via a data output pin. The anti-fuse arrangement 280 , which is a nonvolatile memory device, is connected to the repair address register 250 , which is configured to store the error address, connected. The repair address register 250 is with the comparison unit 251 which is configured to compare the error address with an external address. The comparison unit 251 is with the multiplexer (mux) 252 which is configured to select one of the error address and the external address. Data which is sent via the I / O data buffer 230 can be used as a chip select signal (component designation) for selecting a chip on a memory module.

8th FIG. 13 is a diagram showing a nonvolatile memory device. FIG 1000 illustrated in accordance with an embodiment of the inventive concept.

Referring to 8th has the non-volatile storage device 1000 a fuse arrangement 1100 at which a plurality of fuses or fuses 1110 are arranged, level shifter 1200_1 to 1200_m which generate a high voltage to resistance states of the plurality of fuses 1110 to change, and a sense amplifier 1300 on what information in the fuse arrangement 1100 are stored, scanned / amplified. The nonvolatile storage device 1000 also has a first register unit 1400 and a second register unit 1500 to store fuse data that is generated when information stored in the anti-fuse array 1100 are stored, read. Each of the first register unit 1400 and the second register unit 1500 may be implemented as a shift register having a plurality of registers.

The fuse arrangement 1100 has the plurality of fuses or fuses 1110 in which Information is stored. The fuse arrangement 1100 may include laser fuses whose connections are controlled by laser radiation or may have electrical fuses whose connections are controlled in accordance with an electrical signal. Otherwise, the fuse arrangement 1100 Anti-fuses whose states are changed from a high resistance state to a low resistance state according to an electrical signal, such as a high voltage signal. The fuse arrangement 1100 may include any type of fuses from the various types of fuses described above. In the following embodiment, it is assumed that the fuse arrangement 1100 an anti-fuse arrangement having anti-fuses. Also, information stored in the anti-fuses or data read out from the anti-fuses will be referred to as fuse data hereinafter.

The anti-fuse arrangement 1100 has an arrangement structure in which the plurality of fuses 1100 are arranged at intersections of a plurality of rows and a plurality of columns. For example, if the anti-fuse arrangement 1100 m rows and n columns, then the anti-fuse array 1100 m × n anti-fuses 1110 on. The anti-fuse arrangement 1110 has m word lines WL1 to WLm for accessing the anti-fuses 1110 which are arranged in the m rows and n bit lines BL1 to BLn which are arranged to correspond to the n columns so as to provide information selected from the plurality of anti-fuses 1110 to be read.

The anti-fuse arrangement 1100 stores various information related to operation of the nonvolatile memory device 1000 , For example, the anti-fuse arrangement 1100 a plurality of setting information for setting an operating environment of the nonvolatile memory device 1000 to save. The plurality of setting information is changed by changing the states of the plurality of anti-fuses 1100 by providing voltage signals WLP1 to WLPm which are from the level shifters 1200_1 to 1200_m for the anti-fuse arrangement 1100 are programmed. Information is in the majority of anti-fuses 1110 by programming the plurality of anti-fuses 1110 from the high resistance state to the low resistance state, in contrast to a general fuse circuit, for example a laser fuse circuit or an electrical fuse circuit. The majority of anti-fuses 1110 may have a structure in which a dielectric layer is disposed between two conductive layers, ie, a capacitor structure. The majority of anti-fuses 1110 is programmed by breaking the dielectric layer by applying a high voltage between the two conductive layers.

After the anti-fuse arrangement 1100 is programmed, a read operation on the anti-fuse arrangement 1100 performed together with starting the operation of the nonvolatile memory device 1000 , The read operation may be on the anti-fuse array 1100 simultaneously with the operation of the anti-fuse arrangement 1100 or a predetermined selected time after operating the nonvolatile memory device 1000 be performed. In the anti-fuse arrangement 1100 a word line selection signal is provided across the word lines WL1 to WLm and information contained in a selected anti-fuse 1110 are stored for the sense amplifier 1300 provided over the bit lines BL1 to BLn. According to characteristics of the arrangement structure, the information provided in the anti-fuse arrangement 1100 are randomly accessed by driving the word lines WL1 to WLm and the bit lines BL1 to B1n.

For example, since the word lines WL1 to WLm are sequentially driven, the plurality of anti-fuses are used 1110 from a first row to an mth row in the anti-fuse array 1100 sequentially accessed. The information which is sequentially accessed by the plurality of anti-fuses is used for the sense amplifier 1300 intended. The sense amplifier 1300 has one or more sense amplifier circuits. For example, if the anti-fuse arrangement 1100N Columns, the sense amplifier 1300n Sense amplifier circuits corresponding to the n columns. The n-sense amplifier circuits are connected to the n-bit lines BL1 to BLn, respectively. 1 Fig. 10 illustrates a case where two sense amplifier circuits are arranged to correspond to each of the n bit lines BL1 to BLn. For example, an odd-numbered sense amplifier circuit and an even-numbered sense amplifier circuit are arranged to correspond to a first bit line BL1. The odd numbered sense amplifier circuit samples / amplifies and outputs information stored in the anti-fuses 1110 which are connected to the odd-numbered word lines WL1, WL3, WL5, .... The even numbered sense amplifier circuit samples / amplifies and outputs information stored in the anti-fuses 1110 are stored, which are connected to the even-numbered word lines WL2, WL4, WL6, .... However, the inventive concept is not limited thereto and sense amplifier circuits can be used in be arranged in any of various forms. For example, only one sense amplifier circuit may be arranged to correspond to one bit line, or three or more sense amplifier circuits may be arranged to correspond to one bit line.

The sense amplifier 1300 scans / amplifies and outputs the information to which of the anti-fuse arrangement 1100 is accessed. The sampled / amplified information is fuse data OUT1 to OUTn actually used to provide an operating environment of the volatile memory device 1000 to set or adjust. As described above, since 1 Figure 11 illustrates a case in which two sense amplifier circuits are arranged to correspond to each bit line, actually having fuse data, for example, first fuse data OUT1, odd numbered fuse data, and even numbered fuse data.

The fuse data OUT1 to OUTn supplied by the sense amplifier 1300 are output for the first register unit 1400 intended. The first register unit 1400 may be implemented as a shift register in which a plurality of registers are connected in series to provide a signal sequentially. Likewise, the number of registers which are in the first register unit 1400 are less than that of the plurality of anti-fuses 1110 , which in the anti-fuse arrangement 1100 are included. Likewise, the number of registers stored in the first register unit 1400 are based on those of columns, which in the anti-fuse arrangement 1100 are determined. For example, if the anti-fuse arrangement 1100N Has columns, the first register unit 1400N Register. Otherwise, as described above, when two sense amplifier circuits are arranged to correspond to each bit line, the first register unit may be arranged 1400 Have 2 × n registers.

The first register unit 1400 receives the fuse data OUT1 to OUTn in units of the lines in the anti-fuse arrangement 1100 , For example, if one line out of the lines of the anti-fuse array 1100 is selected, fuse data OUT1 to OUTn, which in anti-fuses 1110 are stored, which are connected to a word line of the selected row, in parallel for the first register unit 1400 intended. The first register unit 1400 sees the fuse data OUT1 to OUTn for the second register unit 150 by shifting the provided fuse data OUT1 to OUTn in units of bits. The second register unit 1500 may be implemented as a shift register in which a plurality of registers are connected in series to provide a signal sequentially. The number of registers which in the second register unit 1500 may be equal to that of the plurality of anti-fuses 1110 , which in the anti-fuse arrangement 1100 are included. Fuse data OUT1 to OUTn, which in the second register unit 1500 may be stored as information for setting an operating environment of the nonvolatile memory device 1000 be used. For example, some of the fuse data OUT1 to OUTn, which may be in the second register unit 1500 are stored as information Info_FA for replacing a memory cell (not shown) stored in the nonvolatile memory device 1000 may be used by a redundant memory cell, and some of the fuse data OUT1 to OUTn may be used as trimming information Info_DC for adjusting a voltage present in the nonvolatile memory device 1000 is generated used.

To the fuse data OUT1 to OUTn from the anti-fuse arrangement 1100 to store registers that are connected to the sense amplifier 1300 for temporarily storing the fuse data OUT1 to OUTn, and registers adjacent to different circuit blocks of the nonvolatile memory device 1000 which use the fuse data OUT1 to OUTn, for example, a row and column decoder or a DC generator required to provide fuse data OUT1 to OUTn for the circuit blocks.

In accordance with exemplary embodiments of the inventive concept, the first register unit receives 1400 the fuse data OUT1 to OUTn from the sense amplifier 1300 and transmits the fuse data OUT1 to OUTn to the second register unit 1500 which is disposed adjacent to these circuit blocks. In particular, the anti-fuse arrangement has 1100 the arrangement structure, and the first register unit 1400 has the registers whose number is that of the columns which in the anti-fuse arrangement 1100 are included corresponds. Thus, the number of registers which are in the first register unit 1400 are less than that of the plurality of anti-fuses 1100 , which in the anti-fuse arrangement 1100 are included. For example, when a sense amplifier circuit is arranged to coincide with each bit line, the first register unit 1400N Sense amplifier circuits. Thus, the number of registers in the first register unit 1400 , which is related to the fuse data OUT1 to OUTn, can not be m × n, and hence can be n. In particular, even if a large number of anti-fuses 1110 in the anti-fuse arrangement 1100 is included, the number of registers, which in the first register unit 1400 be limited to n, according to the structure of the anti-fuse arrangement 1100 , As a result, it is possible to prevent the number of registers stored in the first register unit 1400 is increased proportionally.

9 illustrates a structure of a module 2200 in accordance with an embodiment of the inventive concept.

Referring to 9 assigns the module 2200 a memory having a memory device in accordance with an exemplary embodiment of the inventive concept. For example, the module has 2200 eight DRAMs. Each DRAM has an anti-fuse arrangement, which is a nonvolatile memory device. When an error address is stored in a DRAM 5, a memory controller may select the DRAM 5 by transferring data "0" to only the DRAM 5. The anti-fuse arrangement included in each of the DRAMs is used to store a generated error address in the DRAM. A command and an address are shared by the eight DRAMs.

The 10 and 11 FIG. 5 are timing diagrams illustrating timing in accordance with embodiments of the inventive concept when transmitting an error address.

Referring to 10 For example, a mode setting register command MRS, an active command ACT, a read command RD, and a write command WR are received via a command line CMD. A row error address F-RA and a column error address F-CA are received via an address line ADD. In the module 2200 of the 9 For example, the DRAM5 among the eight DRAMs may be selected by receiving only data "0" (logic low) via a data pin DQ. Since data received via data pins DQ0 to DQ7 logically all become "low", an error address is thus stored in the anti-fuse device, which is a non-volatile memory device included in the DRAM5. After the mode register setting command MRS, the activating command ACT and the write command WR are sequentially supplied and the row error address F-RA and the column error address F-CA are supplied, data "0" is transferred as the final chip selection data provided to the data pin DQ, and the error address is stored in the anti-fuse arrangement. This section is an error address transmission section. A section between when the programmed error address is read in accordance with the read command RD and when another mode register setting command MRS is received is a verification section. A verification process is completed when the other mode register setting command MRS is supplied after the read command is received.

The timing diagram of 11 is similar to the timing diagram of 10 except that a memory cell corresponding to an error address is repaired by receiving only a row error address F-FA via an address line ADD. Also, when a verification operation is performed to read the error address again, the verification process according to a pre-charge command is completed and a current mode is exited.

12 FIG. 11 is a timing diagram illustrating a timing when verification results are transmitted in parallel in accordance with an exemplary embodiment of the inventive concept. FIG.

Referring to 12 For example, when a mode register setting command MRS, an activating command ACT and a write command WR are supplied via a command line CMD, a row error address F-RA and a column error address F-CA are stored in an anti-fuse arrangement which is a non-volatile memory Storage device is. Then, states of the stored row error address F-RA and a column error address F-CA are checked by reading the row error address F-RA and a column error address F-CA to verify them, and resulting verification results become the test device 100 transmitted via data pins DQ0, DQ1 and DQ2. For example, the verification results which are logically low ("L") are transmitted in parallel via the data pins DQ0, DQ1 and DQ2. Values which are transferred to the other data pins DQ3, ... DQ7 are not recognized by a memory controller.

13 FIG. 13 is a table illustrating verification results to be transmitted in parallel according to an exemplary embodiment of the inventive concept.

Referring to 13 For example, states of the verification results may be checked by reading the verification results stored in an anti-fuse device, which is a nonvolatile memory. When verification results transmitted via data pins DQ0, DQ1 and DQ2 are all logically low (Case 1), this means that programming is normally completed and an error bit is replaced by row redundant cells. If the verification results transmitted via the data pins DQ0, DQ1 and DQ2 are logically low, low and high respectively (case 2), this means that the programming is finished normally and an error bit is replaced by column redundant cells , If the verification results transmitted via the data pins DQ0, DQ1 and DQ2 are logically low, high and low respectively (Case 3), this means that programming is normally completed and an error bit is replaced by a single redundant cell , If the verification results, which are transmitted via the data pins DQ0, DQ1 and DQ2, are logically low, high and high (case 4), this means that there is no special significance for future use. Cases 5 through 8 each indicate that programming is incomplete. When the verification results transmitted via the data pins DQ0, DQ1, and DQ2 are logically high, low, and low, respectively (case 5), it means that a rupture process is performed on a memory cell Problem has. If the verification results, which are transmitted via the data pins DQ0, DQ1 and DQ2, are logically high, low and high respectively (case 6), this means that the abort process is still in progress. In this case, verification may be temporarily delayed and then requested according to a read command RD. If the verification results transmitted via the data pins DQ0, DQ1 and DQ2 are logically high, high and low, respectively (case 7), this means that there is no available redundant cell. Accordingly, an error bit can not be repaired and should therefore be replaced by another memory cell. If the verification results transmitted via the data pins DQ0, DQ1 and DQ2 are all logic high (Case 8), this means that no current chip is selected. The verification results will be parallel to the test device 100 transmitted via the data pins DQ0, DQ1 and DQ2.

14 FIG. 11 is a timing diagram illustrating a timing when translating verification results in accordance with an exemplary embodiment of the inventive concept. FIG.

Referring to 14 will be the verification results, which in 13 are illustrated, in series. For example, a 3-bit verification result is transmitted in series via a data pin DQ0. The same 3-bit verification result can be sent to the test device 100 be transmitted via a data pin DQ7.

15 FIG. 13 is a table illustrating verification results to be transmitted in series in accordance with an exemplary embodiment of the inventive concept. FIG.

Referring to 15 Case 1 (LLL) designates that an error bit is replaced by row redundant cells. For example, a 3-bit verification result will be in series with the test device 100 transmitted via a data pin DQ. Case 6 (HLH) indicates that an abort process is still in progress in which a 3-bit verification result is in series with the test device 100 is transmitted via data pins DQ0, DQ1, DQ2 and DQ3.

The 16 and 17 13 are timing diagrams illustrating a method of operating a test device according to an exemplary embodiment of the inventive concept.

Referring to 16 For example, a test device performs error address detection and transmission as described below. First, an error address is detected using an ECC machine or BIST unit (operation S100). Then, the detected error address is stored in a fail address memory (FAM) (operation S105). Then, an error address transmission mode is entered in accordance with a test command given from a CPU (operation S110). The test command includes a test start command, a test end command, a command instructing to start the transmission of the error address, and a command instructing to terminate the transmission of the error address. Then, a mode register setting command, a chip selection signal and the error address are transmitted (operation S120).

Referring to 17 A memory device receives the mode register setting command, a write command, the chip select signal, and the error address (operation S130). Then, the error address is stored in a temporary error address memory (operation S140). Then, in a mode of programming a nonvolatile memory device is entered (operation S150). Then, a memory space of an anti-fuse device which is a nonvolatile memory device is checked (operation S160) (add ok). Then, the anti-fuse device, which is a nonvolatile memory device, is programmed (operation S170). Then, programmed data is read to verify the stored error address (operation S180). Then, a state of the stored data is checked, and a verification result is then transmitted to the outside (operation S190). Finally, one error bit is replaced by another memory cell (operation 200).

18 FIG. 12 is a conceptual diagram of a memory system in accordance with another exemplary embodiment of the inventive concept. FIG.

Referring to 18 the storage system has a test device 100 and a storage device 200 on. The test device 100 transmits an error address Addr, a control signal and data DQ. The storage device 200 has a BIST unit and an anti-fuse arrangement, which is a nonvolatile memory. The BIST unit tests the storage device 200 according to a test command issued by the test device 100 about the test device 100 is received, and stores the error address in the anti-fuse device, which is a nonvolatile memory device.

19 illustrates a circuit block of a memory device 300 in accordance with another exemplary embodiment of the inventive concept.

Referring to 19 has the storage device 300 a fuse arrangement 340 , which is a non-volatile memory constructed to store an error address as program data, a temporary fail address memory (FAM). 330 , a fuse arrangement information memory 350 , which is configured to store information about a fuse, a control unit 360 which is configured to the fuse arrangement 340 and the fuse arrangement information memory 350 to control a BIST unit 310 , which is configured to detect an error address, and a memory cell array 320 on. The BIST unit 310 receives a test command Control and test data DQ from a tester and detects an error address by writing the test data DQ to the memory cell array 320 and then reading the test data DQ from the memory cell array 320 , When an error bit occurs, an error flag and an error address corresponding to the error bit become the FAM 330 transfer. The FAM 330 may be implemented as a register having a plurality of error address arrays FAM 1, ... FAMn. The control unit 360 can be a space or space of the fuse arrangement 340 using the fuse arrangement information memory 350 to verify. The control unit 360 can also have a programming command and a programming address, which in the fuse arrangement 340 to control which is a non-volatile memory device. The test command is provided to the test device according to the control signal and the BIST unit 310 is activated accordingly. Likewise, the error address which is in the FAM 330 is stored according to the control signal to the fuse arrangement 340 transfer.

The 20 and 21 FIG. 10 is timing diagrams illustrating operation of a memory device in accordance with exemplary embodiments of the inventive concept.

Referring to 20 An activation command ACT and a read command RD are supplied via a command line CMD. Test data EDQ are supplied via a data pin DQ. The test data EDQ is written in a memory cell array and read data RDQ is generated by reading the test data EDQ stored in the memory cell array in accordance with the read command RD. When an error flag signal changes from a logic high to a logic low, an Nth row address is written to an error address memory FAM # 1. If the error flag occurs again, an (N + 1) th row address is written to an error address memory FAM # 2. Such an instruction and data are supplied in synchronization with a clock signal CLK, and a clock enable signal CKE and a chip select signal are also supplied in synchronization with the clock signal CLK.

Referring to 21 For example, an activation command ACT, a read command RD, and a pre-charge command Pre are supplied via a command line CMD. The timing diagram of 21 is essentially similar to that of 20 except that an N-th row address is transferred to an error address memory FAM # 1 when the pre-load instruction Pre is input, and an (N + 1) -th row address is transferred to an error address memory # 2, when the pre-load command Pre is supplied again. The FAM 330 of the 19 may be implemented as a register, an SRAM or the like.

22 FIG. 10 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the inventive concept.

Referring to 22 the storage device receives an enable command, a write command, and a read command from a test device (operation S300). Then, a BIST unit of the storage device is activated according to a command (operation S310). Then, an error address is detected, an error flag is generated, or a pre-load instruction is received (operation S320). Then the error address in an error address memory according to the error flag of the Load command saved (operation S330). Then, a fuse arrangement enters a programming mode for programming the error address (operation S340). Then, the capacity of a fuse memory is checked (operation S350). Then the fuse arrangement is programmed (operation S360). After that, an error bit is repaired (operation S370).

23 FIG. 11 is a diagram illustrating optical connections of a memory system in accordance with an exemplary embodiment of the inventive concept. FIG.

Referring to 23 the storage system has a controller 8100 and a storage device 8200 on. The controller 8100 has a control unit 8110 , a controller transmitter 8121 and a controller receiver 8122 on. The control unit 8110 has an ECC machine or a BIST unit. The controller transmitter 8121 has a device E / O which converts an electrical signal into an optical signal. The controller receiver 8122 has a device O / E which converts an optical signal into an electrical signal. The storage device 8200 has an anti-fuse arrangement 8221 which is a nonvolatile storage device, a BIST unit 8222 , a DRAM core 8223 , a transmitter 8312 and a receiver 8211 on. The transmitter 8312 has a device E / O which converts an electrical signal into an optical signal. The recipient 8211 has a device O / E which converts an optical signal into an electrical signal. The controller 8100 and the storage device 8200 are over an optical connection 0 8500 and an optical connection 1 8501 connected to transmit and receive data. In accordance with another exemplary embodiment of the inventive concept, data may be transmitted and received over an optical link. An I / O circuit 8120 of the controller 8100 and an I / O circuit 8210 the storage device 8200 are over the optical connection 0 8500 and the optical connection 1 8501 connected.

24 FIG. 12 shows through silicon via (TSV) stacked chips to which a memory system in accordance with an exemplary embodiment of the inventive concept is applied.

Referring to 24 is an interface chip or interface chip 3,100 arranged as a lowermost layer, and memory chips 3200 . 3300 . 3400 and 3500 are consecutive on the interface chip 3,100 arranged. The interface chip 3,100 may include an ECC machine or a BIST unit, a memory controller, and a CPU. The memory chips 3200 . 3300 . 3400 and 3500 have anti-fuse arrangements 3601 . 3602 . 3603 and 3604 , which are nonvolatile storage devices, and BIST units 3801 . 3802 . 3803 and 3804 on. An error address of a memory chip is determined using a tester (not shown) of the interface chip 3,100 detected and stored in an anti-fuse arrangement of the memory chip. These chips are about microbumps uBump and TSVs formed in them ( 3701 . 3702 . 3703 and 3704 ) connected. For example, the number of layered chips may be one or more.

25 illustrates various interfaces of a memory system in accordance with an exemplary embodiment of the inventive concept.

Referring to 25 (a) a memory system has a controller or a control unit 4000 and a storage device 5000 on. The controller 4000 has a control unit 4100 and an I / O input / output circuit 4200 on. The control unit 4100 may have an ECC machine or a BIST unit. The storage device 5000 has a DRAM core 5300 , an anti-fuse arrangement 5100 which is a nonvolatile storage device, a BIST unit 5400 and an I / O circuit 5200 on. The I / O circuit 4200 of the controller 4000 has an interface through which a command, a control signal, an address and a data strobe DQS to the memory device 5000 and data DQ are transferred to and from the storage device 5000 transmit and receive. An error address is transmitted via the interface.

Referring to 25 (b) has an I / O circuit 4200 a controller 4000 an interface via which a chip select signal CS and an address to a memory device 5000 are transmitted using a packet and data DQ are to and from the storage device 5000 transmit and receive. An error address is transmitted via the interface.

Referring to 25 (c) has an I / O circuit 4200 a controller 4000 an interface through which a chip select signal CS, an address and write data wData to a memory device 5000 using a packet and read data rData from the storage device 5000 be received. An error address is transmitted via the interface.

Referring to 25 (d) has an I / O circuit 4200 a controller 4000 an interface via which a command, an address and data DQ to and from a storage device 5000 are transmitted and received, and a chip select signal CS is supplied from the memory device 5000 receive. An error address is transmitted via the interface.

The 26 and 27 13 are diagrams illustrating system connections of a memory system in accordance with exemplary embodiments of the inventive concept.

Referring to 26 are a memory 7300 which is an anti-fuse arrangement 7301 , which is a nonvolatile memory, and a BIST unit 7302 has a CPU 7100 which is a BIST unit or ECC machine 7101 and a user interface 7200 via a system bus 7110 connected.

Referring to 27 are a storage system 6500 which is a store 6520 , which has an anti-fuse arrangement and a BIST unit, and a memory controller 6510 comprising a BIST or ECC machine; a CPU 6100 , a Random Access Memory (RAM) 6200 , a user interface or a user interface 6300 and a modem 6400 via a system bus 6110 connected.

A memory testing apparatus, method, and system in accordance with an exemplary embodiment of the inventive concept may detect an error address of a fault memory cell contained in a memory device, and repair the fault memory cell by repairing the fault memory cell. Even during operation of a chip or after a chip packaging is performed, a storage device can be tested and repaired using a test device. As a result, malfunctions of the memory device due to an error cell can be reduced, thereby improving the operational reliability of the memory device.

The foregoing is illustrative of embodiments and should not be considered as limiting thereto. Although some embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in embodiments without materially departing from the new teachings and advantages. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, device plus function formulations are provided to encompass the structures described herein as performing said function, and not just structural equivalents but also equivalent structures. Accordingly, it should be understood that the foregoing is illustrative of various embodiments and is not to be considered as limited to the particular embodiments disclosed, and that modifications of the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims (52)

A storage system comprising: a storage device ( 200 . 300 . 5000 . 8200 ) which a non-volatile memory device ( 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) having a matrix array structure of at least N × M, wherein N and M each denote an integer equal to or greater than 2; and a test device ( 100 ) configured to store the memory device ( 200 . 300 . 5000 . 8200 ), with an error address being passed through the test device ( 100 ) is detected, to the storage device ( 200 . 300 . 5000 . 8200 ) and in the non-volatile memory device ( 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) is stored. A memory system according to claim 1, wherein the test device ( 100 ) has a semiconductor chip. The memory system of claim 2, wherein the semiconductor chip comprises an error correction code (ECC) machine, and the nonvolatile memory device (12). 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) an anti-fuse arrangement ( 280 . 1100 . 3601 - 3604 . 5100 . 8221 ), which has a matrix array structure of at least N × M, where N and M each denote an integer equal to or greater than 2. The memory system of claim 2, wherein the semiconductor chip has a built-in self-test (BIST) unit, and the nonvolatile memory device (FIG. 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) an anti-fuse arrangement ( 280 . 1100 . 3601 - 3604 . 5100 . 8221 ), which has a matrix array structure of at least N × M, where N and M each denote an integer equal to or greater than 2. The storage system of claim 4, wherein the BIST unit is connected to the ECC machine. The memory system of claim 2, wherein the semiconductor chip comprises an error correction code (ECC) engine or a built-in self-test (BIST) unit and an error address memory ( 110 . 260 ) configured to the error address. A memory system according to claim 6, wherein the error address memory ( 110 . 260 ) by a control unit ( 130 . 270 . 360 . 4100 . 8110 ) is controlled. The memory system of claim 2, wherein the semiconductor chip comprises an error correction code (ECC) engine or a built-in self-test (BIST) unit, an error address memory ( 110 . 260 ), an address output unit ( 140 ), a control output unit ( 150 ), a data buffer ( 230 ) and a control unit ( 130 . 270 . 360 . 4100 . 8110 ) having. A memory system according to claim 8, wherein the control output unit controls the operation of the ECC engine or the BIST unit, the fault address memory ( 110 . 260 ), the data buffer ( 230 ) and the control unit ( 130 . 270 . 360 . 4100 . 8110 ) controls. The memory system of claim 2, wherein the semiconductor chip is contained in a memory controller and connected to a central processing unit (CPU). The memory system of claim 10, wherein the CPU issues a test instruction for the memory device (10). 200 . 300 . 5000 . 8200 ). The memory system of claim 11, wherein the test command comprises a test start command, a test end command, or an error address transfer command. A memory system according to claim 1, wherein the test device ( 100 ) is included in a test equipment. A memory system according to claim 13, wherein the test equipment comprises a pattern generator ( 1210 ), a test card ( 1220 ) and a socket ( 1230 ) having. A memory system according to claim 1, wherein said nonvolatile memory device ( 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) an anti-fuse arrangement ( 280 . 1100 . 3601 - 3604 . 5100 . 8221 ), which has a matrix array structure of at least N × M, where N and M each denote an integer equal to or greater than 2. The memory system of claim 15, further comprising a temporary error address memory ( 110 . 260 ) which is configured to store the error address. A memory system according to claim 16, wherein the error address in the anti-fuse arrangement ( 280 . 1100 . 3601 - 3604 . 5100 . 8221 ) under the control of the control unit ( 130 . 270 . 360 . 4100 . 8110 ) is stored. A memory system according to claim 17, wherein the control unit ( 130 . 270 . 360 . 4100 . 8110 ) in response to a mode enable signal received from a decoder unit ( 240 ) is activated. A memory system according to claim 17, wherein the control unit ( 130 . 270 . 360 . 4100 . 8110 ) the error address to or from the anti-fuse arrangement ( 280 . 1100 . 3601 - 3604 . 5100 . 8221 ) to write or read, and a verification result to the outside of the memory device ( 200 . 300 . 5000 . 8200 ), controls or verifies. A memory system according to claim 16, wherein the anti-fuse arrangement ( 280 . 1100 . 3601 - 3604 . 5100 . 8221 ) with a repair address memory ( 250 ) which is configured to store the error address, the repair address memory ( 250 ) with a comparison unit ( 251 ), which is configured to compare the error address with an external address, the comparison unit ( 251 ) with a multiplexer ( 252 ) configured to select one of the error address and the external address. A memory device, comprising: a temporary error address memory ( 260 ) for provisionally storing the error address; a non-volatile memory device ( 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) having a matrix arrangement structure of at least N × M to store the error address, wherein N and M each denote an integer equal to or greater than 2; and a control unit ( 130 . 270 . 360 . 4100 . 8110 ) which is configured to allow transmission of the error address stored in the temporary error address memory ( 260 ) is stored to the nonvolatile memory device ( 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) to control. A memory device according to claim 21, wherein said nonvolatile memory device ( 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) an anti-fuse arrangement ( 280 . 1100 . 3601 - 3604 . 5100 . 8221 ) having. A memory device according to claim 22, wherein in order to determine whether the error address is accurately written, the control unit ( 130 . 270 . 360 . 4100 . 8110 ) from the anti-fuse arrangement ( 280 . 1100 . 3601 - 3604 . 5100 . 8221 ) error address to be read and one to the outside of the memory device ( 200 . 300 . 5000 . 8200 ) controls or verifies the verification result to be transmitted. A memory device according to claim 22, wherein the control unit ( 130 . 270 . 360 . 4100 . 8110 ) the to be scanned or programmed anti-fuse arrangement ( 280 . 1100 . 3601 - 3604 . 5100 . 8221 ) controls or checks. A memory device according to claim 22, wherein said anti-fuse arrangement ( 280 . 1100 . 3601 - 3604 . 5100 . 8221 ) with a repair address memory ( 250 ) which is configured to store the error address, the repair address memory ( 250 ) with a comparison unit ( 251 ), which is configured to compare the error address with an external address, and wherein the comparison unit ( 251 ) with a multiplexer ( 252 ) configured to select one of the error address and the external address. A memory device according to claim 21, wherein said temporary error address memory ( 260 ) with an address buffer ( 210 ) configured to receive an external address. A memory device according to claim 21, wherein the control unit ( 130 . 270 . 360 . 4100 . 8110 ) according to a mode enable signal supplied by a decoding unit ( 240 ) is activated. A memory device according to claim 24, wherein the decoding unit ( 240 ) with the address buffer ( 210 ) and a control buffer ( 220 ) which is configured to receive a control signal. A test apparatus comprising: an error correction code (ECC) circuit configured to detect and correct an error bit; an error address memory ( 110 . 260 ) configured to store an error address of the error bit; and a control unit ( 130 . 270 . 360 . 4100 . 8110 ), which is configured to be in the error address memory ( 110 . 260 ) to check and control according to a test command to be transmitted to the outside error address. Test device according to claim 29, wherein the ECC circuit is equipped with a data buffer ( 230 ) configured to receive the error bit. The test device of claim 29, wherein the test command comprises a test start command, a test end command, or an error address transfer command. The test device of claim 29, wherein the ECC circuit comprises a built-in self test (BIST) unit. Test device according to claim 29, wherein the test device ( 100 ) is contained in a memory controller and connected to a central processing unit (CPU). Test device according to claim 29, wherein the test device ( 100 ) is included in a test equipment. The test device of claim 34, wherein the test equipment further comprises a pattern generator ( 1210 ), a test card ( 1220 ) and a socket ( 1230 ) having. Method for operating a test device ( 100 ) to transmit an error address, the method comprising: detecting the error address using an error correction code (ECC) circuit; storing the error address in an error address memory ( 110 . 260 ); entering an error address transfer mode according to a test command; transmitting a transmission signal having a mode register setting command; and transmitting the error address. The method of claim 36, wherein the error address is detected by an ECC machine or a built-in self-test (BIST) unit. The method of claim 36, wherein the transmission signal further comprises a write command and a chip select signal. The method of claim 36, wherein the test instruction comprises a command instructing to start transmission of the error address or a command instructing to terminate the transmission of the error address and given by a central processing unit (CPU). Method for operating a memory device to load an error address into the memory device ( 200 . 300 . 5000 . 8200 ), the method comprising: receiving the error address according to a mode register setting command; storing the error address in a temporary error address memory ( 110 . 260 ); and storing the error address in a nonvolatile memory device ( 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) having a matrix arrangement structure of at least N × M, where N and M each denote an integer equal to or greater than 2. The method of claim 40, further comprising checking a storage location of the non-volatile storage device (10). 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) before the error address in the nonvolatile memory device ( 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) is stored. The method of claim 40, further comprising reading the stored error address after the error address in the non-volatile memory device ( 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) is stored. The method of claim 42, further comprising transmitting a verification result indicating a state of the read error address in series or in parallel to the outside after the stored error address is read. Method for operating a test device ( 100 ) to return an error address to a memory device ( 200 . 300 . 5000 . 8200 ), the method comprising: detecting the error address by an error correction code (ECC) circuit; storing the error address in an error address memory ( 110 . 260 ); entering an error address transfer mode according to a test command; transmitting a transmission signal having a mode register setting command; transmitting the error address; receiving the error address in accordance with the mode register setting signal; storing the error address in a temporary error address memory ( 260 ); and storing the error address in a nonvolatile memory device ( 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) having a matrix array structure of at least N × M, wherein N and M each denote an integer equal to or greater than 2. The method of claim 44, further comprising verifying a storage location of the non-volatile storage device ( 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) before the error address in the nonvolatile memory device ( 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) is stored. A memory system comprising: a test device ( 100 ) configured to store test data for a storage device ( 200 . 300 . 5000 . 8200 ); wherein the storage device ( 200 . 300 . 5000 . 8200 ) Comprises: a built-in self-test (BIST) unit configured to store the memory device (BIST); 200 . 300 . 5000 . 8200 ) to test; and a nonvolatile memory device ( 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) which has a matrix array structure of at least N × M, where N and M each denote an integer equal to or greater than 2, and an error address obtained by testing the memory device (FIG. 200 . 300 . 5000 . 8200 ) is generated by the BIST unit in the nonvolatile memory device ( 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) is stored. A memory system according to claim 46, wherein said non-volatile memory device ( 340 . 1000 . 3601 - 3604 . 5100 . 7301 . 8221 ) an anti-fuse arrangement ( 280 . 1100 . 3601 - 3604 . 5100 . 8221 ), which has a matrix array structure of at least N × M, where N and M each denote an integer equal to or greater than 2. A memory system according to claim 46, wherein the memory device ( 200 . 300 . 5000 . 8200 ) further comprises at least two error address register arrangements configured to temporarily store the error address. The memory system of claim 48, wherein the BIST unit transmits the error address to the at least two error address storage registers in accordance with an error flag. The memory system of claim 49, wherein the error generation flag is replaceable by a pre-load instruction. A memory system according to claim 1, wherein the test device ( 100 ) is configured to communicate with the storage device ( 200 . 300 . 5000 . 8200 ) by silicon vias (TSVs) or microbumps. A memory system according to claim 1, wherein the test device ( 100 ) is configured to communicate with the storage device ( 200 . 300 . 5000 . 8200 ) to be connected by optical connections.

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