DE102013022377B3 - Device for operating passive infrared sensors - Google Patents

Abstract

Device for operating a passive infrared detector (PIR), characterized in that such PIR detectors are two-pole and can be symbolized in the equivalent circuit diagram by a current source that delivers a current (IPIR) depending on the change in irradiation and that has a capacity CPIR in parallel is switched, wherein - the passive infrared detector (PIR) is provided with two electrical connections and - the device comprises a differential amplifier stage which has a reference current source (Iref) and - has a resistor (RM1bis RMn) and - this resistance (RM1bis RMn) has a controllable tap which is connected to said reference current source (Iref) and - wherein one terminal of the resistor (RM1 to RMn) is connected to a first transistor (T1) and wherein the other terminal of the resistor (RM1 to RMn) is connected to a second transistor (T2) is connected and - the control electrode of the first transistor (T1) and the control electrode of the second transistor (T2) form the differential input and - each transistor (T1, T2) has its third connection with a working resistance (R1 , R2, C1, C2, IW1, IW2), which can be a differential working resistance, - a ΔΣ converter is provided for converting a differential analog input signal into a digital signal, - the outputs of this differential amplifier respectively is connected to an integrating filter and/or a capacitor in each case and- wherein the outputs of each integrating filter and/or each capacitor are connected to a comparator and- wherein the output of the comparator is connected to a digital integrating filter and/or an up/down counter are connected, which at least temporarily increments or decrements its counter reading at predetermined and / or programmed time intervals depending on the output of the comparator and - the output of this digital integrating filter and / or the up / down counter for controlling the controllable resistance (RM1 to RMn ) is used and - the output of this digital filter is used directly and / or after filtering by another digital filter as the output value of the ΔΣ converter.

Description

Various methods are known for measuring infrared radiation. An essential sensor principle is the use of passive infrared detectors (PIR detectors).

These are characterized by their simple and cost-effective production. Such PIR detectors are two-pole and can be symbolized in the equivalent circuit diagram by a current source that supplies a current I _PIR depending on the change in irradiation and thus the temperature and to which a capacitance C _PIR is connected in parallel. (See also 1 .)

• Zum einen kommt es zu einer Verschiebung des Arbeitspunkts des PIR-Detektors durch eine Selbstaufladung. Zum anderen liefert die Stromquelle I_PIR in der Regel nur einen sehr geringen Strom bei einem relativ hohen Innenwiderstand. Dieser Innenwiderstand R_PIR ist in 1 eingezeichnet. Diese Randbedingungen resultieren in der Forderung nach einem großen Dynamikbereich und einem sehr hohen Innenwiderstand für die nachfolgende Verstärker- und Analog-zu-Digital-Wandler-Schaltung (Auswerteschaltung).

When evaluating the signal from a PIR sensor, various problems arise:

• On the one hand, the operating point of the PIR detector shifts due to self-charging. On the other hand, the current source I _PIR usually only delivers a very low current with a relatively high internal resistance. This internal resistance R _PIR is in 1 drawn. These boundary conditions result in the requirement for a large dynamic range and a very high internal resistance for the subsequent amplifier and analog-to-digital converter circuit (evaluation circuit).

However, due to the high internal resistance of an optimal evaluation circuit, once generated, charges can no longer flow away. This can result in the circuit leaving the operating range of the evaluation circuit because it is overdriven.

From the US 4,377,808 A an improved infrared intrusion detection system with two sensors is known. The device of US 4,377,808 A includes a motion discriminator that allows the system to respond only to radiating objects moving through the system's surveillance area. Depending on the relative amount of the sensors on the device US 4,377,808 A According to the technical teachings of the incident radiation US 4,377,808 A generates a positive or negative sensor signal. A switching amplifier discharges in the device US 4,377,808 A depending on the polarity of the sensor signal, selectively selects one of two capacitors. According to technical theory, the voltages on the capacitors are: US 4,377,808 A coupled to the inputs of a voltage comparator. According to technical theory, the time constants for recharging the capacitors are: US 4,377,808 A selected so that an alarm is only displayed if the length of the time interval between the occurrence of a sensor signal of a certain polarity and the subsequent occurrence of a sensor signal of the opposite polarity is within prescribed limits. The solution of the US 4,377,808 A However, in terms of discharge, it is inferior to the system presented here because it has lower input resistances and therefore places a greater load on the pyroelectric element.

Task of the invention

It is the object of the invention to provide an evaluation method and a high-resistance measuring circuit with a large dynamic range for evaluating the signal of a PIR detector, without overloading occurring due to the charging of the inputs of the PIR detector evaluation circuit. The power consumption should be minimized.

This task is solved by a device according to claim 1.

Description of the invention

The system according to the invention is in 1 shown. The passive infrared detector (PIR) is connected to a discharge network R _G with its two connecting lines. This in turn is connected to an analog-to-digital converter (ADC). The output of the analog-to-digital converter is connected via a first bus (T) with a first bus bandwidth to a digital filter (DF), whose output Out typically has a larger second bus bandwidth than the first bus bandwidth.

When developing the method according to the invention for operating a passive infrared detector (PIR), it was recognized that the charging of the inputs represents a significant obstacle to correct operation of the system. As will be explained further later, the ΔΣ converter (ADC) according to the invention is sensitive to such operating point drift. However, this increased sensitivity of the ΔΣ converter (ADC) according to the invention enables particularly efficient suppression of the quantization errors by the comparator of the ΔΣ converter (ADC) according to the invention. Therefore, the ΔΣ converter according to the invention and the discharge of the passive infrared detector by means of the discharge network (R _G ) according to the invention form an inventive unit. Based on this said inventive finding of incorrect charging of the inputs, the simplest solution to this problem can be achieved by discharging the input nodes using a switch when the voltage at the detector reaches the dynamic range. In this case, no evaluation of the voltage can be made during the discharge and shortly afterwards detector. Alternatively, the discharge can take place through a leakage resistor between the connections of the sensor or from the connections to reference ground (R _{dis_1} , R _{dis_2} ). A major disadvantage of this solution is the continuous attenuation of the signal and the detector's own noise. In addition, a giga-ohm resistor cannot be implemented in a low-cost CMOS technology with reasonable effort. During development, it was recognized that discharging the second output via the internal resistance of the power source of the PIR sensor (PIR) does not lead to satisfactory results. It has been shown that the resistance value of these leakage resistors should be greater than 1 MOhm and/or preferably greater than 10 MOhm and/or preferably greater than 100 MOhm and/or preferably greater than 1 GOhm and/or preferably greater than 10 GOhm. The optimal leakage value depends on the respective PIR detector and the respective application and should be adjusted on a case-by-case basis. In the case of large charge shifts due to rapid temperature changes (temperature shock), disproportionately low leakage resistance values would be necessary, which would almost eliminate the signal to be detected.

It is clear here that the leakage resistances of the discharge network (R _G ) should preferably be designed to be equal and as symmetrical as possible, or “matching” in technical terms. These leakage resistors can also be more complex circuits that only perform the function of a leakage resistor, among other things. As part of the development of the invention, it was recognized as advantageous to at least partially design the leakage resistors as a switched capacitor circuit. With such circuits, any relatively high-resistance leakage resistors that may be required can be implemented relatively easily. For the operation of such a switched capacitor network, it is particularly advantageous if these networks are operated with a non-overlapping two-phase clock. Of course, single-phase and multi-phase clocks can also be used, but they are usually more complex to implement.

The requirement for a reliable discharge of the PIR detector is in contrast to the highest possible input resistance of the evaluation circuit. In the context of the invention, it was therefore recognized that it makes sense to make the average equivalent resistance of at least the discharge resistors of the passive infrared detector dependent on whether a measurement of the infrared radiation potential is being carried out using the passive infrared sensor (PIR detector) or not. Before a measurement, the discharge resistors are switched to a very high-resistance state (measuring state). After the end of the measurement, the discharge resistors are switched to a state that has a lower resistance compared to the measuring state.

Alternatively, the state of charge (voltage at the detector) can be measured and the size of the discharge resistors can be readjusted depending on the state of charge.

It is conceivable that other operating conditions also require switching. For example, it is conceivable to discharge the PIR detector in a defined manner using a switch. In such a mode, switching the discharge resistors to high resistance would also make sense. In extreme cases, the measurement condition can mean a complete disconnection of a discharge resistor.

The resistance values are always based on average values over several cycles of the operating cycle of the respective switched capacitor network, provided that this is used to implement the discharge resistors. It is therefore an essential inventive idea that the discharge resistances of the PIR detector assume different values depending on the states of the sensor system, whereby at least the states of measurement and no measurement/discharge should be implemented.

The ΔΣ converter (ADC) according to the invention consists, among other things, of a differential amplifier, the current source of which is not, as is usual with normal differential amplifiers, divided symmetrically into two branches with symmetrical control of the transistors of the differential amplifier, but instead of the common contact point for the Transistors in the branches of the differential amplifier and the operating current source have a current divider which divides the current differently depending on an external control value. It can be assumed that the operating current source has a finite internal resistance. In this respect, the use of a real voltage source is also possible. This current divider is implemented in the device according to the invention by a resistor chain which is connected at one end to a transistor of the differential amplifier and at the other end to the other transistor of the differential amplifier. A multiplexer now connects the operating current source to a node of this resistor chain depending on the external control value. The current divider therefore behaves like a digitally controlled potentiometer, the tap of which is adjusted by the external parameter. This sets a different current feedback for the different branches of the differential amplifier. The power distribution takes place in such a way that the gate-source voltages of the transistors are adjusted by the voltage drop across the resistors of the current divider so that the sum of the current through the two branches corresponds to the current of the operating current source. The other connections of the transistors are each connected to a working resistor. It has proven to be particularly advantageous if these working resistances are designed as real current sources, since the differential working resistance and thus the differential amplification are then particularly large.

Capacitances that integrate the output signal can be connected in parallel to these working resistances. The use of Miller capacities is also conceivable. In the case of the ΔΣ converter according to the invention, these capacitances carry out the summing Σ function of the ΔΣ converter and thus eliminate the quantization error by a downstream comparator.

The following method is recommended for operating a passive infrared detector: Each of the outputs of said passive infrared detector is connected to the control input of an assigned input transistor of the differential amplifier described. One contact of each of these input transistors is connected to an associated current divider output of a controllable current divider. Said current divider distributes the current from a reference current source (I _ref ) to the current divider outputs depending on a control input. The other contacts of the transistors are each connected to a working resistor, preferably an integrating filter or a capacitance (C ₁ , C ₂ ). The output values of these integrating filters, work resistances and capacitances are now compared with one another by at least one comparator. This creates an unavoidable quantization error that is minimized by the feedback described below. The comparator output signal of this comparator is connected to a digital integrating filter, which carries out a second integration in addition to the said capacitances. The control input of said current divider, which divides the current of an operating power source, is connected to the output of the digital integrating filter. If the current divider is controlled analogue, a digital-to-analog converter (DAC) and/or a signal format converter is required which converts the output signal of the digital integrating filter into a suitable format. However, in the example described here, this is not necessary because the multiplexer can be controlled digitally.

Something similar may be necessary when adapting a digital control input for the current divider to the digital output of the digital integrating filter.

In addition to this two-phase version, a single-phase version of an evaluation circuit can also be used. An output of the passive infrared detector controls at least a second power source. This second power source feeds power into a first account (S _b ). This first node (S _b ) is connected via an integrating filter to the input of a comparator which compares the signal level of this first node (S _b ) with an internal level. The output of this comparator is again directly or indirectly connected to the said digital integrating filter and thus controls it. The output of this digital integrating filter now controls a digital-to-analog converter (DAC). The output of this digital-to-analog converter now controls a first current source (I ₁ ), which in turn also feeds its current into the first node (S _b ). In contrast to the previous version, in this version one connection of the passive infrared detector is connected to ground, while the other connection is connected to the evaluation circuit described above. Such a circuit is also suitable for evaluating thermopiles.

For both methods, it is advantageous if the digital integrating filter is implemented as an up/down counter that counts in measurement phases in a predetermined or programmable cycle. The counting direction is preferably determined by the output of the comparator. The step size of this counting and the time intervals at which a counting takes place can also be constant and predetermined or programmable. In some applications it has proven useful to make the counting increment dependent on the counter reading itself in order to avoid overflow or underflow and thus total inoperability. If the counter reading exceeds a critical upper value, this can be detected, for example, and cause the measurement state to be exited and the detector element to be activated in the discharge state. This is particularly useful for the one-handed version, as it is able to measure the absolute level of an input signal. The output of the digital integrating filter represents the measured value.

In any case, it is still advisable to add another digital filter (DF) to the digital integrating filter before the measured value is used. This suppresses the quantization errors above a cutoff frequency.

It can be shown that the quantization error becomes zero at a frequency of 0Hz in the interference spectrum and approaches a finite value for infinitely high frequencies. The cutoff frequencies depend essentially on the load capacities (C ₁ , C ₂ ) and the resistance (R _M ) of the current divider and can therefore be easily adjusted.

Of course, it makes sense to allow essential parts of this process to run in a signal processor. Only the input stages should then be created using specially designed electronics. Such a device is then able to carry out the method described above.

• 1 zeigt die grundsätzlichen Blöcke einer erfindungsgemäßen Vorrichtung eines passiven Infrarot-Detektors. Die Vorrichtung besteht aus einem passiven Infrarot-Detektor (PIR), das mit dem Entladenetzwerk R_G gekoppelt ist. Die Aufgabe dieses Entladenetzwerks ist es, Aufladungen des PIR-Detektors zu beseitigen und den PIR-Detektor in einem für den nachfolgenden Analog-zu-Digital-Wandler günstigen Arbeitspunkt zu halten ohne die Dynamik des Systems zu belasten. Der Analog-zu-Digital-Wandler wandelt das Signal des Entladenetzwerks in ein erstes digitales Signal auf einem Bus T mit einer ersten Busbreite (Anzahl Bits) um. Ein nachfolgendes digitales Filter (DF) filtert das Signal auf dem ersten Bus T und gibt über einen Ausgangsbus (Out) die Daten mit einer größeren Auflösung aus. Daher besitzt der Ausgangsbus Out typischerweise eine größere Busbreite als der erste Bus T.
• 2 zeigt das nicht beanspruchte Ersatzschaltbild eines passiven Infrarot-Detektors (PIR) mit Ersatzstromquelle (I_PIR) und einer Serienschaltung von parasitärem Detektorkapazität (C_PIR) und zugehörigem Verlustwiderstand R_{PIR_C} sowie den Innenwiderstand der Ersatzstromquelle (R_PIR). Dieser Innenwiderstand der Stromquelle (R_PIR) liegt parallel zur Stromquelle (I_P,R) und ist typischerweise sehr hoch. Eine zu große Belastung des Detektors lässt daher die Ausgangsspannung zusammenbrechen.
• 3 zeigt eine einhändige Version des Analog-zu-Digital-Wandlers (ADC) aus 1. Eine erste gesteuerte Stromquelle (I₁) (auch als weitere Stromquelle bezeichnet) wird durch den Rückkoppelpfad gesteuert und speist in den ersten Knoten (Sb) ein. Eine zweite gesteuerte Stromquelle (I₂) (auch als Stromquelle bezeichnet) wird durch einen Ausgang des passiven Infrarot-Detektors gesteuert und speist ebenfalls in den ersten Knoten (S_b) ein. Die Summe der beiden Stromquellenströme lädt eine Kapazität (C_1b) auf oder entläd diese. Ist der Regelkreis stabil, so liefert die zweite Stromquelle (I₂) einen im Vorzeichen unterschiedlichen, jedoch betragsgleichen Strom, wie die erste Stromquelle (I₁). Der Komparator (CP_b) ist mit seinem Eingang mit diesem Kondensator (C_1b) verbunden und vergleicht den Spanungswert an diesem Kondensator und damit am ersten Knoten (S_b) mit einem internen Vergleichswert. Der Auf-/Abzähler (Int_b) zählt nun in diesem Beispiel mit jedem Systemtakt entweder um eins aufwärts oder um ein abwärts je nachdem, ob der Eingang des Komparators (CP_b) über oder unter der Schaltschwelle des Komparators (CP_b) liegt. 6 Bit des Zählerstandes des Auf- / Abzählers (Int_b) werden beispielsweise für die Rückkopplung verwendet. In diesem Beispiel werden diese 6 Bit durch einen Digital-zu-Analog-Wandler (DAC) in ein analoges Signal gewandelt, dass die weitere Stromquelle (I₁) steuert. Ein digitales Filter (DF) filtert den Zählerstand des Auf-Ab-Zählers (Int_b) zum Ausgangssignal (Out), welches der Ausgangsbus des digitalen Filters DF ist.
• 4 zeigt ebenfalls eine einhändige Version des Analog-zu-Digital-Wandlers (ADC) aus 1. Allerdings ist anstelle der steuerbaren Stromquelle die eine Quelle des einen Bezugssignals nun so realisiert, dass der Zählerstand (Val) des Auf-/Abzählers (Int_b) nun den Abgriff (IN_FB) an einer Widerstandskaskade (R_FB) aus einzelnen Widerständen (nicht gezeichnet) steuert. Dieser Abgriff kann dann einem Differenz-Transconduktanz-Verstärker zugeführt werden, der den Stromausgang (CS) besitzt. Die Stromausgänge laden und entladen jeweils einen Kondensator (C_1c, C_2c). Die dabei auftretenden Spannungen an den Kondensatoren (C_1c, C_2c) werden durch einen Komparator (CP) miteinander verglichen, der wiederum den Auf-/Abzähler (Int_b) steuert.
• 5 zeigt einen steuerbaren Stromteiler als Teil einer erfindungsgemäßen Differenzstufe bestehend aus der Widerstandskette von n Widerständen R_M1 bis R_Mn, die typischerweise aber nicht notwendigerweise identisch ausgeführt werden. Von den in diesem Beispiel n+1 Abgriffen der Widerstandskette wird durch einen analogen Multiplexer (MUX) einer mit der Betriebsstromquelle (I_ref) verbunden. Die Busbreite des Steuerbusse (Val) des analogen Multiplexers (Mux) muss dabei ausreichend gewählt werden und dürfte typischerweise größer als der Logarithmus der von n zur Basis 2 sein. Der Stromteiler, die Stromquelle und die Transistoren (T₁, T₂) bilden eine erfindungsgemäße Differenzstufe.

• 6 Zeigt die Differenzstufe aus 5 mit zwei Arbeitswiderständen (R_L1, R_L2). Es ist offensichtlich, dass die Stromteilerwiderstände (R_M1 bis R_Mn) zu einer unterschiedlichen Stromgegenkopplung für die beiden Zweige des Differenzverstärkers führen. Diese unterschiedliche Stromgegenkopplung wird durch das Steuersignal (Val) eingestellt. In diesem Beispiel sind zwei beispielhafte Ausgänge (ON, OP) einzezeichnet.
• 7 zeigt die Differenzstufe aus 6 als Teil einer Konstruktion entsprechend 3. An Stelle der Arbeitswiderstände (R_L1, R_L2) aus 6 sind je ein Kondensator (C₁, C₂) parallelgeschaltet mit einem Arbeitswiderstand (R₁, R₂) eingesetzt. An den Anschlüssen IN und IP wird der passive Infrarotsensor (PIR) entsprechend der 1 und 2 angeschlossen.
• 8 entspricht 7 mit dem Unterschied, dass die Widerstände (R₁, R₂) durch reale Stromquellen (I_W1, I_W2) ersetzt sind. Dies hat den Vorteil, dass diese einen erhöhten differentiellen Widerstand aufweisen. Bei der Realisierung als integrierte Halbleiterschaltung stellt diese Konstruktion eine gegen parametrische Schwankungen robuste Lösung dar. Die Konstruktion ist sehr einfach und verbraucht aus diesem Grund nur sehr wenig Strom. Dabei weist sie gleichzeitig einen sehr hohen Eingangswiderstand auf. Da die Source-Anschlüsse durch die Gegenkopplung über den Stromteiler den jeweiligen Gate-Spannungen (im Mittel) folgen, schwanken die Gate-Source-Spannungen nicht. Daher sind die komplexen Eingangsimpedanzen sehr hoch. Die Gate-Source-Kapazitäten müssen nicht wesentlich umgeladen werden. Das Quantisierungsrauschen des Analog-zu-Digital-Wandlers wird mit steigender Anzahl n der Widerstände R_Mi geringer. Die zuvor genannten Punkte stellen wesentliche Vorteile der Erfindung gegenüber dem Stand der Technik dar.
• 9 zeigt eine mögliche Realisierung der Entladeschaltung R_G aus 1 bzw. der Entladewiderstände (R_{dis_1}, R_{dis_2}) in 1. Diese Widerstände müssen einen relativ hohen Widerstandswert aufweisen und sollten typischerweise möglichst gleich sein. Die in dieser 8 gezeigte Switch-Capacitor-Realisierung arbeitet mit Transfergattern, die wechselweise mit einem von zwei nicht überlappenden Takten (ϕ₁, ϕ₂) geschaltet werden. Abgesehen von der Nichtüberlappung ist der eine Takt der inverse des anderen Taktes. Die Speicherkapazitäten befördern dabei jeweils eine gewisse Ladungsmenge mit jedem Halbtakt um einen Knoten weiter. Die Figur zeigt zwei Stränge. Die Stränge werden um jeweils einen Halbtakt versetzt betrieben. Hierdurch kommt es zu einem kontinuierlichen Ladungsabfluss. Werden die Takte abgeschaltet, was insbesondere in den Messphasen vorzugsweise der Fall ist, so fließt kein Strom mehr. Der so gebildete Arbeitswiderstand wird hochohmig. Wird der Takt der Entladung als von der Eingangsspannung abhängig gewählt, so kann die Entladung beispielsweise so gesteuert werden, dass sie bei größeren Eingangsspannungsdifferenzen größer und bei kleineren Eingangsspannungsdifferenzen kleiner ist und in einem vorgebbaren Bereich verschwindet.
• 10 zeigt ein weiteres Beispiel eines Entladenetzwerks R_G als aktives Netzwerk. Die Transistoren T₃ und T₄ werden in Abhängigkeit von der Differenz der Eingangsspannung zwischen IP und IN leitend geschaltet. Der Differenzverstärker bildet dabei den Betrag der Differenz an seinen Eingängen OP und ON und öffnet die Transistoren T₃ und T₄ entsprechend einer vorgegebenen Funktion in Abhängigkeit von diesem Differenzbetrag. Da die Kennlinie der Transistoren nicht linear ist, führt dies bei einem verschwindenden Differenzbetrag der Eingangsspannung zwischen IP und IN zu einem verschwindenden Leitwert der Transistoren T₃ und T₄.
• 11 zeigt eine weitere mögliche Implementierung eines Entladenetzwerkes R_G. Eine erste Stromquelle speist mit dem Strom I jeweils zur Hälfte die MOS-Dioden T9 und T14. Der Strom durch die MOS-Diode T14 wird durch T13 vermindert. Der Strom durch die MOS-Diode T9 wird durch T11 vermindert. Eine zweite Stromquelle liefert einen Strom, der typischerweise 80% des Wertes des Stroms der ersten Stromquelle beträgt. Da der Transistor T11 mit der MOS-Diode T12 einen Stromspiegel bildet und der Transistor T13 mit der gleichen MOS-Diode T12 einen Stromspiegel bildet, wird ein auf typischerweise 80% des Stromes I bezogener Offsetstrom von den Strömen durch T9 bzw. durch T14 angezogen. Sind die Eingänge IP und IN ungleich vorgespannt, so führt dies zu einer unausgeglichenen Stromaufteilung durch die Differenzstufe aus T5 und T6. Dies äußert sich dann so, dass zusätzlicher Strom durch die MOS Dioden T9 oder T14 fließen kann, was zu einer Öffnung der Transistoren T7 und T15 oder T8 und T16 führt und somit zu einer Entladung der Eingangsknoten IP und IN.
• 12 zeigt eine beispielhafte Entladewiderstandskennlinie einer Schaltung gemäß 11. Durch die geeignete Wahl der Stromspiegel- und Transistorverhältnisse kann erreicht werden, dass die Kennlinie des Eingangswiderstands einen extrem hochohmigen Bereich A aufweist, in dem der Eingangswiderstand praktisch nur vom Leckstrom der Schaltung bestimmt wird und einen Bereich B in dem eine Spannungsbegrenzung einsetzt und einen Bereich C, in dem der Eingangswiderstand sehr niederohmig ist.

The invention is explained below with reference to the accompanying figures:

• 1 shows the basic blocks of a passive infrared detector device according to the invention. The device consists of a passive infrared detector (PIR) coupled to the discharge network R _G. The task of this discharge network is to eliminate charging of the PIR detector and to keep the PIR detector at an operating point that is favorable for the subsequent analog-to-digital converter without putting a strain on the dynamics of the system. The analog-to-digital converter converts the signal of the discharge network into a first digital signal on a bus T with a first bus width (number of bits). A subsequent digital filter (DF) filters the signal on the first bus T and outputs the data with a higher resolution via an output bus (Out). Therefore, the output bus Out typically has a larger bus width than the first bus T.
• 2 shows the unused equivalent circuit diagram of a passive infrared detector (PIR) with a backup power source (I _PIR ) and a series connection of parasitic detector capacitance (C _PIR ) and associated loss resistance R _{PIR_C} as well as the internal resistance of the backup power source (R _PIR ). This internal resistance of the current source (R _PIR ) is parallel to the current source ( _IP,R ) and is typically very high. If the detector is subjected to too great a load, the output voltage will collapse.
• 3 shows a one-handed version of the analog-to-digital converter (ADC). 1 . A first controlled current source (I ₁ ) (also referred to as a further current source) is controlled by the feedback path and feeds into the first node (Sb). A second controlled current source (I ₂ ) (also referred to as a current source) is controlled by an output of the passive infrared detector and also feeds into the first node (S _b ). The sum of the two power source currents charges or discharges a capacitance (C _1b ). If the control loop is stable, the second current source (I ₂ ) supplies a current that is different in sign but has the same magnitude as the first current source (I ₁ ). The comparator (CP _b ) has its input connected to this capacitor (C _1b ) and compares the voltage value at this capacitor and thus at the first node (S _b ) with an internal comparison value. In this example, the up/down counter (Int _b ) now counts either up by one or down by one with each system cycle, depending on whether the input of the comparator (CP _b ) is above or below the switching threshold of the comparator (CP _b ). For example, 6 bits of the count of the up/down counter (Int _b ) are used for feedback. In this example, these 6 bits are converted by a digital-to-analog converter (DAC) into an analog signal that controls the additional current source (I ₁ ). A digital filter (DF) filters the count of the up-down counter (Int _b ) to the output signal (Out), which is the output bus of the digital filter DF.
• 4 also shows a one-handed version of the analog-to-digital converter (ADC). 1 . However, instead of the controllable current source, the one source of the one reference signal is now implemented in such a way that the counter reading (Val) of the up/down counter (Int _b ) now has the tap (IN _FB ) on a resistor cascade (R _FB ) made up of individual resistors (not drawn) controls. This tap can then be fed to a differential transconductance amplifier which has the current output (CS). The current outputs each charge and discharge a capacitor (C _1c , C _2c ). The resulting voltages on the capacitors (C _1c , C _2c ) are compared with each other by a comparator (CP), which in turn controls the up/down counter (Int _b ).
• 5 shows a controllable current divider as part of a differential stage according to the invention consisting of the resistance chain of n resistors R _M1 to R _Mn , which are typically but not necessarily identical. In this example, one of the n+1 taps of the resistor chain is connected to the operating current source (I _ref ) through an analog multiplexer (MUX). The bus width of the control bus (Val) of the analog multiplexer (Mux) must be chosen sufficiently and should typically be larger than the logarithm of n to base 2. The current divider, the current source and the transistors (T ₁ , T ₂ ) form a differential stage according to the invention.

• 6 Shows the difference level 5 with two working resistors (R _L1 , R _L2 ). It is obvious that the current divider resistors (R _M1 to R _Mn ) result in different current feedback for the two branches of the differential amplifier. This different current feedback is set by the control signal (Val). In this example, two exemplary outputs (ON, OP) are shown.
• 7 shows the difference level 6 as part of a construction accordingly 3 . Instead of the working resistors (R _L1 , R _L2 ). 6 A capacitor (C ₁ , C ₂ ) connected in parallel with a working resistor (R ₁ , R ₂ ) is used. The passive infrared sensor (PIR) is connected to the IN and IP connections 1 and 2 connected.
• 8th corresponds 7 with the difference that the resistors (R ₁ , R ₂ ) are replaced by real current sources (I _W1, I _W2 ). This has the advantage that they have an increased differential resistance. When implemented as an integrated semiconductor circuit, this construction represents a solution that is robust against parametric fluctuations. The construction is very simple and for this reason only consumes very little power. At the same time, it has a very high input resistance. Since the source connections follow the respective gate voltages (on average) due to the negative feedback via the current divider, the gate-source voltages do not fluctuate. Therefore the complex input impedances are very high. The gate-source capacitances do not need to be significantly reloaded. The quantization noise of the analog-to-digital converter decreases as the number n of resistors R _Mi increases. The aforementioned points represent significant advantages of the invention over the prior art.
• 9 shows a possible implementation of the discharge circuit R _G 1 or the discharge resistors (R _{dis_1} , R _{dis_2} ) in 1 . These resistors must have a relatively high resistance value and should typically be as equal as possible. The ones in this 8th The switch capacitor implementation shown works with transfer gates that are switched alternately with one of two non-overlapping clocks (ϕ ₁ , ϕ ₂ ). Apart from the non-overlapping, one bar is the inverse of the other bar. The storage capacities transport a certain amount of charge by one node with every half cycle. The figure shows two strands. The strands are each operated offset by half a cycle. This results in a continuous flow of charge. If the clocks are switched off, which is particularly the case in the measuring phases, no more current flows. The working resistance formed in this way becomes high-resistance. If the cycle of the discharge is chosen to be dependent on the input voltage, the discharge can, for example, be controlled in such a way that it is larger for larger input voltage differences and smaller for smaller input voltage differences and disappears in a predeterminable range.
• 10 shows another example of a discharge network R _G as an active network. The transistors T ₃ and T ₄ are switched on depending on the difference in the input voltage between IP and IN. The differential amplifier forms the amount of the difference at its inputs OP and ON and opens the transistors T ₃ and T ₄ according to a predetermined function depending on this difference amount. Since the characteristic curve of the transistors is not linear, this leads to a vanishing conductance of the transistors T ₃ and T ₄ when the difference in the input voltage between IP and IN disappears.
• 11 shows another possible implementation of a discharge network R _G. A first current source supplies half of the current I to each of the MOS diodes T9 and T14. The current through the MOS diode T14 is reduced by T13. The current through the MOS diode T9 is reduced by T11. A second power source supplies a current that is typically 80% of the value of the current of the first power source. Since the transistor T11 forms a current mirror with the MOS diode T12 and the transistor T13 forms a current mirror with the same MOS diode T12, an offset current related to typically 80% of the current I is attracted to the currents through T9 or through T14. If the inputs IP and IN are biased unequally, this leads to an unbalanced current distribution by the differential stage made up of T5 and T6. This then manifests itself in the way that additional current can flow through the MOS diodes T9 or T14, which leads to an opening of the transistors T7 and T15 or T8 and T16 and thus to a discharge of the input nodes IP and IN.
• 12 shows an exemplary discharge resistance characteristic of a circuit according to 11 . Through the appropriate choice of the current mirror and transistor ratios, it can be achieved that the characteristic curve of the input resistance has an extremely high-resistance range A, in which the input resistance is practically is only determined by the leakage current of the circuit and an area B in which a voltage limitation sets in and an area C in which the input resistance is very low.

The two connections are thus discharged by this electrical circuit arrangement, the equivalent resistance of which is significantly greater at an operating point in area A than at an operating point in areas B or C.

This makes it possible to operate a passive infrared detector so that the electrical connections are discharged through a current path when the voltage is outside a predetermined range A. The discharge current through this circuit depends on the input voltage between the electrical connections IP and IN. In the range A of the input voltage specified by the dimensions, the discharge current disappears except for the leakage current of the transistors. The discharge current increases as the input voltage increases outside of this range A. The input resistance RIN(IP-IN) depends on the differential voltage V(IP-IN) between the inputs IP and IN of the network R _G. The input resistance considered here can be assumed to be located between the connections IP and IN as well as between a connection IP or IN on the one hand and the reference potential, for example ground, on the other side. The behavior in 12 should preferably be similar in each of these two consideration cases.

Reference symbol list

A

Voltage range in which the discharge network is high-resistance

ADC

Analogue to digital converter

b

Voltage range in which the discharge network has a medium conductivity

C

Voltage range in which the discharge network has a higher conductivity

C1

First capacity

C1b

First integrating filter (third capacity)

C2

Second capacity

C.P

comparator

CPb

comparator

CPO

Comparator output

CPIR

Parasitic capacitance of the PIR sensor PIR

C.S

Current output of the differential transconductance amplifier

DAC

Digital to Analog Converter

DF

Downstream digital filter

I1

Another power source

I2

power source

Ia1

First current divider output

Ia2

Second current divider output

IN

First connection for the PIR sensor

Int

Integrating filter (in the simplest case an up/down counter)

Intb

Integrating filter (in the simplest case an up/down counter)

IN

Second connection for the PIR sensor

INFB

Tap on a resistance cascade (R _FB ) made up of individual resistors

IPIR

Power source of the PIR sensor equivalent circuit

Iref

Reference power source

IW1

First power source used as a working resistor

IW2

Second power source used as a working resistor

MUX

Analog 1:(n-1) or 1:n or 1:(n+1) multiplexer. n preferably has a value greater than three and/or 4. Values of n=(2 ^m -2) with m>2 or m>3 are particularly advantageous. In the present example, m=6 is chosen.

ON

First output of the differential stage

OP

Second output of the differential stage

Out

Output bus of the digital filter DF (= downstream filter DF)

ϕ1

First clock of the SC network to form a discharge resistor

ϕ2

Second clock of the SC network to form a discharge resistor. The clock is essentially inverse to ϕ ₁ and does not overlap with ϕ ₁ .

PIR

PIR sensor

R1

First work resistance

R2

Second working resistance

Rdis_1

First unfavorable discharge resistor in the prior art. This leads to a load on the output IP and a reduction in the output signal. In the device according to the invention, this resistance is modulated.

Rdis_2

Second unfavorable discharge resistor in the prior art. This leads to

RFB

a load on the output IN and a reduction of the output signal. In the device according to the invention, this resistance is modulated. Resistance cascade made up of individual resistors. A control signal (Val) controls the tapping of the output signal IN _FB . The resistance cascade therefore behaves like a potentiometer controlled by the value Val. The implementation is similar to the implementation of the current divider from multiplexer MUX and resistor cascade R _M1 to R _Mn .

RG

Discharge network This discharge network prevents the PIR sensor from charging both against ground and the PIR sensor connections against each other.

RIN(IP-IN)

Input resistance of the network R _G dependent on the difference voltage V(IP-IN) between the inputs IP and IN. The input resistance can be assumed to be between the connections IP and IN as well as between a connection IP or IN on the one hand and the reference potential, for example ground, on the other side. The behavior in 12 should preferably be similar in each of these two cases.

RL1

First work resistance

RL2

Second working resistance

RM

Current divider resistance. It is the sum value of the

RM1 to RMn

Resistor chain R _M1 to R _Mn made of n resistors. Resistors of the resistance chain consisting of n resistors of the current part of the differential stage according to the invention

RPIR

Internal resistance of the PIR sensor PIR, which is parallel to the outputs of the PIR sensor (see 1 )

RPIR_C

Series resistance of the parasitic capacitance C _PIR .

Sb

First node

T

ADC output with typically smaller bit width than the bus out

T1

First transistor of the differential stage

T2

Second transistor of the differential stage

T3

Third transistor

T4

Fourth transistor

T5 to T16

Transistors of an exemplary further discharge network.

Val

Control input of the multiplexer MUX

V(IP-IN)

Voltage between the outputs of the PIR sensor and thus between the inputs of the discharge network R _G

Vref

Reference voltage

Claims (3)

Device for operating a passive infrared detector (PIR) characterized in that - such PIR detectors are two-pole and can be symbolized in the equivalent circuit diagram by a current source which supplies a current (I _PIR ) depending on the change in irradiation and which has a capacity C _PIR is connected in parallel, whereby - the passive infrared detector (PIR) is provided with two electrical connections and - the device comprises a differential amplifier stage which has a reference current source (I _ref ) and - has a resistor (R _M1 to R _Mn ). and - wherein this resistor (R _M1 to R _Mn ) has a controllable tap which is connected to said reference current source (I _ref ) and - wherein a connection of the resistor (R _M1 to R _Mn ) is connected to a first transistor (T ₁ ). is connected and wherein the other terminal of the resistor (R _M1 to R _Mn ) is connected to a second transistor (T ₂ ) and - wherein the control electrode of the first transistor (T ₁ ) and the control electrode of the second transistor (T ₂ ) are the differential Input form and - where each transistor (T ₁ , T ₂ ) is connected with its third connection to a working resistance (R ₁ , R ₂ , C ₁ , C ₂ , IW ₁ , IW ₂ ), which is a differential working resistance can act, - a ΔΣ converter is provided for converting a differential analog input signal into a digital signal, - the outputs of this differential amplifier are each connected to an integrating filter and / or a capacitor and - the outputs of each integrating filter and / or each capacitor is connected to a comparator and - wherein the output of the comparator is connected to a digital integrating filter and / or an up / down counter, which at least temporarily changes its counter reading at predetermined and / or programmed time intervals depending on the output of the comparator incremented or decremented and - where the output of this digital integrating filter and / or the up / down counter is used for controlling the controllable resistance (R _M1 to R _Mn ) and - where the output of this digital filter directly and / or after filtering another digital filter is used as the output value of the ΔΣ converter. Device according to Claim 1 , - where the controllable resistor comprises an analog 1:(n-1) multiplexer or an analog 1:n multiplexer, or an analog 1:(n+1) multiplexer (MUX) connected to the single output that taps the Resistor (R _M1 to R _Mn ), is connected to said reference current source (I _ref ) and - wherein the resistor (R _M1 to R _Mn ) is a resistor chain of n resistors (R _M1 to R _Mn ) of the resistor (R _M1 to R _Mn ) and - wherein each of the (n-1) nodes between two of the n resistors (R _M1 to R _Mn ) of the resistor (R _M1 to R _Mn ) is connected to an input/output of the analog multiplexer (MUX). and - in the case of a 1:n multiplexer (MUX), the end or the beginning of the resistor chain made up of the n resistors (R _M1 to R _Mn ) of the resistor (R _M1 to R _Mn ) is additionally connected to the multiplexer (MUX). and - where in the case of a 1:(n+1) multiplexer (MUX), the end and the beginning of the resistor chain from the n resistors (R _M1 to R _Mn ) of the resistor (R _M1 to R _Mn ) with the multiplexer (MUX _{) . _ _ _} Resistors (R _M1 to R _Mn ) of the resistor (R _M1 to R _Mn ) are connected to at least one second transistor (T ₂ ). Device according to Claim 1 , whereby the ΔΣ converter has a control input by means of which the integration by the digital integrating filter and/or the counting up or down by the up/down counter can be prevented or enabled.

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