DE102012200532A1 - Method for manufacturing e.g. MOSFET, involves forming insulating substrate by spraying insulative material on exposed surface portions of chip and contact carrier device that remains uncovered by insulative material - Google Patents
Method for manufacturing e.g. MOSFET, involves forming insulating substrate by spraying insulative material on exposed surface portions of chip and contact carrier device that remains uncovered by insulative material Download PDFInfo
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- DE102012200532A1 DE102012200532A1 DE201210200532 DE102012200532A DE102012200532A1 DE 102012200532 A1 DE102012200532 A1 DE 102012200532A1 DE 201210200532 DE201210200532 DE 201210200532 DE 102012200532 A DE102012200532 A DE 102012200532A DE 102012200532 A1 DE102012200532 A1 DE 102012200532A1
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Abstract
Description
Die Erfindung betrifft ein Herstellungsverfahren für eine Halbleitervorrichtung. Des Weiteren betrifft die Erfindung eine Halbleitervorrichtung.The invention relates to a manufacturing method for a semiconductor device. Furthermore, the invention relates to a semiconductor device.
Stand der TechnikState of the art
In der
Offenbarung der ErfindungDisclosure of the invention
Die Erfindung schafft ein Herstellungsverfahren für eine Halbleitervorrichtung mit den Merkmalen des Anspruchs 1 und eine Halbleitervorrichtung mit den Merkmalen des Anspruchs 10.The invention provides a manufacturing method for a semiconductor device having the features of claim 1 and a semiconductor device having the features of
Vorteile der ErfindungAdvantages of the invention
Durch das Bilden der mindestens einen isolierenden Unterlage mittels eines gezielten Aufdruckens und/oder Aufsprühens mindestens eines isolierenden Materials, wobei eine freiliegende Teilfläche des mindestens einen Chips, der Trägerseite und/oder der Kontaktträgereinrichtung von dem isolierenden Material ungedeckt bleibt/freigehalten wird, kann die Anzahl der Arbeitsschritte zum Herstellen der Halbleitervorrichtung reduziert werden. Dies ermöglicht eine Vereinfachung des Herstellungsverfahrens und senkt die Herstellungskosten. By forming the at least one insulating substrate by means of a targeted printing and / or spraying of at least one insulating material, wherein an exposed partial surface of the at least one chip, the carrier side and / or the contact carrier device is left uncovered by the insulating material, the number the steps for manufacturing the semiconductor device can be reduced. This allows a simplification of the manufacturing process and lowers the manufacturing costs.
Gegenüber einem herkömmlichen Verfahrensschritt zum Bilden der mindestens einen isolierenden Unterlage mittels eines gesamtflächigen Aufbringens einer Isolationsschicht und eines anschließenden (optischen und/oder chemischen) Strukturierens der flächigen Isolationsschicht zum Freilegen von Bereichen des mindestens einen Chips, der Trägerseite und/oder der Kontaktträgereinrichtung kann mittels des hier beschriebenen Herstellungsverfahrens die mindestens eine isolierende Unterlage in einem einzigen Arbeitsschritt aufgebracht werden. Somit entfällt insbesondere die Notwendigkeit eines Herausstrukturierens der mindestens einen isolierenden Unterlage aus einer gesamtflächigen Isolationsschicht. Dadurch entfällt auch das Risiko eines Beschädigens von Komponenten des mindestens einen Chips, der Trägereinrichtung und/oder der Kontaktträgereinrichtung während eines Ätzschritts und/oder eines optischen Wegbrennens von Bereichen der mindestens einen Isolationsschicht. Es ist deshalb auch nicht notwendig, Komponenten des mindestens einen Chips, der Trägereinrichtung und/oder der Kontaktträgereinrichtung, welche bei dem Herausstrukturieren der mindestens einen isolierenden Unterlage aus einer gesamtflächigen Isolationsschicht beschädigt werden könnten, mit einer Schutzschicht abzudecken. Eine größere Designfreiheit beim Auslegen der mindestens einen isolierenden Unterlage und der entsprechenden Komponenten des mindestens einen Chips, der Trägereinrichtung und/oder der Kontaktträgereinrichtung ist zusätzlich gewährleistet.Compared to a conventional method step for forming the at least one insulating substrate by means of a total surface application of an insulating layer and a subsequent (optical and / or chemical) structuring of the sheet-like insulating layer to expose portions of the at least one chip, the carrier side and / or the contact carrier device can by means of described here manufacturing method, the at least one insulating pad are applied in a single step. Thus, in particular, the necessity of structuring out the at least one insulating backing from a total-area insulation layer is eliminated. This also eliminates the risk of damaging components of the at least one chip, the carrier device and / or the contact carrier device during an etching step and / or an optical burn-off of regions of the at least one insulating layer. It is therefore also not necessary to cover components of the at least one chip, the carrier device and / or the contact carrier device, which could be damaged in the structuring out of the at least one insulating pad from a total-area insulating layer, with a protective layer. A greater freedom of design when laying the at least one insulating pad and the corresponding components of the at least one chip, the carrier device and / or the contact carrier device is additionally ensured.
Es wird darauf hingewiesen, dass ein nachträgliches Strukturieren des mindestens einen isolierenden Materials der mindestens einen isolierenden Unterlage bei dem gezielten Aufbringen nicht notwendig ist. Selbst Feinkorrekturen des gezielt aufgedruckten und/oder aufgesprühten mindestens einen isolierenden Materials sind nicht notwendig.It should be noted that a subsequent structuring of the at least one insulating material of the at least one insulating pad in the targeted application is not necessary. Even fine corrections of the selectively printed and / or sprayed on at least one insulating material are not necessary.
Es wird nochmals darauf hingewiesen, dass unter dem zielgerichteten Aufdrucken und/oder Aufsprühen kein flächiges/gesamtflächiges Aufbringen, sondern ein partiales/lokales Aufbringen des mindestens einen isolierenden Materials unter Freihaltung von zumindest einer freiliegenden Teilfläche des mindestens einen Chips, der Trägerseite und/oder der Kontaktträgereinrichtung zu verstehen ist. It is again pointed out that under the targeted printing and / or spraying no surface / total surface application, but a partial / local application of the at least one insulating material, leaving free at least one exposed face of the at least one chip, the carrier side and / or Contact carrier device is to be understood.
Die mittels der vorliegenden Erfindung realisierbare Halbleitervorrichtung weist einen mittels der mindestens einen aufgebrachten Leitungseinrichtung realisierten flächigen Anschluss auf. Ein derartiger flächiger Anschluss hat eine geringere Streuinduktivität. Die Reduzierung der Streuinduktivität mittels des realisierbaren flächigen Anschluß kann eine schnelle Schaltzeit bewirken. Außerdem kann auf einfache Weise durch eine geeignete Auslegung des mindestens einen flächigen Anschlusses (einer von der Trägerseite weg gerichteten Chipvorderseite zu der Trägerseite und/oder der Kontaktträgereinrichtung) ein Widerstand der mindestens einen Leitungseinrichtung gesenkt werden. Durch den mindestens einen flächigen Anschluß kann auch eine Bauhöhe der Halbleitervorrichtung verringert werden. The semiconductor device which can be realized by means of the present invention has a planar connection realized by means of the at least one applied line device. Such a planar connection has a lower leakage inductance. The reduction of the leakage inductance by means of the realizable surface connection can cause a fast switching time. In addition, a resistance of the at least one line device can be lowered in a simple manner by a suitable design of the at least one planar connection (a chip front side facing away from the carrier side to the carrier side and / or the contact carrier device). Due to the at least one planar connection, a height of the semiconductor device can also be reduced.
Außerdem benötigt die realisierbare Halbleitervorrichtung kein Abdecken von Gatepads, welches bei einem Drahtbonden zum elektrischen Verbinden mindestens eines Chips mit einer Trägereinrichtung herkömmlicherweise notwendig ist. Dies bewirkt eine erhöhte Einsatztemperatur der realisierbaren Halbleitervorrichtung, wodurch weniger temperaturbedingte Ausfälle erreicht und die Zuverlässigkeit der Halbleitervorrichtung erhöht wird. Gegenüber einem Kupfer-Clip hat die mittels der vorliegenden Erfindung realisierbare Anschlußtechnik außerdem den Vorteil, dass auch verschiedene Anschlußtypen, wie beispielsweise Source- und/oder Gatekontakte, kontaktiert werden können.In addition, the realizable semiconductor device does not require masking of gate pads, which is conventionally necessary in wire bonding for electrically connecting at least one chip to a carrier device. This causes an increased use temperature of the realizable semiconductor device, whereby less temperature-induced failures are achieved and the reliability of the semiconductor device is increased. Across from a copper clip, the realizable by means of the present invention connection technology also has the advantage that also different types of terminals, such as source and / or gate contacts, can be contacted.
In einer vorteilhaften Ausführungsform wird die mindestens eine isolierende Unterlage mittels eines Tintendruckverfahrens (Tintenstrahldruckverfahren/Inkjet-Verfahren) und/oder eines Aerosolverfahrens aufgedruckt und/oder aufgesprüht. Das Verwenden eines Tintendruckverfahrens und/oder eines Aerosolverfahrens zum gezielten Aufbringen der mindestens einen isolierenden Unterlage bietet eine vorteilhafte Zielgenauigkeit für eine Vielzahl von isolierenden Materialien zu geringen Ausführungskosten. In an advantageous embodiment, the at least one insulating substrate is printed and / or sprayed on by means of an ink printing process (inkjet printing process / inkjet process) and / or an aerosol process. The use of an ink printing method and / or an aerosol method for the targeted application of the at least one insulating pad offers an advantageous target accuracy for a large number of insulating materials at low execution costs.
In einer weiteren vorteilhaften Ausführungsform wird (auch) die mindestens eine Leitungseinrichtung durch ein weiteres zielgerichtetes Aufdrucken und/oder Aufsprühen mindestens eines leitfähigen Materials gebildet. Somit kann auch anstelle eines gesamtflächigen/flächigen Aufbringens einer Metallschicht auf die freiliegenden Flächen der Trägerseite, des mindestens einen Chips, der mindestens einen isolierenden Unterlage und/oder der Kontaktträgereinrichtung und einem anschließenden Strukturieren der aufgebrachten Metallschicht die mindestens eine Leitungseinrichtung in einem einzigen Arbeitsschritt gebildet werden. Somit entfallen auch die Nachteile eines Strukturierens/Ätzens einer flächig/gesamtflächig aufgebrachten Metallschicht, wie beispielsweise Ätzschaden oder ungewollte Metallrückstände.In a further advantageous embodiment, the at least one conduit device is (also) formed by a further targeted printing and / or spraying of at least one conductive material. Thus, instead of a total area / surface application of a metal layer on the exposed surfaces of the carrier side, the at least one chip, the at least one insulating pad and / or the contact carrier device and a subsequent structuring of the applied metal layer, the at least one conduit means can be formed in a single step , This also eliminates the disadvantages of structuring / etching a flat / total surface applied metal layer, such as etch damage or unwanted metal residues.
Außerdem kann das aufgedruckte und/oder aufgesprühte mindestens eine leitfähige Material mittels eines stromlosen Galvanikschritts verstärkt werden. Somit können auch Leitungseinrichtungen mit einer vergleichsweise großen Schichtdicke gebildet werden. In addition, the printed and / or sprayed at least one conductive material can be amplified by means of an electroless plating step. Thus, conduction devices with a comparatively large layer thickness can also be formed.
Beispielsweise wird die mindestens eine Leitungseinrichtung unter Verwendung von Kupfer, Silber und/oder mindestens einem leitfähigen Polymer gebildet. Insbesondere Leitungseinrichtungen aus Kupfer, Silber und/oder mindestens einem leitfähigen Polymer können auf einfache Weise mittels eines Tintendruckverfahrens und/oder Aerosolverfahrens verläßlich gebildet werden. Die hier genannten Materialien gewährleisten auch einen vorteilhaften Zuleitungswiderstand. By way of example, the at least one conduit device is formed using copper, silver and / or at least one conductive polymer. In particular, conductor devices made of copper, silver and / or at least one conductive polymer can be reliably formed in a simple manner by means of an ink printing method and / or aerosol method. The materials mentioned here also ensure an advantageous lead resistance.
Außerdem kann die mindestens eine isolierende Unterlage unter Verwendung von mindestens einem organischen Polyimids und/oder mindestens einem isolierenden Polymer gebildet werden. Die Verwendung dieser Materialien bietet eine verlässliche Ausführbarkeit des zielgerichteten Aufdruckens und/oder Aufsprühens, insbesondere bei Anwendung des Tintendruckverfahrens und/oder Aerosolverfahrens.In addition, the at least one insulating backing may be formed using at least one organic polyimide and / or at least one insulating polymer. The use of these materials provides reliable performance of the targeted printing and / or spraying, especially when using the ink printing process and / or the aerosol process.
In einer weiteren vorteilhaften Ausführungsform wird der mindestens eine Chip auf der Trägerseite der Trägereinrichtung eutektisch gebondet, diffusionsgebondet, festgelötet und/oder festgesintert. Dies gewährleistet einen vorteilhaft sicheren Halt des mindestens einen Chips auf der Trägerseite auch bei einer signifikant variierenden Temperatur und/oder einer auf den mindestens einen Chip ausgeübten Kraft. In a further advantageous embodiment, the at least one chip is eutectically bonded, diffusion bonded, firmly soldered and / or firmly sintered on the carrier side of the carrier device. This ensures an advantageously secure hold of the at least one chip on the carrier side even at a significantly varying temperature and / or a force exerted on the at least one chip force.
Beispielsweise kann der mindestens eine Chip an einer DBC-Halbleiterstruktur und/oder einem Kupfer-Stanzgitter als der Trägereinrichtung angeordnet werden. Somit sind vorteilhafte Ausführungsbeispiele für die mindestens eine Trägereinrichtung verwendbar. For example, the at least one chip can be arranged on a DBC semiconductor structure and / or a copper stamped grid as the carrier device. Thus, advantageous embodiments for the at least one carrier device can be used.
Insbesondere kann ein Leitungshalbleiter als Halbleitervorrichtung hergestellt werden. Aufgrund der oben schon genannten Vorteile eines flächigen Chipanschlusses, wie beispielsweise ein reduzierter Zuleitungswiderstand, ein reduzierter Wärmewiderstand, ein flächiger Aufbau und/oder eine reduzierte Streuinduktivität, kann die mittels des hier beschriebenen Herstellungsverfahren hergestellte Halbleitervorrichtung auch als Leitungshalbleiter in der Leitungselektronik für das Steuern und Schalter hoher elektrischer Ströme und Spannungen verlässlich ausgelegt werden. Es wird darauf hingewiesen, dass der mittels des hier beschriebenen Herstellungsverfahrens gewonnene Leitungshalbleiter auch für das Steuern und Schalten von Strömen und Spannungen von mehreren tausend Ampere und Volt ausgelegt sein kann. In particular, a line semiconductor can be manufactured as a semiconductor device. Due to the above-mentioned advantages of a planar chip connection, such as a reduced lead resistance, a reduced thermal resistance, a planar structure and / or a reduced stray inductance, the semiconductor device produced by the manufacturing method described here can also be used as a line semiconductor in the line electronics for the control and switch high electrical currents and voltages are designed to be reliable. It should be noted that the line semiconductor obtained by means of the manufacturing method described here can also be designed for the control and switching of currents and voltages of several thousand amps and volts.
Die oben aufgezählten Vorteile des Herstellungsverfahrens sind auch bei einer Halbleitervorrichtung gewährleistet, welche zumindest das Merkmal aufweist, dass die mindestens eine isolierende Unterlage jeweils an mindestens einem von der mindestens einen Leitungseinrichtung unbedeckten Seitenrandbereich mit einer konvexen Krümmung abflachend geformt ist, da diese Halbleitervorrichtung offensichtlich mittels des oben beschriebenen Herstellungsverfahren hergestellt ist.The above-enumerated advantages of the manufacturing method are also ensured in a semiconductor device having at least the feature that the at least one insulating pad is flattened on at least one side edge portion having a convex curvature uncovered by the at least one lead means, since this semiconductor device is obviously formed by means of the prepared above manufacturing method.
Insbesondere kann die mindestens eine isolierende Unterlage jeweils an dem mindestens einen Seitenrandbereich exponentiell abgeflacht geformt sein. Die exponentiell abflachende Form der Seitenrandbereiche ist durch das Erstarren des gezielt aufgedruckten und/oder aufgesprühten mindestens einen isolierenden Materials der mindestens einen isolierenden Unterlage bedingt. In particular, the at least one insulating pad can be formed in each case exponentially flattened on the at least one side edge region. The exponentially flattening shape of the side edge regions is due to the solidification of the selectively printed and / or sprayed on at least one insulating material of the at least one insulating pad.
In bevorzugter Weise umfassen der mindestens eine Chip, die Trägereinrichtung und/oder die Kontaktträgereinrichtung Siliziumkarbid und/oder Galliumnitrid. Die Verwendung derartiger Halbleiter ist vorteilhaft, da dies eine Auslegung der Halbleitervorrichtung für relativ hohe Ströme und Spannungen gewährleistet. Somit ist die Halbleitervorrichtung vorteilhaft als Leitungshalbleiter einsetzbar.Preferably, the at least one chip, the carrier device and / or the contact carrier device silicon carbide and / or gallium nitride. The use of such semiconductors is advantageous because it ensures a design of the semiconductor device for relatively high currents and voltages. Thus, the semiconductor device is advantageously used as a line semiconductor.
Kurze Beschreibung der ZeichnungenBrief description of the drawings
Weitere Merkmale und Vorteile der vorliegenden Erfindung werden nachfolgend anhand der Figuren erläutert. Es zeigen:Further features and advantages of the present invention will be explained below with reference to the figures. Show it:
Ausführungsformen der ErfindungEmbodiments of the invention
Bei dem im Weiteren beschriebenen Herstellungsverfahren für eine Halbleitervorrichtung wird mindestens ein Chip
Der mindestens eine Chip kann an einer DBC-Halbleiterstruktur (Direct Bonded Copper) und/oder einem Kupfer-Stanzgitter als Trägereinrichtung
Der mindestens eine Chip
In einem weiteren Verfahrensschritt wird mindestens eine isolierende Unterlage
Es wird darauf hingewiesen, dass unter dem zielgerichteten Aufdrucken und/oder Aufsprühen des mindestens einen isolierenden Materials der mindestens einen isolierenden Unterlage
Die mindestens eine isolierende Unterlage
Bei der Ausführung des Herstellungsverfahrens kann die mindestens eine isolierende Unterlage
Die mindestens eine isolierende Unterlage
Die mindestens eine Leitungseinrichtung
Die mindestens eine Leitungseinrichtung
Die mindestens eine Leitungseinrichtung
Sofern dies gewünscht wird, kann das aufgedruckte und/oder aufgesprühte mindestens eine leitfähige Material der mindestens einen Leitungseinrichtung
Als Alternative zu einem stromlosen Galvanikschritt kann das Aufsprühen und/oder Aufdrucken des mindestens einen leitfähigen Materials auch mehrmals ausgeführt werden, um eine gewünschte Schichtdicke der mindestens einen Leitungseinrichtung
Die mindestens eine Leitungseinrichtung
Das Herstellungsverfahren bietet somit ein effizientes Fertigungsverfahren, auch durch einheitliche Deponierungstechnik für alle Kontakte des mindestens einen Chips
Obwohl die mindestens eine Leitungseinrichtung
Die mindestens eine isolierende Unterlage
Die mindestens eine isolierende Unterlage
Im Gegensatz zu einer herausgeätzten/herausstrukturierten Restisolationsschicht oder zu einer Folie weist die mindestens eine isolierende Unterlage
Insbesondere kann die mindestens eine isolierende Unterlage
Die Formen der Seitenrandbereiche
Außerdem kann auch eine Außenlinie
Ebenso kann die Außenfläche der der mindestens einen isolierenden Unterlage
Des Weiteren kann eine benachbart zu der mindestens einen Leitungseinrichtung
Die fertig hergestellte Halbleitervorrichtung kann für verschiedene Halbleiterbauelemente, insbesondere solche mit einem vertikalen Stromfluss, genutzt werden. Die Halbleitervorrichtung kann aufgrund der oben aufgezählten Vorteile insbesondere ein Leistungshalbleiter sein. Das hier beschriebene Herstellungsverfahren gewährleitet auch einen großen Freiheitsgrad bei der Festlegung des Zeitpunkts zum Vereinzeln des mindestens einen Chips
ZITATE ENTHALTEN IN DER BESCHREIBUNG QUOTES INCLUDE IN THE DESCRIPTION
Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.
Zitierte PatentliteraturCited patent literature
- US 2010/0210071 A1 [0002] US 2010/0210071 A1 [0002]
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DE201210200532 DE102012200532A1 (en) | 2012-01-16 | 2012-01-16 | Method for manufacturing e.g. MOSFET, involves forming insulating substrate by spraying insulative material on exposed surface portions of chip and contact carrier device that remains uncovered by insulative material |
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DE102005011652A1 (en) * | 2005-03-14 | 2007-02-01 | Infineon Technologies Ag | Semiconductor component production, especially for power semiconductor technology, requires forming through-apertures in masking layer at regions over identified contact surfaces |
DE102005037321A1 (en) * | 2005-08-04 | 2007-02-15 | Infineon Technologies Ag | Semiconductor component with interconnects between semiconductor chip and circuit carrier and method for producing the same |
US20090093090A1 (en) * | 2007-10-04 | 2009-04-09 | Infineon Technologies Ag | Method for producing a power semiconductor module comprising surface-mountable flat external contacts |
US20100210071A1 (en) | 2009-02-13 | 2010-08-19 | Infineon Technologies Ag | Method of manufacturing semiconductor devices |
DE102010000401A1 (en) * | 2009-02-12 | 2010-08-26 | Infineon Technologies Ag | Semiconductor device |
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DE102005011652A1 (en) * | 2005-03-14 | 2007-02-01 | Infineon Technologies Ag | Semiconductor component production, especially for power semiconductor technology, requires forming through-apertures in masking layer at regions over identified contact surfaces |
DE102005037321A1 (en) * | 2005-08-04 | 2007-02-15 | Infineon Technologies Ag | Semiconductor component with interconnects between semiconductor chip and circuit carrier and method for producing the same |
US20090093090A1 (en) * | 2007-10-04 | 2009-04-09 | Infineon Technologies Ag | Method for producing a power semiconductor module comprising surface-mountable flat external contacts |
DE102010000401A1 (en) * | 2009-02-12 | 2010-08-26 | Infineon Technologies Ag | Semiconductor device |
US20100210071A1 (en) | 2009-02-13 | 2010-08-19 | Infineon Technologies Ag | Method of manufacturing semiconductor devices |
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