DE102011120769B4 - Synchronously modulated full-digital delta-sigma modulator circuit - Google Patents

Abstract

A synchronously modulated full digital delta sigma modulator circuit comprising: a synchronous frequency modulator circuit (24) comprising - a multibit bus control signal input (28) connected to a fractional part multibit data bus (16) for a digital fractional part control signal (Df), - one A clock signal input (50) connected to a clock signal line (25) for a clock signal (clk), a reset signal input (51) connected to a reset signal line (26) for a reset signal (rst) and a multi-bit bus control signal output (29) with a frequency modulator data bus (27) for a digitally modulated digital fractional part control signal (Dfm), and further comprising four identical but individually programmable digital signal generators (31), (32), (33) and (34), - an over a multibit modulation data bus (36), (37), (38) and (39), respectively, to each of the digital modulation adders connected to these digital signal generators (31), (32), (33) and (34) rer (35) connected to the multi-bit bus control signal output (29) via the frequency modulator data bus (27), and wherein the synchronous frequency modulator circuit (24) is configured so that the clock signal line (25) and the reset signal line (26) are interconnected, that all digital signal generators (31), (32), (33) and (34) simultaneously the same clock signal (clk) and simultaneously receive the same reset signal (rst) and that both of the digital signal generator (31) generated digital Output signal as a data stream signal (fm1) via a multi-bit modulation data bus (36) as well as the digital output signal generated by the digital signal generator (32) as a data stream signal (fm2) via a multi-bit modulation data bus (37) as well as that of the digital signal generator ( 33) generated digital output signal as a data stream signal (fm3) via a multi-bit modulation data bus (38) as well as digitally generated by the digital signal generator (34) e output signal as a data stream signal (fm4) via a multi-bit modulation data bus (39) as well as - the digital decimal-portion control signal (Df) via a fractional part multi-bit data bus (16) - simultaneously and jointly supplied to the digital modulation adder (35), - this forms the synchronously clocked super-balanced sum of all of the above-mentioned signals and thus then provides a digitally modulated digital decimal point control signal (Dfm) which instead of the unmodulated digital decimal portion control signal (Df) for further processing via the multi-bit bus control signal output (29) subsequent full-digital delta-sigma modulator circuit is provided.

Description

Technical area

The present invention generally relates to improving the stochasticity of delta-sigma digital fully modulator circuits and, more particularly, to improving signal generation using delta-sigma modulator (DD-DSM) fully controlled fractional-N PLL frequency synthesizer circuits.

State of the art

For example, frequency synthesizers are used today to generate arbitrary sinusoidal signals in the frequency range of a few gigahertz in steps of a few hertz from a reference signal with a frequency of a few megahertz.

For a long time, frequency-synthesized circuits have conventionally used circuits with integer-divisional phase-locked loops (integer N-PLL). That's what the DD 283 880 A5 from 1983 such a circuit.

In this case, a comparison signal with a comparison frequency is continuously compared with the divided by an integer divider output signal by means of a phase detector, the latter represents an improved development of the phase detector. The phase detector compares the temporal sequence z. B. the rising edges of the above two digital signals. If the output signal corresponds exactly to the integer multiple of the comparison signal, then the edge times are identical, the charge pump is then inactive, the loop filter supplies a constant voltage to the voltage-controlled oscillator, which then retains its frequency exactly.

For example, when the voltage-controlled oscillator changes its frequency by heating, the phase detector detects a deviation in the respective timing of the rising edges of the digital signals and activates the charge pump.

By appropriate charge transport into the loop filter or by removal of charges from the loop filter, the control voltage at the output of the filter is adjusted so that the voltage-controlled oscillator is readjusted with respect to its signal frequency.

By changing the divider ratio, a correspondingly different output frequency of the voltage-controlled oscillator can be set at any time. Due to the above-described feedback, the control voltage for the voltage-controlled oscillator is varied until the output signal generated by it again corresponds exactly to the now-changed integer multiple of the comparison signal. Such an arrangement can therefore generate output frequencies in the raster of the integer multiple of the comparison frequency.

However, if, for example, at signal frequencies in the range of a few gigahertz, one wishes to achieve a step size of the output frequency in the range of, for example, 0.001 Hz, then reference oscillators with a comparison frequency of 0.001 Hz must be used in the above-described circuits with integer-divisor phase-locked loops (integer-N-PLL) become. However, this would make the control loop unacceptably slow. Integer-N PLL circuits are therefore useless for such task.

The solution to this problem area is provided by the fractional-divider phase-locked loop (Fractional-N-PLL). Such circuits are already known and, for example, in the DE 698 29 166 T2 described.

For fractional-N PLL frequency synthesizer circuits, for example, the division ratio N of the main divider is increased by 1 according to a predetermined scheme. By this procedure, a fractional division ratio is achieved on average over time. The associated loop filters are typically designed so that the noise generated by the continuous switching is largely eliminated in the output signal. However, often very disturbing parasitic spectral components remain, which are due to the continuous switching of the divider ratio. Improvement for this problem area can be achieved in certain circumstances, for example, through the use of additional delta-sigma modulators associated with fractional-divider phase-locked loops (Fractional-N-PLL) circuits.

Such circuits are already known and, for example, in the US 2008/0024240 A1 described. By using delta-sigma modulators to drive the fractional main divider, the switching of the divider module is much more compatible. In addition, the switching times do not take place only at a periodically fixed time, but are statistically distributed by the special properties of the delta-sigma modulator. As a result, the interfering spectral components are shifted into a frequency range in which they can be filtered out much easier.

Nevertheless, even in the improved circuits still disturbing spectral components that can have undesirable effects with increasingly sophisticated demands on the circuits depending on the application.

The remedy for this problem area is provided by the fractional-divider phase-locked loops (fractional-N-PLL) circuits with higher-order delta-sigma modulators.

Such circuits are already known and, for example, in the DE 101 49 593 A1 described. By using delta-sigma modulators with up to z. B. to the fourth order to drive the fractional main divider the spurious spectral components are further reduced.

In this respect, the published patent application DE 101 49 593 A1 called "single-bit sigma-delta-modulated fractional-N-frequency synthesizer" in the present invention, the state of the art because a synthesizer based on a sigma-delta modulator, which is already a cascade, is also used there -Akkumulatorschaltung having a provision.

To summarize, the invention discloses therein: "A fractional-N frequency synthesizer includes a voltage-controlled oscillator, a dual-modulus divider that divides an output frequency of the voltage-controlled oscillator according to a fractional control quantity, and a phase comparator. which compares a phase of an output of the dual modulus divider with a phase of a reference frequency, wherein an output of the phase comparator controls an input of the voltage controlled oscillator. The synthesizer further includes a sigma-delta modulator having a single-bit output and a bit converter that converts the single-bit output of the sigma-delta modulator to the fractional control magnitude applied to the dual-modulus divider . "

Another prior art document is the "United States Patent Application Publication" with the publication number US 2008/0157 823 A1 and named "PHASE LOCKED LOOP FREQUENCY SYNTHESIZER". It also discloses a synthesizer that uses a delta-sigma modulator to improve signal quality and has, inter alia, an additional modulator ("Auxiliary Multilayer Modulator") but here for the digital precompression control signal and not for the digital fractional control signal is used, resulting in the disadvantages or problems described below.

The decisive for the signal quality digital decimal portion control signal is also varied according to this document in a known manner only directly with the help of the delta-sigma modulator. This procedure corresponds to the state of the art researched here, on which the invention presented below builds.

As the closest prior art, the "United States Patent Application Publication" with the publication number US 2011/0 133 797 A1 regarded as "NOVEL METHOD OF FREQUENCY SYNTHESIS FOR FAST SWITCHING".

This document discloses a delta-sigma modulator circuit having a plurality of signal generators which are controlled or added by a delta-sigma modulator in response to a digital decimal-part control signal.

The decisive for the signal quality digital decimal proportion control signal is thus also varied according to this document, which basically agrees in principle with the invention described herein and with the approach to signal improvement in principle. However, the realizations of the synthesis of the signal variations are significantly different from the invention presented here.

Presentation of the deficiencies of the previously known versions

Despite all the circuit measures taken but again and again disturbing spectral components are observed in the immediate vicinity of the frequency spectrum of the synthesized output signal sporadically appear in an initially unrecognizable temporal sequence and then disappear again and which is still high orders of delta-sigma modulators and despite all Careful filter measures can not be eliminated. In practice, so-called spurs are generated by overcoupling, non-linear charge pumps, etc., which are often only a few 10 kHz to 100 kHz in addition to the signal frequency to be generated and are therefore difficult to filter out. Detailed simulations of the relationships in the interaction of the signals involved in DD-DSM fractional-N PLL frequency synthesizers Circuits with the aid of the computer reveal, as a disturbing cause, superimposed sinusoidal signal components, which are connected in phase with the timing of the delta-sigma modulator.

Especially for interference signals of this type, no circuit measures are known, taking advantage of the already existing Circuit components by a slight modification of the arrangement, can achieve significant improvements. At this point, the present invention begins.

Illustration of the present invention:

Task, solution, benefits

Based on the above-mentioned shortcomings and disadvantages of the prior art, the present invention seeks to remedy the problem of unwanted, carrier near interfering spectral components with relatively little circuit complexity and thereby the respective synthesized output of fully digital DD-DSM fractional-N PLL frequency synthesizer circuits significantly improve.

This object is achieved by the features listed in the main claim and in the subclaims. Advantageous embodiments and expedient developments of the present invention are also characterized in the respective subclaims.

The advantages achieved by the invention are in particular that only by an upstream additional electronic circuit with relatively little additional circuit complexity, thus by minor modifications and only small-scale extension to the relevant integrated circuits, the unwanted spectral components can be eliminated. Another advantage achieved by the invention is, in particular, that such a modified block can be fully functionally compatible and pin-compatible, because it makes no fundamental changes to the circuit, but is merely installed as an extension in the respective DD-DSM control loop, which For example, a retrofitting and thus significant improvement of the electrical properties of existing product lines can be made by a simple replacement by such improved circuit chips.

list of figures

• 1 schematisch den typischen Aufbau einer modernen DD-DSM Fraktionalen-N-PLL-Frequenzsynthesizer Schaltung, wie er hier als Stand der Technik ermittelt worden ist und auf dem die hier beschriebene Erfindung aufbaut,
• 2 schematisch den typischen Aufbau einer modernen DD-DSM Fraktionalen-N-PLL-Frequenzsynthesizer Schaltung mit einem Ausführungsbeispiel der erfindungsgemäßen Schaltungserweiterung und deren einfache Integration in die herkömmliche Schaltung,
• 3 schematisch beispielhaft den inneren schaltungstechnischen Aufbau der erfindungsgemäßen Schaltungserweiterung,
• 4 schematisch beispielhaft weitere Details des schaltungstechnischen Aufbaus von elektronischen Bausteinen der erfindungsgemäßen Schaltungserweiterung.

To explain the invention drawings are given, which are described in more detail below. It shows

• 1 schematically the typical structure of a modern DD-DSM fractional-N PLL frequency synthesizer circuit, as has been determined here as prior art and on which builds the invention described here,
• 2 schematically the typical structure of a modern DD-DSM fractional-N PLL frequency synthesizer circuit with an embodiment of the circuit expansion according to the invention and their simple integration into the conventional circuit,
• 3 schematically exemplifies the internal circuitry construction of the circuit expansion according to the invention,
• 4 schematically exemplary further details of the circuit construction of electronic components of the circuit expansion according to the invention.

Example for carrying out the present invention

To explain the invention is in 1 schematically shows the typical structure of a modern DD-DSM fractional-N PLL frequency synthesizer circuit as it corresponds to the current state of the art.

A frequency stable oscillator circuit (1) , which may be stabilized by a quartz oscillator, for example, generates a continuously changing output signal, which periodically varies between a maximum voltage value ("High") and a minimum voltage value ("Low") and can therefore be regarded as a digital signal.

A reference frequency divider circuit (2) shares that from the frequency stable oscillator circuit (1) supplied high-frequency signal by a fixed reference numerical value (R), wherein the value for the reference numerical value (R) include all natural numbers except the zero, but otherwise can be chosen arbitrarily in principle.

As a reference signal for the intended function of the circuit is a digital comparison signal (8th) required in principle any frequency, which are either directly from the frequency-stable oscillator circuit (1) or from the, the frequency-stable oscillator circuit (1) downstream reference frequency divider circuit (2), can be obtained. This digital comparison signal (8th) is supplied to a phase detector circuit (3) as a first of two digital input signals.

There is also a voltage controlled variable frequency oscillator circuit (6), also called VFO (Variable Frequency Oscillator), which provides a continuous high frequency output signal (9) generated, which represents the actual useful signal of the entire circuit. The output of this voltage controlled, variable frequency oscillator circuit (6) is now split into two paths.

The majority of this signal is used for the intended electronic further processing. A small portion of this signal, for example, coupled via an attenuator, fed back into the circuit and used to monitor the signal frequency.

For this purpose, this signal first passes to a frequency divider circuit (7), which can divide the continuous high-frequency output signal (9) by a variable divisor numerical value (N), wherein the value for the divisor numerical value (N) in principle all natural numbers except the May include zero. This divider can very quickly change to another divisor numeric value (N) be switched.

The current value for the divisor numeric value (N) is determined by such a digital number passing through a digital frequency divider data bus (21) the frequency divider circuit (7) is supplied and in principle can be set as intended. Thereby, the continuous high-frequency output signal (9) is divided by the respective value for the divisor numerical value (N) and serves as a digital reference signal (10) , It is considered a second of two digital input signals of the phase detector circuit (3) fed. From the comparison of the time sequence of the edges of these two input signals now generates the phase detector circuit (3) an output signal for driving a charge pump (4) , Depending on the specific nature of the structure of the circuit, various scenarios are now possible. For example, a typical circuit arrangement would cause the charge pump (4) depending on the time difference of both edges more charge in the connected loop filter (5) provides, whereby the voltage for controlling the frequency of the variable frequency oscillator circuit (6) to a certain value is increasingly varied, so for example, the voltage to control the frequency of the frequency-variable oscillator circuit (6) increase when the signal edge of the digital reference signal (10) at a later time from "low" to "high" changes than the digital comparison signal (8th) ,

Conversely, a typical circuit arrangement would, for example, cause the charge pump (4) depending on the reverse time difference of both edges negative charge in the connected loop filter (5) provides, whereby the voltage for controlling the frequency of the variable frequency oscillator circuit (6) is varied toward a certain decreasing value, that is, for example, the voltage would be used to control the frequency of the frequency-variable oscillator circuit (6) fall off when the signal edge of the digital reference signal (10) switches from "low" to "high" at an earlier time than with the digital comparison signal (8th) ,

The described circuit blocks are connected in such a way that the interaction of these circuit blocks results in a self-contained control loop, which causes the frequency of the continuous high-frequency output signal (9) is kept constant at such a value, by the respective division ratio of the frequency divider circuit (7) and thus the respective value of the digital divider numerical value (N) passing through a digital frequency divider data bus (21) of the frequency divider circuit (7) is supplied is determined.

The loop filter (5) acts like a low-pass filter and prevents the voltage to control the frequency of the frequency-variable oscillator circuit (6) can change abruptly. Thus, it has an integrating effect on the otherwise erratic voltage curve, which would result from the constant switching of the current direction in the charge pump (4).

To achieve any division ratios of the frequency divider circuit (7), the respective digital value of the divisor numerical value (N) varied continuously. As a result, the dividing ratio to be set according to the input divider ratio data (D) is finally achieved in the time average.

In older, simpler versions of fractional-N PLL frequency synthesizer circuits, the divisor numerical value (N) becomes the frequency divider circuit (7) temporarily increased, for example, by 1 according to a fixed schedule. Therefore, such a circuit is also often referred to as an N / N + 1 divider circuit.

In modern versions of fully digital delta-sigma modulator fractional-N PLL frequency synthesizer circuits provides the frequency divider circuit (7) a digital multi-modulus divider, which assumes the most different division ratios in normal operation, that is, for example, from N-7 to N + 8.

This depends on the special characteristics of the fully digital delta-sigma modulator circuit (23) together and will be discussed below by way of example.

First, the dividing ratio to be set becomes according to the inputted dividing ratio data (D) as any digital fixed-point number or floating-point number via a divider ratio data bus (15) of a number divider circuit (11) supplied which the Vorkommaanteil this number as a digital Vorkommaanteil control signal (Di) over one Integer part data bus (17) directly to the divider adder (12), because it has been found to be advantageous to use only the fractional fractional part as a digital fractional part control signal (Df) to use for driving the fully digital delta-sigma modulator circuit (23).

The fractional part of this number is applied to the digital input adder as a digital fractional part control signal (Df) via a fractional part multi-bit data bus (16) (13) the fully digital delta-sigma modulator circuit (23) fed.

That via an output data bus (18) output signal of the digital inner delta-sigma modulator circuit provided as a digital numerical value (Dn) (14) Then, in conventional modern fully digital delta-sigma modulator (DD-DSM) controlled fractional-N PLL frequency synthesizer circuits, both the divider data bus (19) and the divider adder (12) supplied to the digital Vorkommaanteil control signal (Di) and that of the fully digital delta-sigma modulator circuit (23) processed original digital fractional part control signal (Df) using the divide-by-adder (12) as a divisor numerical value (N) adds additively according to the divider ratio to be set and then via the digital frequency divider data bus (21) to the frequency divider circuit (7) and in parallel via a feedback data bus (20) to the inverting input of the digital input adder (13) the fully digital delta-sigma modulator circuit (23) supplies the digital difference value over an inner data bus (22) to a digital inner delta-sigma modulator circuit (14) then this digital delta-sigma inner modulator circuit (14) may each be a first order, second order, third order, or higher order delta sigma modulator circuit.

By the interaction of the inverting input of the digital input adder (13) with the inner data bus (22) , the digital in-delta sigma modulator circuit (14), the output data bus (18) for the output value and the feedback data bus (20) results in a closed loop for the fully digital delta-sigma modulator circuit (23) such that the over the output data bus (18) digital numerical value provided for the output value (Dn) the fully digital delta-sigma modulator circuit (23) in the time average over the fractional part multi-bit data bus (16) supplied in the form of the digital decimal-portion control signal (Df) in the digital numerical value corresponds exactly, but the respective instantaneous value varies during short periods in rapid order, whereby the frequency divider circuit (7) can realize any divider ratio in the time average. The fully digital delta-sigma modulator circuit (23) thus sets the digital fractional part control signal (Df) into a continuous sequence of integers, which thus form the output signal in the form of the digital numerical value (Dn).

This results in the fractional part in the form of the digital fractional part control signal (Df) as a total of all digital numerical values normalized to the number of iteration steps (Dn) ,

By this measure, the disturbances caused by the switching of the divider ratio in the output spectrum of the continuous high-frequency output signal (9) because of the special switching sequence of the fully digital delta-sigma modulator circuit (23) shifted in a frequency range in which they can be filtered easily from the loop filter (5).

In order to clarify the relevant prior art, it should again be summarized here that the divider ratio to be set according to the divider ratio data (D) in a Vorkommaanteil, realized by the digital Vorkommaanteil control signal (Di) , and a fractional part, realized by the digital fractional part control signal (Df) , is split; and the divider ratio, according to the divisor numerical value (N), of the frequency divider circuit (7) is continuously switched by means of a pseudo-random signal supplied by the all-digital delta-sigma modulator circuit (23).

To further optimize the timing of the digital reference signal (10) at a branch point for the clock signal (30), this branch point can be conveniently secured by an electronic buffer circuit against overload, as a clock signal (Clk) with the help of the clock signal line (25) supplied to the fully digital delta-sigma modulator circuit (23).

Furthermore, a reset signal (Rst) with the aid of the reset signal line (26) also the fully digital delta-sigma modulator circuit (23) are supplied, whereby the timing of the fully digital delta-sigma modulator circuit (23) can be additionally controlled.

In the case of fully digital delta-sigma modulator fractional-N-PLL frequency synthesizer circuits, in the ideal case no unwanted deterministic sinusoidal interference signal components - the so-called spurs - are generated, which often lie with their frequency spectrum in close proximity to the specifically generated carrier signal and then called baseband spurs become.

In real practice, however, spurs are repeatedly generated by overcoupling, by non-linear charge pumps and other non-ideal conditions or electronic circuit modules, for example, only a few 10 kilohertz to 100 kilohertz next to the desired carrier signal and therefore not sufficiently filtered out for the vast majority of applications which can lead to functional degradations of the entire complex electronic circuit.

To analyze the problem, the interaction of the respective signals involved and the electronic conditions in modern DD-DSM fractional-N PLL frequency synthesizer circuits can be simulated using the computer. As a result, a number of superimposed sinusoidal signal components, which are obviously phase-locked with the timing of the delta-sigma modulator, are revealed.

A simple mathematical lighting illuminates the connections and shows the problem solution.

mit der konstanten Sollfrequenz $f_{Soll}^0,$

den jeweiligen Basisband-Spurfrequenzen f_spur,i, den jeweiligen Phasenwinkeln φ_i und den jeweiligen Amplituden A_i der Basisband-Spurs.Assuming a pure phase modulation, the following applies to the phase angle φ (t) of the output signal: $$\phi \left(t\right)=2\pi f_{SOll}^0\cdot t+{\displaystyle \underset{i}{\Sigma }{A}_i\text{cos}\left(\text{2}\pi {\text{f}}_{Spur.i}+{\phi }_i\right).}$$

with the constant nominal frequency $f_{SOll}^0.$

the respective baseband track frequencies f _{track, i} , the respective phase angles φ _i and the respective amplitudes A _{i of} the baseband track.

Here, the time t = 0 corresponds to the start time of each delta-sigma modulator used here. In the next simulation step, the setpoint frequency is not kept constant, but it is varied.

Since the respective individual amplitudes A _{i of} the baseband spurs are smaller by a few orders of magnitude compared to the amplitude of the nominal frequency, the phase angle φ (t) of the output signal at a variable nominal frequency with a very good approximation now applies: $$\phi \left(t\right)\approx 2\pi {\displaystyle \int f_{SOll}^0\left(t\right)dt,}$$

ergibt sich durch Einsetzen und Umformen der Gleichungen als Bedingung für die Auslöschung der störenden Spektralanteile der Zusammenhang: $$B_i\approx -\frac{A_i}{2\pi f_{Spur,i}}.$$

With a solution in the form: $$f_{SOll}\left(t\right)=f_{SOll}^0+{\displaystyle \underset{i}{\Sigma }{B}_i\text{sin}\left(2\pi f_{Spur.i}\cdot t+{\phi }_i\right)}$$

results from inserting and transforming the equations as a condition for the extinction of the interfering spectral components of the relationship: $$B_i\approx -\frac{A_i}{2\pi f_{Spur.i}},$$

zunächst gezielt mit sinusförmigen Signalen geringer Amplitude gemäß der Gleichung (03) und der Gleichung (04) überlagert wird.The disturbances can thus be compensated if the constant nominal frequency $f_{SOll}^0$

initially superimposed selectively with sinusoidal signals of low amplitude according to the equation (03) and the equation (04).

In order to realize this measure for eliminating the baseband spurs with the lowest possible circuitry complexity, according to the invention, only the fractional decimal portion in the form of the digital decimal portion control signal (Df) for driving the fully digital delta-sigma modulator circuit (23) - modulated with a number of sinusoidal oscillations by means of a synchronous frequency modulator circuit (24) according to the invention and additionally inserted as an extension of the hitherto known fully digital delta-sigma modulator circuits.

The 2 schematically shows the typical structure of a modern DD-DSM fractional-N PLL frequency synthesizer circuit with an embodiment of the circuit expansion according to the invention in the form of an additional synchronous frequency modulator circuit (24) and their easy integration into the conventional circuit. In addition to the electronic components known from the prior art for constructing a modern DD-DSM fractional-N PLL frequency synthesizer circuit, there is now a synchronous frequency modulator circuit (24) between the numeric divider circuit (11) and the fully digital delta Sigma modulator circuit (23), whereby the fractional-part multi-bit data bus (16) originating from the divider circuit (11) over which the fractional decimal part represented by the digital decimal-portion control signal (Df) for driving the all-digital delta sigma -Modulator circuit (23) is guided, first is first redirected.

The digital numerical value of the fractional decimal portion originating from the number divider circuit (11) in the form of the digital fractional part control signal (Df) thus initially passes through a multi-bit bus Control signal input (28) in the synchronous frequency modulator circuit (24).

Here, these digital numerical values are supplemented with additional data, stored in a programmable memory in the form of a so-called look-up table, of different sinusoidal oscillations, discrete in time, with different frequencies and different amplitudes.

This measure digitally modulates the digital post-commutation control signal (Df), which represents the fractional fractional part.

It then passes as a digitally modulated digital decimal portion control signal (Dfm) to the multi-bit bus control signal output (29) and then then via the frequency modulator data bus (27) first to the fully digital delta-sigma modulator circuit (23) and is used as the now modulated digital numeric value for driving.

The synchronicity of the synchronous frequency modulator circuit (24), which has an extremely significant influence on the signal quality of the continuous high-frequency output signal (9) This ensures that, for both the synchronous frequency modulator circuit (24) and the all-digital delta-sigma modulator circuit (23), one and the same clock signal line (25) for each, at the branch point for the clock signal (30) decoupled clock signals (clk) and one and the same reset signal line (26) for the respective reset signals (Rst) be used. By sharing the respective lines, it is ensured that the respectively time-variant signals involved are always identical for both electronic components.

The variant presented here is only a typical application example. Numerous expedient modifications of the circuit arrangements are conceivable. Alternatively, for example, synchronization measures can also be undertaken with the aid of signals derived from the internal parameters of the fully digital delta-sigma modulator circuit (23), if this is advantageous.

A further synchronization to the frequency divider circuit (7) is not required, since it passes through all states very quickly compared to the frequencies f _{track, i} the baseband _track and thus the phase errors generated thereby are negligible.

The 3 shows schematically by way of example the internal circuit construction of the synchronous frequency modulator circuit (24) as a circuit expansion according to the invention.

The synchronous frequency modulator circuit (24) has a digital modulation adder (35) and a sufficient number of identically constructed but different data programmed digital signal generators (31), (32), (33) and (34) for respective sinusoidal data stream signals (Fm1) . (Fm2) . (FM3) and (FM4) ,

The number of digital signal generators can in principle be chosen arbitrarily. In the embodiment shown here, arbitrarily four digital signal generators (31), (32), (33) and (34) have been drawn, which represents a lower limit of the number.

In this case, the digital signal generator generates in the circuit reproduced here by way of example (31) the data stream signal (fm1), the digital signal generator (32) the data flow signal (fm2), the digital signal generator (33) the data stream signal (FM3) and the digital signal generator (34) the data stream signal (FM4) ,

The points in the 3 between the digital signal generator (33) and the digital signal generator (34) are intended to symbolically indicate that the number of digital signal generators can be extended in principle beyond the marked extent.

All digital signal generators (31) . (32) . (33) and (34) are structurally identical and therefore identical in terms of circuitry. The difference between the individual digital signal generators lies only in the programming, ie in the differently stored information stored in the respective digital signal generators (31), (32), (33) and (34), ie in the different data in form the stored respective lookup tables contained therein.

Via a clock signal input (50) receive the respective digital signal generators (31) . (32) . (33) and (34) all at the same time the same clock signals (Clk) via a common clock signal line (25) , This ensures a time-synchronous readout of the respective data stream signals with certainty.

In addition, the digital signal generators receive (31) . (32) . (33) and (34) via a reset signal input (51) also each time all the same reset signals (rst) via a common reset signal line (26). This ensures a time-synchronous readout of the respective data stream signals with certainty.

By the same reset signals (Rst) on the common reset signal line (26) and by the same clock signals (clk) on the common clock signal line (25) the retrieval of the data, the waveforms stored in the respective internal look-up tables, is initiated synchronously.

Thus, the retrieved temporally discretized sinusoidal voltage fluctuations with previously stored predetermined amplitudes, frequency values and zero phase angles become a digitized data current signal (Fm1) to (FM4) the respective digital signal generators (31) to (34) generated synchronously as output signals in time. The values of these respective digital output signals are then passed through the respective multi-bit modulation data bus (36), (37), (38) and (39) to the digital modulation adder (35) fed.

In addition, the digital post-commutation control signal (Df) is added via the fractional part multi-bit data bus (16) also the digital modulation adder (35) fed.

The sum of all these digital signals gives as an output the digitally modulated digital decimal part control signal (Dfm) which is supplied via the frequency modulator data bus (27) and via the multi-bit bus control signal output from the synchronous frequency modulator circuit (24) then the digital input adder (13) the fully digital delta-sigma modulator circuit (23) fed and further processed as intended.

As already mentioned, the number of digital signal generators can in principle be chosen arbitrarily. In practice, a significant improvement in signal quality is already evident in a number of four digital signal generators. For even better results, the number can be increased without major problems, for example, to sixteen. However, it is always to be weighed responsibly, whether the increased circuit requirement, area consumption, power consumption, etc. inevitably associated with a further increase in the number of digital signal generators is justified for the respective application.

The 4 schematically shows, by way of example, further details of the circuit construction of electronic components of the circuit expansion according to the invention. As an example, the internal structure of the digital signal generator (31) is shown. Since all digital signal generators are constructed identically and differ only by the data stored in the internal memory, the detailed exemplary description of only one of these blocks suffices.

A digital signal generator (31) has a counter module as index generator (41) , To diverge with the fully digital delta-sigma modulator circuit (23) The counter module must be avoided (41) have the same width as their accumulators, so for example be 32 bits wide.

At each edge of the clock signal (Clk) on the common clock signal line (25) will now be this counter block (41) with a digital increment value, which was previously stored in the increment value data memory (44) applied. For this purpose, the current counter value via the internal data bus (46) a digital generator adder (42) fed, which from a programmable incremental data memory (44) via an internal increment data bus (47) the previously stored value to the digital generator adder (42) which adds the sum of these two digital values via another internal adder data bus (48) to the counter module (41) returns.

It is expedient to use only the four highest significant data bits or another number of the most significant significant data bits of the counter module (41) to be indexed by means of the counter module data bus (45) from a function history data memory serving as a lookup table (43) Recall the previously stored mathematical data values of a discrete, sinusoidal oscillation at various times with programmable amplitude, frequency, and phase angle values and as a digital output over the multi-bit modulation data bus (36) to the digital modulation adder (35) supply.

digital diskretisiert auf beispielsweise sechzehn oder mehr als sechzehn verschiedenen Zeitpunkten, abgerufen. Über einen gemeinsamen Programmierdatenbus (49) werden die jeweiligen Informationen als Programmierdaten (DR) für den programmierbaren Inkrementwertdatenspeicher (44) und den Funktionsverlaufsdatenspeicher (43) über einen gemeinsamen Schnittstelleneingang (40) zugeführt.In this way, the previously stored mathematical data values are used as function curves in the mathematical form $$f\left(t\right)=B_i\text{sin}\left(2\pi f_{Spur.i}\cdot t+{\phi }_i\right)$$

digitally discretized at, for example, sixteen or more than sixteen different times. Via a common programming data bus (49) the respective information is called programming data (DR) for the programmable increment value data memory (44) and the function history datastore (43) via a common interface input (40) fed.

An associated programming interface facilitates the convenient storage of the data both in the function history data memory (43) and in the increment value data memory (44) and thus allows a possible correction and optimization of the data records at any time. In particular, you can By subsequently adapting the data sets also further disturbances in the signal spectrum, which are only later determined metrologically but whose origin is largely unknown, are effectively combated by the targeted choice of data values. Thus, the presented invention is very well suited for the practice and has a significant economic benefit.

The synchronously modulated full digital delta-sigma modulator circuit has hitherto been described by way of example in direct connection with a very suitable application example, namely a contemporary fully digital delta-sigma modulator (DD-DSM) controlled fractional-N PLL frequency synthesizer circuit. By means of this application example, which is very familiar to the person skilled in the art, the effectiveness of this method for improving the signal could be explained vividly and clearly.

However, the subject of the invention presented here is not merely a special circuit for improving the signal quality of a fully digital delta-sigma modulator (DD-DSM) controlled fractional-N PLL frequency synthesizer circuit, but quite a more general method for modifying the output signal of a fully digital delta-sigma modulator circuit, which may also result in other circuits, in which also fully digital delta-sigma modulator are used, such as in the measurement data acquisition, where appropriate, advantageous improvements.

The method is always based on digitally storing mathematical data values of numerous discrete sinusoidal oscillations each having different amplitudes, different frequencies and different zero phase angles at different times, each individual discretized sinusoidal oscillation receiving an individual memory address. These values are provided in a function history data memory (43) whose respective memory contents are targeted by the supply of a digital index number whose value is continuously varied after each read out of the full memory contents by a random generator circuit, both by a clock signal (clk) and by a reset signal (Rst) controlled, in each case isochronously read out as a data stream. As a result, a modification signal is generated which is formed by a clock-synchronized readout of programmed mathematical data values of at least one or more discretized sinusoidal oscillations at different times and the addition of these digital numerical values to the digital numerical values of an unmodified input signal. wherein generating the modification signal comprises modifying the output signal of the all-digital delta-sigma modulator circuit by supplying the thus modulated input signal, that is, in place of the unmodified input signal.

In particular, this method is particularly suitable for controlling a fully digital delta-sigma modulator (DD-DSM) controlled fractional-N PLL frequency synthesizer, then by this method, the output of a fully digital delta-sigma modulator circuit by a digital numerical modulation with the discretized data of different harmonic electrical oscillations is modified, wherein the control signals then on the one hand the digital decimal portion control signal (Df) and on the other hand the digital Vorkommaanteil control signal (Di) of the divider ratio according to the predetermined divisor ratio data (D) are and wherein the frequency divider circuit (7) the fractional-N PLL frequency synthesizer is then controlled by the modification signal thus generated.

For this method, a synchronously modulated full digital delta-sigma modulator circuit is always used. This has a synchronous frequency modulator circuit as an extension of the prior art according to the invention (24) , with a multi-bit bus control signal input (28) connected to a fractional part multibit data bus (16) for a digital fractional part control signal (Df) , further comprising a clock signal input (50) connected to a clock signal line (25) for a clock signal (Clk) , as well as a reset signal input (51) connected to a reset signal line (26) for a reset signal (Rst) and a multi-bit bus control signal output (29) connected to a frequency modulator data bus (27) for a digitally modulated digital fractional part control signal (Dfm) , In circuit terms, the synchronously modulated fully digital delta-sigma modulator circuit has a certain number of, for example, four identically constructed but individually programmable digital signal generators (31) . (32) . (33) and (34) each having a multi-bit modulation data bus (36), (37), (38) and (39) with a digital modulation adder (35) which in turn are connected via the frequency modulator data bus (27) with the multi-bit bus control signal output (29) connected is.

Here is the synchronous frequency modulator circuit (24) configured so that the clock signal line (25) and the reset signal line (26) are connected such that all digital signal generators (31) . (32) . (33) and (34) simultaneously the same clock signal (Clk) and at the same time the same reset signal (Rst) and that both from the digital signal generator (31) generated digital output signal in the form of the data stream signal (Fm1) above a multi-bit modulation data bus (36) as well as the digital signal generator (32) generated digital output signal in the form of the data stream signal (Fm2) via a multi-bit modulation data bus (37) as well as the digital signal generator (33) generated digital output signal in the form of the data stream signal (FM3) via a multi-bit modulation data bus (38) as well as the digital signal generator (34) generated digital output signal in the form of the data stream signal (FM4) via a multi-bit modulation data bus (39) as well as the digital fractional part control signal (Df) via a fractional part multi-bit data bus (16) simultaneously and in common to the digital modulation adder (35) be supplied, which forms the synchronous super-balanced sum of all these mentioned signals as a desired output signal and thus then a digitally modulated digital decimal part control signal (Dfm) which, in place of the unmodulated digital decimal portion control signal (Df), is provided for further processing via the multi-bit bus control signal output (29) the following fully digital delta-sigma modulator circuit is provided.

In this case, the number of signal generators used in the synchronous frequency modulator circuit (24) initially exemplarily expedient but arbitrarily named four to discuss a concrete circuit example.

The number of digital signal generators used for the data stream signals in the synchronous frequency modulator circuit (24) can be either greater than or less than four, without significant principal operational penalty. In individual cases, this depends on the respective technical requirements or on the respective suppression signal frequencies to be suppressed in the output spectrum. However, if a different number of digital signal generators are used, then the respective synchronous frequency modulator circuit (24) be corresponding circuit technology adapted so that the described operation of the synchronous frequency modulator circuit (24) is ensured even for this changed number of digital signal generators used. So, for example, the number of inputs of the digital modulation adder (35) and the number of the multi-bit modulation data buses for the respective data stream signals are adjusted according to the number of digital signal generators.

The individual digital signal generators are designed identically in terms of circuitry and differ only in the digital data stored in them.

That is, the synchronously modulated full digital delta-sigma modulator circuit has a number of identically constructed digital signal generators for retrievable data stream signals. In order to be able to describe the details of the respective internal structure of such a digital signal generator exactly, it is therefore sufficient to select a single copy arbitrarily.

It is thus the identical but individually programmable digital signal generator (31) , described on behalf of all other digital signal generators.

In the digital signal generator (31) there is a counter module (41), via the clock signal line (25) the clock signal (Clk) and via the reset signal line (26) the reset signal (Rst) and a digital generator adder (42) , the digital signals over the internal data bus (46) from the counter module (41) and via the internal adder data bus (48) the counter module (41) and a function history data memory (43), the digital index signals (There) via the counter module data bus (45) receives and from these digital index signals (There) each retrieved values then as a respective digital output signal, in this case as a data stream signal (Fm1) via the multi-bit modulation data bus (36).

Furthermore, the digital signal generator has (31) a programmable incremental data memory (44) , the one selectable, pre-programmed increment value via the internal increment data bus (47) to the digital generator adder (42) forwards and a common interface input (40) as access for the programming data (DR) that has a programming data bus (49) is used for both the programmable increment data memory (44) and the function history data memory (43).

Here is the identical but individually programmable digital signal generator (31) configured so that the counter module (41) at each edge of the clock signal (Clk) on the clock signal line (25) is applied with a digital increment value, including the current counter value via the internal data bus (46) the digital generator adder (42) is supplied, which, via the internal increment data bus (47) supplied, the programmable incremental data memory (44) added, previously programmed increment value added and as a counter increment signal via the internal adder data bus (48) the counter module (41) provides, wherein the counter module (41) in a sequence determined by this procedure, numerical register addresses in the form of digital index signals (There) generated over the counter module data bus (45) the function history data memory (43) are supplied, which then from these digital index signals (There) respectively recalled, previously programmed and stored function history values, as the respective digital output signal, in the form of the data stream signal (Fm1) , via the multibit modulation data bus (36) and the digital modulation adder (35) supplies.

In order to reduce the circuit complexity, it is sufficient to use only the four highest significant data bits or another number of the highest significant data bits of the counter module to be sensibly selected (41) in the identical but individually programmable digital signal generator (31) to use it to numerical register addresses in the form of digital index signals (There) to be generated by means of the counter module data bus (45) the function history data store (43) and thereby reading the previously programmed and stored function history values as a respective digital output signal in the form of a data stream signal (fm1) via the multi-bit modulation data bus (36) to control.

In the function history datastore (43) The identical but individually programmable digital signal generator (31) stores, for example, the mathematical data values of a sinusoidal oscillation discretized at different times, each having individually and differently programmable values for the amplitude, the frequency and the phase angle. This will be the programming data (DR) both for the increment value data memory (44) and for the function history data memory (43) to a common interface input (40) and fed via a common programming data bus (49) supplied to the respective electronic components.

With the aid of the synchronously modulated, fully digital delta-sigma modulator circuit, it is then also possible, as already mentioned above, to construct a fractional-N PLL frequency synthesizer with very good signal quality.

This must then be a fully digital delta-sigma modulator circuit as electronic components (23) with an integrated divider adder (12) , a synchronous frequency modulator circuit (24) and a number divider circuit (11), which is arranged, the dividing ratio data (D) for the frequency-determining divider ratio of the frequency divider circuit (7) into a digital pre-commutation control signal (Di) and a digital post-commutation control signal (Df).

Here is the Zahlenaufteilerschaltung (11) connected to the all-digital delta-sigma modulator circuit (23) via the pre-commutation data bus (17) to apply the digital pre-commutation control signal (Di) to the divisor adder first of two control signals (12) supply.

The number divider circuit (11) is connected to the multi-bit bus control signal input (28) via the fractional-part multi bit data bus (16) for supplying the digital post-commander control signal (Df) to the synchronous frequency modulator circuit (24), the multi-bit bus control signal output (29) of the synchronous frequency modulator circuit (24). over the frequency modulator data bus (27) with the fully digital delta-sigma modulator circuit (23) is connected to the digitally modulated digital decimal-portion control signal (Dfm) as the second of two control signals after electronic processing by the digital delta-sigma inner modulator circuit (14) together with the digital input adder (13) and the associated data buses - also the divider adder (12) supply.

Furthermore, a frequency divider circuit (7) required with the divider adder (12) connected via the frequency divider data bus (21) to the output of the divider adder (12) as a control signal to receive, as well as a frequency stable oscillator circuit (1) connected to a reference frequency divider circuit (2) , which together form a reference signal circuit and a digital comparison signal (8th) provide a phase detector circuit (3) connected via a first input to the reference divider circuit (2) connected, a charge pump (4) , which is connected to the output of the phase detector circuit (3), a loop filter (5) connected to the output of the charge pump (4) is connected and a frequency-variable oscillator circuit (6) that with the loop filter (5) is connected and which is adapted to output a continuous high-frequency output signal (9) as a useful signal.

In this case, the fractional-N PLL frequency synthesizer is set up, the frequency divider circuit (7) one from the continuous high-frequency output signal (9) to supply the derived signal.

The frequency divider circuit (7) For its part, it has set up a digital reference signal (10) as a feedback signal to a second input of the phase detector circuit (3) supply.

With a fractional-N PLL frequency synthesizer constructed in this way, an almost complete symptomatic compensation of interference frequencies can then be achieved, which then increases with relatively little circuit complexity an extremely high quality of each generated signals leads.

LIST OF REFERENCE NUMBERS

(1)

Frequenzstabile Oszillatorschaltung

(2)

Referenzfrequenzteilerschaltung

(3)

Phasendetektor-Schaltung

(4)

Ladungspumpe

(5)

Schleifenfilter

(6)

Frequenzvariable Oszillatorschaltung

(7)

Frequenzteilerschaltung

(8)

Digitales Vergleichssignal

(9)

Kontinuierliches hochfrequentes Ausgangssignal

(10)

Digitales Bezugssignal

(11)

Zahlenaufteiler-Schaltung

(12)

Teileraddierer

(13)

Digitaler Eingangsaddierer

(14)

Digitale innere Delta-Sigma-Modulatorschaltung

(15)

Teilerverhältnis-Datenbus

(16)

Nachkommaanteil-Multibitdatenbus

(17)

Vorkommaanteil-Datenbus

(18)

Ausgangs-Datenbus

(19)

Teiler-Datenbus

(20)

Rückkopplungs-Datenbus

(21)

Frequenzteiler-Datenbus

(22)

Innerer Datenbus

(23)

Volldigitale Delta-Sigma-Modulatorschaltung

(24)

Synchrone Frequenzmodulatorschaltung

(25)

Taktsignalleitung

(26)

Rücksetzsignalleitung

(27)

Frequenzmodulator-Datenbus

(28)

Multibitbus-Steuersignaleingang

(29)

Multibitbus-Steuersignalausgang

(30)

Verzweigungstelle für das Taktsignal

(31)

Digitaler Signalgenerator für Datenstromsignal (fm1)

(32)

Digitaler Signalgenerator für Datenstromsignal (fm2)

(33)

Digitaler Signalgenerator für Datenstromsignal (fm3)

(34)

Digitaler Signalgenerator für Datenstromsignal (fm4)

(35)

Digitaler Modulationsaddierer

(36)

Multibit-Modulationsdatenbus für Datenstromsignal (fm1)

(37)

Multibit-Modulationsdatenbus für Datenstromsignal (fm2)

(38)

Multibit-Modulationsdatenbus für Datenstromsignal (fm3)

(39)

Multibit-Modulationsdatenbus für Datenstromsignal (fm4)

(40)

Gemeinsamer Schnittstelleneingang

(41)

Zählerbaustein

(42)

Generator-Addierer

(43)

Funktionsverlaufsdatenspeicher

(44)

Inkrementwertdatenspeicher

(45)

Zählerbaustein-Datenbus

(46)

Interner Datenbus

(47)

Interner Inkrement-Datenbus

(48)

Interner Addierer-Datenbus

(49)

Programmierdatenbus

(50)

Taktsignaleingang

(51)

Rücksetzsignaleingang

(Digits)

(1)

Frequency stable oscillator circuit

(2)

Reference frequency divider circuit

(3)

Phase detector circuit

(4)

charge pump

(5)

loop filter

(6)

Frequency-variable oscillator circuit

(7)

Frequency divider circuit

(8th)

Digital comparison signal

(9)

Continuous high-frequency output signal

(10)

Digital reference signal

(11)

Zahlenaufteiler circuit

(12)

Teileraddierer

(13)

Digital input adder

(14)

Digital inner delta-sigma modulator circuit

(15)

Division ratio data bus

(16)

Fractional-Multibitdatenbus

(17)

Integer part data bus

(18)

Output data bus

(19)

Divider data bus

(20)

Feedback data

(21)

Frequency divider data bus

(22)

Inner data bus

(23)

Fully digital delta-sigma modulator circuit

(24)

Synchronous frequency modulator circuit

(25)

Clock signal line

(26)

Reset signal line

(27)

Frequency modulator data bus

(28)

Multibitbus control signal input

(29)

Multibitbus control signal output

(30)

Branch point for the clock signal

(31)

Digital signal generator for data stream signal (fm1)

(32)

Digital signal generator for data stream signal (fm2)

(33)

Digital signal generator for data stream signal (fm3)

(34)

Digital signal generator for data stream signal (fm4)

(35)

Digital modulation adder

(36)

Multibit Modulation Data Bus for Data Stream Signal (fm1)

(37)

Multibit modulation data bus for data stream signal (fm2)

(38)

Multibit Modulation Data Bus for Data Stream Signal (fm3)

(39)

Multibit modulation data bus for data stream signal (fm4)

(40)

Common interface input

(41)

counters block

(42)

Generator adder

(43)

Function curve data storage

(44)

Inkrementwertdatenspeicher

(45)

Counter component data bus

(46)

Internal data bus

(47)

Internal increment data bus

(48)

Internal adder data bus

(49)

Programmierdatenbus

(50)

Clock signal input

(51)

Reset signal input

LIST OF REFERENCE NUMBERS

(clk)

Taktsignal

(D)

Teilerverhältnis-Daten

(Da)

Digitales Indexsignal

(Df)

Digitales Nachkommaanteil-Steuersignal

(Dfm)

Digital moduliertes digitales Nachkommaanteil-Steuersignal

(Dn)

Digitaler Zahlenwert

(Di)

Digitaler Vorkommaanteil-Steuersignal

(DR)

Programmierdaten

(fm1)

Datenstromsignal der Frequenzgeneratorschaltung (31)

(fm2)

Datenstromsignal der Frequenzgeneratorschaltung (32)

(fm3)

Datenstromsignal der Frequenzgeneratorschaltung (33)

(fm4)

Datenstromsignal der Frequenzgeneratorschaltung (34)

(N)

Teiler-Zahlenwert

(R)

Referenz-Zahlenwert

(rst)

Rücksetzsignal

(Letters)

(Clk)

clock signal

(D)

Divider ratio data

(There)

Digital index signal

(Df)

Digital fractional part control signal

(Dfm)

Digitally modulated digital fractional part control signal

(Dn)

Digital numeric value

(Di)

Digital precompression control signal

(DR)

programming data

(Fm1)

Data stream signal of the frequency generator circuit (31)

(Fm2)

Data stream signal of the frequency generator circuit (32)

(FM3)

Data stream signal of the frequency generator circuit (33)

(FM4)

Data stream signal of the frequency generator circuit (34)

(N)

Divider value

(R)

Reference value

(Rst)

Reset signal

Claims (9)

Synchronously modulated fully digital delta-sigma modulator circuit, comprising: a synchronous frequency modulator circuit (24) comprising a multibit bus control signal input (28) connected to a fractional part multibit data bus (16) for a digital postparticipate control signal (Df), a clock signal input (50) connected to a clock signal line (25) for a clock signal (clk), a reset signal input (51) connected to a reset signal line (26) for a reset signal (rst) and a multi-bit bus control signal output (29) connected to a frequency modulator data bus (27) for a digitally modulated digital post-commutation control signal (Dfm), and further comprising four identically but individually programmable digital signal generators (31), (32), (33) and (34), a digital modulation adder (35), connected in each case via a multi-bit modulation data bus (36), (37), (38) and (39) to all digital signal generators (31), (32), (33) and (34), which is connected to the multi-bit bus control signal output (29) via the frequency modulator data bus (27), and wherein the synchronous frequency modulator circuit (24) is configured such that - The clock signal line (25) and the reset signal line (26) are connected so that all digital signal generators (31), (32), (33) and (34) simultaneously the same clock signal (CLK) and simultaneously the same reset signal (RST) and that both - The digital output signal generated by the digital signal generator (31) as a data stream signal (fm1) via a multi-bit modulation data bus (36) as well the digital output signal generated by the digital signal generator (32) as a data stream signal (fm2) via a multi-bit modulation data bus (37) as well - The digital output signal generated by the digital signal generator (33) as a data stream signal (fm3) via a multi-bit modulation data bus (38) as well - The digital output signal generated by the digital signal generator (34) as a data stream signal (fm4) via a multi-bit modulation data bus (39) as well the digital fractional part control signal (Df) via a fractional part multi-bit data bus (16) are simultaneously and jointly supplied to the digital modulation adder (35), - Wherein this forms the synchronously clocked super-balanced sum of all of these above-mentioned signals and thus then provides a digitally modulated digital decimal fraction control signal (Dfm), which - Is provided for further processing via the multi-bit bus control signal output (29) of the subsequent fully digital delta-sigma modulator circuit instead of the unmodulated digital decimal portion control signal (Df). Synchronously modulated full digital delta-sigma modulator circuit after Claim 1 wherein the number of digital signal generators used in the synchronous frequency modulator circuit (24) is either greater than four, or less than four, and wherein the thus modified synchronous frequency modulator circuit comprises circuitry in providing one of the plurality of digital signal generators used corresponding number of multi-bit modulation data buses and a corresponding number of inputs for the digital modulation adder (35) is adapted so that the in Claim 1 described operation of the synchronous frequency modulator circuit (24) is ensured even for this changed number of digital signal generators used. Synchronously modulated fully digital delta-sigma modulator circuit, according to one of the preceding claims, wherein the structurally identical but individually programmable digital signal generator (31) comprises - a counter module (41), via the clock signal line (25) the clock signal (clk) and the reset signal line (26) the reset signal (rst) is supplied, - a digital generator adder (42) which receives digital signals via the internal data bus (46) from the counter module (41) and via the internal adder data bus (48) the counter module ( 41), - a function history data memory (43) which receives digital index signals (Da) via the counter module data bus (45) and retrieves the respective values retrieved from these digital index signals (Da) as a respective digital output signal in the form of a data stream signal (fm1) the multibit modulation data bus (36) outputs, - a programmable increment value data memory (44), the one selectable, previously ein programmed increment value via the internal increment data bus (47) to the digital generator adder (42) - a common interface input (40) as input for the programming data (DR), via a programming data bus (49) for both the programmable increment data memory ( 44) as well as the function history data memory (43) and wherein the structurally identical but individually programmable digital signal generator (31) is configured so that - the counter module (41) is acted upon on each edge of the clock signal (clk) on the clock signal line (25) with a digital increment value, including the current counter value is supplied via the internal data bus (46) to the digital generator adder (42) which adds the previously programmed incremental value taken from the internal incremental data bus (47) to the programmable incremental data memory (44) and as a counter increment Signal is provided to the counter module (41) via the internal adder data bus, wherein the counter module (41) generates numerical register addresses in the form of digital index signals (Da) in a sequence determined by this procedure, which are transmitted via the counter module data bus (45 ) are supplied to the function history data memory (43), which then - the of These respective digital index signals (Da) respectively output previously stored and stored function history values as a respective digital output signal in the form of a data stream signal (fm1) via the multi-bit modulation data bus (36) and the digital modulation adder (35) supplies. Synchronously modulated fully digital delta-sigma modulator circuit, according to Claim 3 in which only the four highest significant data bits or another sensibly selectable number of the highest significant data bits of the counter module (41) in the identically but individually programmable digital signal generator (31) are used to derive numerical register addresses in the form of digital index signals (Da ), which are supplied to the function history data memory (43) by means of the counter module data bus (45) and thereby read out the previously programmed and stored function history values as a respective digital output signal in the form of a data stream signal (fm1) via the multi-bit modulation data bus (36). Taxes. Synchronously modulated fully digital delta-sigma modulator circuit, according to Claim 3 in which the mathematical data values of a sinusoidal oscillation discretized at different times are stored in the functional course data memory (43) in the identical but individually programmable digital signal generator (31) with programmable values for the amplitude, the frequency and the phase angle. Synchronously modulated fully digital delta-sigma modulator circuit, according to Claim 3 , - wherein the programming data (DR) for both the incremental data memory (44) and the function history data memory (43) at a common interface input (40) and fed via a common programming data bus (49) the respective electronic components. Fractional-N PLL frequency synthesizer comprising a synchronously modulated fully digital delta-sigma modulator circuit according to any one of Claims 1 to 6 - a fully digital delta-sigma modulator circuit (23) with an integrated divider adder (12) - a synchronous frequency modulator circuit (24) - a numeric divider circuit (11), which is arranged, the dividing ratio data (D) for the frequency-determining divider ratio the frequency divider circuit (7) into a digital Vorkommaanteil control signal (Di) and a digital decimal portion control signal (Df) to divide - the numerical divider circuit (11) via the Vorkommaanteil data bus (17) with the fully digital delta-sigma modulator circuit (23) is connected to directly supply the digital pre-mate control signal (Di) to the divisor adder (12) as first of two control signals, and - the divider circuit (11) via the fractional-part multi-bit data bus (16) to the multi-bit bus control signal input (28) is connected to supply the digital decimal portion control signal (Df) to the synchronous frequency modulator circuit (24), the Mul tibitbus control signal output (29) of the synchronous frequency modulator circuit (24) is connected to the all-digital delta-sigma modulator circuit (23) via the frequency modulator data bus (27) to provide the digitally modulated digital fractional part control signal (Dfm) as the second of two control signals - after electronic processing by the digital delta-sigma inner modulator circuit (14) with the digital input adder (13) and the associated data buses - also to the divider adder (12), - a frequency divider circuit (7) connected to the divider adder (12 ) is connected via the frequency divider data bus (21) in order to receive the output signal of the divider adder (12) as a control signal, - a frequency-stable oscillator circuit (1) connected to a reference frequency divider circuit (2) which together form a reference signal circuit and a digital comparison signal ( 8), - a phase detector circuit (3) connected via a first input a charge pump (4) connected to the output of the phase detector circuit (3), a loop filter (5) connected to the output of the charge pump (4), a frequency-variable oscillator circuit (6) connected to the loop filter (5) and arranged to output a continuous high-frequency output signal (9) as a useful signal, - the fractional-N PLL frequency synthesizer being arranged, - the frequency divider circuit (7 ) supply a signal derived from the continuous high-frequency output signal (9) and - the frequency divider circuit (7) is arranged to supply a digital reference signal (10) as a feedback signal to a second input of the phase detector circuit (3). A method of modifying the output of a fully digital delta-sigma modulator circuit, comprising: Digitally storing mathematical data values of numerous discretized sinusoidal oscillations each having different amplitudes, different frequencies and different zero phase angles at different times, - Each individual discretized sinusoidal oscillation receives an individual memory address and providing these values in a function history data memory (43), their respective memory contents - By the supply of a digital index number (Da), whose value is varied continuously after each reading of the full memory contents by a random number generator circuit, and - Controlled by both a clock signal (clk) and by a reset signal (rst) is clocked out synchronously. Generating a modification signal by a clock-synchronized to the clock signal and the reset signal reading out of programmed mathematical data values of at least one or more than one at each time discrete discrete sinusoidal vibration and - Addition of these digital numerical values to the digital numerical values of an unmodified input signal - wherein the generation of the modification signal comprises modifying the output signal of the fully digital delta-sigma modulator circuit by supplying the thus modulated input signal - instead of the unmodified input signal A method of controlling a fractional-N PLL frequency synthesizer, comprising: - the method of modifying the output signal of a fully digital delta-sigma modulator circuit Claim 8 in which the control signals are the digital post-commander control signal (Df) and the digital post-commutation control signal (Di) corresponding to the divider ratio according to the predetermined divider ratio data (D), and wherein the frequency divider circuit (7) of the fractional-N PLL Frequency synthesizer is controlled by the resulting modification signal.

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