US20110133797A1 - Novel method of frequency synthesis for fast switching - Google Patents

Novel method of frequency synthesis for fast switching Download PDF

Info

Publication number
US20110133797A1
US20110133797A1 US13/028,049 US201113028049A US2011133797A1 US 20110133797 A1 US20110133797 A1 US 20110133797A1 US 201113028049 A US201113028049 A US 201113028049A US 2011133797 A1 US2011133797 A1 US 2011133797A1
Authority
US
United States
Prior art keywords
signal
input
frequency synthesizer
frequency
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/028,049
Inventor
Kartik M. Sridharan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orca Systems Inc
Original Assignee
Orca Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US11/321,110 priority Critical patent/US7482885B2/en
Priority to US12/334,359 priority patent/US7898345B2/en
Application filed by Orca Systems Inc filed Critical Orca Systems Inc
Priority to US13/028,049 priority patent/US20110133797A1/en
Assigned to ORCA SYSTEMS, INC. reassignment ORCA SYSTEMS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SRIDHARAN, KARTIK M.
Publication of US20110133797A1 publication Critical patent/US20110133797A1/en
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/02Digital function generators
    • G06F1/022Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/602Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using delta-sigma sequences
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K21/00Details of pulse counters or frequency dividers

Abstract

A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL).

Description

    CROSS-REFERENCE TO RELATED PATENT APPLICATIONS
  • The present application claims the benefit of and priority to and is a Divisional of U.S. application Serial No. 12/334,359, filed on Dec. 12, 2008, entitled “A NOVEL METHOD OF FREQUENCY SYNTHESIS FOR FAST SWITCHING” by Sridharan, which is a Continuation of U.S. application Serial No. 11/321,110, filed on Dec. 29, 2005, entitled “A Novel Method of Frequency Synthesis for Fast Switching” by Sridharan, both applications are incorporated herein by reference in its entirety.
  • BACKGROUND OF THE INVENTION
  • The present application generally relates to communication circuits and systems and more specifically to frequency synthesizers using a novel open-loop generation method. More particularly, the present application relates to frequency synthesizers capable of fast switching, frequency synthesizers capable of providing precise, high frequency clock references, and/or frequency synthesizers for use in communication equipment.
  • According to one particular application, radio frequency (RF) signal generation in mobile communication equipment, frequency synthesizers are utilized to provide a frequency source for a number of communication channels. In general, conventional frequency synthesizers have employed integer or fractional phase locked loops (PLLs) to generate a frequency signal. These conventional frequency synthesizers (PLL-based frequency synthesizers) utilize a phase locked loop comprised of a loop filter, a comparator circuit, and a voltage controlled oscillator. These conventional PLL-based frequency synthesizers also have used dithering, and delta-sigma dithering methods to generate the fractional frequencies.
  • The oscillator has a control input coupled to the loop filter. The output of the comparator circuit is coupled to the loop filter. A first input of the comparator circuit is coupled to an integer divider and a delta-sigma averaging circuit. A second input of the comparator circuit is coupled to a reference signal. The combination of the integer divider and the delta-sigma averaging circuit constitute a fractional divider. The reference frequency signal can be generated from a crystal or other device. A delta-sigma fractional synthesizer is disclosed in U.S. Pat. No. 4,609,881 issued to Wells on Sep. 2, 1986.
  • Generally, such PLL-based frequency synthesizers are disadvantageous because they cannot be readily integrated on digital integrated circuits (ICs or chips). PLL-based frequency synthesizers require more expensive process technologies and are not compatible with the same CMOS technology that is used for base band and other digital control circuitry. As process technologies shrink in size, it becomes even more desirous to provide a radio architecture which is compatible with CMOS processes. U.S. Patent Publication No. 2004/0066240 discusses certain advantages of migrating to digitally intensive synthesizer architectures.
  • In communication applications, the frequency synthesizer must often be capable of producing precise, high frequency clock references. Heretofore, most conventional synthesizers have utilized analog intensive designs to achieve precise, high frequency clock references. These conventional analog designs cannot take advantage of the digital processing capability inherent in advanced CMOS logic devices.
  • Therefore, there is a need for a frequency synthesizer that is more compatible with digital designs. Further still, there is a need for a synthesizer that does not utilize a conventional PLL-based design. Further still, there is a need to integrate frequency synthesizers into CMOS logic devices. Further still, there is a need for a frequency synthesizer capable of fast switching which does not have the traditional problems associated with analog-intensive designs. Yet further still, there is a need for a digital frequency synthesizer capable of producing precise high frequency clock signals.
  • SUMMARY OF THE INVENTION
  • An exemplary embodiment relates to a digital frequency synthesizer. The digital frequency synthesizer includes a frequency multiplier coupled to at least one source for providing a digital frequency signal. The frequency multiplier is configured to receive the digital frequency signal at a second multiplier input and to provide a multiplier output. A delta signal modulator is configured to receive a fractional input and to provide a modulator output. The modulator output is a sequence of integers whose average represents the fractional input. The delta signal modulator includes a clock input for receiving a clock signal. The clock signal is the multiplier output signal or is derived from the multiplier output signal. A summer circuit is configured to receive the modulator output from the delta signal modulator and an integer input and to provide a summer output. The summer output is provided as the second multiplier input to the frequency multiplier.
  • Another exemplary embodiment relates to a frequency synthesizer. The frequency synthesizer includes an operator receiving a first signal at a first operator input and a sum signal at a second operator input. The operator provides an output signal at a first output. The operator is a divider or a multiplier. A summer receives a modulator signal at a first input and an integer signal at a second input and provides the sum signal at a summer output. The modulator provides the modulator signal and receives a fraction signal at a fraction input.
  • Still another exemplary embodiment relates to a frequency synthesizer including an operator receiving a sum signal and a clock signal and providing an output signal and a control circuit providing a first signal in response to a fraction signal. A summer provides the sum signal in response to the first signal in the frequency input.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Preferred exemplary embodiment will hereinafter be described in conjunction with the appended drawings, wherein like numerals denote like elements and:
  • FIG. 1 is an electrical schematic block diagram of a digital frequency synthesizer in accordance with an exemplary embodiment;
  • FIG. 2 is a more detailed block diagram of the controller illustrated in FIG. 1 in accordance with another exemplary embodiment;
  • FIG. 3 is a waveform diagram of two waveforms associated with the synthesizer illustrated in FIG. 1 in accordance with an exemplary embodiment;
  • FIG. 4 is a waveform diagram of two waveforms associated with the synthesizer illustrated in FIG. 1 in accordance with yet another exemplary embodiment;
  • FIG. 5 is an electrical schematic block diagram of a digital frequency synthesizer in accordance with yet another exemplary embodiment;
  • FIG. 6 is an electrical schematic block diagram of a frequency synthesizer in accordance with still another exemplary embodiment;
  • FIG. 7 is an electrical schematic block diagram of a frequency synthesizer and a PLL circuit for cleaning output signals provided by the frequency synthesizers illustrated in any of FIG. 1, 4, or 5 in accordance with still yet another exemplary embodiment; and
  • FIG. 8 is an electrical schematic block diagram of a digital frequency synthesizer in accordance with an exemplary embodiment.
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • With reference to FIG. 1, a digital frequency synthesizer 10 can be utilized in any application requiring the generation of a frequency signal, such as, a high frequency signal. Preferably, frequency synthesizer 10 is a non-phase locked loop (PLL) based synthesizer that can be utilized in communication applications, such as, wireless communication applications (e.g., cellular phone applications). Synthesizer 10 includes a number of frequency sources 12A-D, a controller 16, and switches 14A-D. In one embodiment, synthesizer 10 is used for modulation (e.g., wideband modulation). An exemplary embodiment relates to a digital frequency synthesizer. The digital frequency synthesizer includes at least one source for providing a plurality of digital frequency signals, a plurality of switches, and a control circuit. Each of the digital frequency signals is provided at a distinct frequency. The switches are coupled to receive the digital frequency signals. The control circuit is coupled to the switches and controls the switches to select the digital frequency signals to provide an output signal.
  • According to one embodiment, the output frequency is the average of the digital frequency sources—as determined by a dithering sequence. For example, if Tone 1 is 890 MHz and Tone 2 is 900 MHz, and if the dithering sequence is Tonel, Tone2, Tonel, Tone2 . . . , then the output frequency is 895 MHz. As another example, if the dithering sequence is Tonel, Tonel, Tonel, Tone2,...., then the output frequency is 892.5 MHz. Thus, the dithering sequence and the tone frequencies determine the final output frequency. This dithering sequence can be performed by a control circuit embodied as a sigma delta modulator, or any other dithering sequence generator. An exemplary structure for a dithering sequence generator is in U.S. Pat. No. 4,609,881.
  • Another exemplary embodiment relates to a digital frequency synthesizer. The digital frequency synthesizer includes a frequency multiplier, a delta-sigma or other dithering circuit, and a fractional input. The frequency multiplier has a clock input, a second input, and a multiplier output. The multiplier receives a clock signal at the clock input and provides a frequency signal at the multiplier output that is the input clock frequency times the multiplication number as set by the second input. The delta-sigma or other dithering circuit has a dithering output that provides a signal representing an “integer+fraction” for the desired multiplication. The delta-sigma/dithering output is coupled to the second input. The fractional input is coupled to the delta-sigma or other dithering circuit input. The fractional input provides an input signal that represents the fraction factor by which one wants the input clock frequency to be multiplied.
  • Still another exemplary embodiment relates to a digital frequency synthesizer. The digital frequency synthesizer includes a frequency source for providing a first signal at a first frequency, a frequency multiplier for receiving the first signal and providing a second signal at a second frequency, and a variable frequency divider. The digital frequency synthesizer also includes a delta-sigma modulator or any other dithering circuit. The second frequency is at a fixed multiple of the first frequency. The frequency divider receives the second signal and provides a third signal having an average third frequency. The average third frequency is less than the second frequency. The delta- sigma modulator or other dithering circuit controls the divider so that the third frequency is the average of a dithering sequence from the dithering circuit.
  • An exemplary embodiment relates to a signal source. The signal source includes a digital frequency synthesizer for providing a frequency signal and a phase lock loop clean-up circuit. The phase lock loop clean-up circuit is coupled to receive the frequency signal and provide a clean-up frequency signal. The digital frequency synthesizer can utilize: 1. at least one digital frequency source, switches and a dithering control circuit controlling the switches; 2. a frequency multiplier and a dithering circuit coupled to the multiplier to provide an output signal at a frequency related to an integer plus a fraction; 3. a single digital frequency source capable of providing a sequence of frequency signals at distinct frequencies; or 4. a frequency multiple and variable frequency divider.
  • Another exemplary embodiment relates to a digital frequency synthesizer including at least one digital frequency source for providing a plurality of digital frequency signals and a control circuit. The digital frequency signals are provided at distinct frequencies. The control circuit controls the digital frequency source to provide an output signal having an average frequency at a first frequency. The average frequency being within a range of the distinct frequencies.
  • Preferably, sources 12A-D and switches 14A-D are in a one-to-one relationship. The number of sources 12A-D can be any number from two to n, and the number of switches 14A-D can be any number from two to n. Preferably, at least 2 number of sources 12A-D and switches 14A-D are utilized depending upon application parameters and system criteria. Switches 14A-D are preferably solid-state switches such as CMOS devices. Switches 14A-D can also be implemented as a multiplexer.
  • Frequency sources 12A-D have outputs coupled to each of switches 14A-D. Switches 14A-D have an output coupled to output 18 which is coupled to controller 16. Controller 16 has an output coupled to a control input of each of switches 14A-D via control lines 14A-D.
  • Sources 12A-D can be implemented as any type of frequency sources such as integer or fractional PLLs, Clock multipliers, or multiplying DLLs. In one preferred embodiment, sources 12A-D are digital delay locked loops (DLLS). Digital delay locked loops can be implemented as conventional DLLs.
  • In one alternative embodiment, frequency sources 12A-D are implemented by one delay locked loop with a programmable multiplier. This is a preferred implementation since one can recognize from FIG. 1 that when a particular switch is on, all the other switches are off. As an example, if switch 14A connected to source 12A is on, then switches 14B, 14C, 14D are all off. This means that the sources 12B, 12C, and 12D need not be on. Thus, the amount of hardware in the implementation may be reduced considerably by implementing a single frequency agile source which can generate signals associated with sources 12A, 12B, 12C, 12D as needed and as determined by the switches 14A to 14D.
  • In an alternative embodiment (FIG. 8), frequency synthesizer 500 includes, a single frequency source structure 502 (e.g., single source), such as, a multiplying DLL (integer or fractional). Source 502 provides the signals associated with sources 12A-D. In this embodiment, switches 14A-D are not necessary. A controller 526, similar to controller 16 described in more detail below can be utilized to cause structure 502 of synthesizer 500 to provide the appropriate sequence of signals. The sequence of signals preferably have an average frequency within the range of the signals provided by source 502. Controller 526 can receive a fraction value at input 528.
  • In operation, frequency sources 12A-D advantageously provide a set of n precise frequency signals. The desired frequency for a signal at output 18 is somewhere within the set of n precise frequencies. The desired frequency is variable and can change to any frequency within the set of n precise frequencies. For example, the desired frequency can be 905 MHz and frequencies from sources 12A-D can be 890 MHz , 900 MHz, 910 MHz, and 920 MHz, respectively. As another example, if the desired frequency is 905 MHz, then the set of sources of 902 MHz, 904 MHz, 906 MHz, 908 MHz with the appropriate dithering between them will also result in 905 MHz.
  • The advantage of placing the tones closer to each other is that the resulting output phase noise, or jitter is considerably reduced. The tones can be spaced equally apart from neighboring tones in one embodiment. In another embodiment, the tones are not spaced apart equally from neighboring tones.
  • Controller 16 preferably controls individual switches of switches 14A-D over time so that the output signal with the desired frequency is provided at output 18. Controller 16 can receive a fraction factor from a fraction input 15. The fraction factor is used by controller 16 to control switches 14A-D to obtain the desired frequency. Controller 16 advantageously chooses the appropriate combination of frequency sources 12A-D over time via control lines 14A-D so that the desired frequency is obtained. Preferably, synthesizer 10 operates as essentially a variable clock signal source which jitters around the desired frequency as shown in FIGS. 3 and 4.
  • Synthesizer 10 can be a frequency synthesizer for use in a cellular phone. Synthesizer 10 advantageously allows very fast switching between frequencies and avoids the disadvantages associated with feedback loops. The rate of switching between switches 14A-D can be at a relatively low rate, e.g., at crystal frequency. Alternatively, output 18 can be coupled to controller 16 as in FIG. 1 to provide a much higher switching rate. Applicants believe that a faster switching rate for controller 16 and hence switches 14A-D results in a reduced noise floor. A frequency divider can be disposed between the output 18 and the controller 16 in order to reduce the rate at which controller 16 operates.
  • Fraction input 23 provides controller 16 the appropriate fraction for providing the desired frequency at output 18. Input 23 is similar to input 15 (FIG. 1). The fraction can be provided by a variety of circuits, controllers, etc. Controller 16 generates the appropriate sequence on outputs 20A, 20B, 20C, and 20D to achieve the frequency associated with the fraction (e.g., integer+fraction) provided by fraction input 23. Advantageously, synthesizer 10 can have a very high bandwidth due to the lack of the feedback loop.
  • Synthesizer 10 can operate as an open loop system without the use of feedback loops as in a standard PLL implementation. Synthesizer 10 preferably operates as a completely digital frequency source and is capable of being integrated in an all digital CMOS process. This feature in addition to the relatively small die size required for synthesizer 10 makes it very attractive for digital and analog integration.
  • With reference to FIG. 2, according to one preferred embodiment, controller 16 is implemented as a delta-sigma modulator or other dithering circuit. The delta-sigma modulator receives an indication of the desired frequency and provides a sequence of signals on control lines 14A-D to effect generation of the desired frequency signal.
  • An exemplary implementation of the delta-sigma modulator is in U.S. Pat. No. 4,609,881. The output of the delta-sigma modulator (or any dithering circuit) is a sequence of numbers that change at the clock rate. The input of the delta-sigma modulator (or any dithering circuit) is a fraction—for example, 0.3333. The property of the delta-sigma modulator (or any dithering circuit) is that the average of the sequence will be the input fraction. Note that the output is preferably integer numbers. Frequency dividers or multipliers generally can be made only as integer dividers or multipliers. In the example of the input being 0.3333, the output sequence can be 0, 2, -1, 1, 0, 0, -2, 3, 0, and so on. Note that the average of the sequence is 0.3333. Another property of the delta- sigma modulator is that the sequence repeats only after a very long period. Thus, we obtain a pseudo-random source and the jitter or noise at the output will not have spurious tones (since these spurious tones are caused by any periodic repetition in the dithering sequence).
  • Controller 16 can be implemented as a delta-sigma modulator using standard architecture implemented on a CMOS process. Applicants believe that synthesizer 10 advantageously splits up the two functions associated with the conventional fractional-N PLL circuit (the two functions are that of tone generation, and noise filtering). The architecture for synthesizer 10 uses digital implementation for frequency selection and uses a PLL for filtering of the output signal. This can also be viewed as a jitter removal circuit or clean-up PLL. This clean-up PLL may not be required in all applications. Applicants believe that only applications with very stringent phase noise requirements will require the clean-up PLL. Clean-up phase locked loop 34 is discussed with reference to FIG. 7. This division of two functions associated with a conventional PLL-base synthesizer advantageously reduces the power requirements and allows the use of digital circuitry for frequency synthesizer 10.
  • With reference to FIG. 3, synthesizer 10 provides an output signal 202. Output signal 202 can be frequency averaged to provide output signal 206, if necessary for the specific application. The averaging of the frequency of the signal 202 can be performed utilizing a clean up phase locked loop such as clean up phase locked loop 348 discussed with reference to FIG. 7.
  • Signal 202 is generated by selecting frequency sources 12A-D. As can be seen in the example, signal 202 has 8 pulses across the same time that signal 206 has 8 pulses. However, the pulses of signal 202 do not have the same period between them.
  • Signal 202 has pulse widths (or, equivalently, pulse frequency) that can be switched at each pulse. In this embodiment, the frequency of signal 202 can be changed on a pulse-by-pulse basis. Alternatively, controller 16 can control switches 14A-D at every nth pulse of the output clock.
  • With reference to FIG. 4, signal 208 represents the signal at output 18. Signal 208 is provided in a synthesizer 10 configured so that controller 16 only selects switches 14A-D every 5 pulses, as an example. Signal 210 is an average or cleaned up version of signal 208 using phase locked loop 348 (FIG. 7).
  • With reference to FIG. 5, a digital frequency synthesizer 300 is similar to digital frequency synthesizer 10 and achieves similar advantages. Synthesizer 300 can be utilized to generate signals 202 and 208.
  • Synthesizer 300 includes a clock frequency multiplier 306, a dithering circuit (e.g., delta-sigma modulator 302), and a fractional input 304. Multiplier 306 receives a reference signal (CLK) at an input. The reference signal can be provided from any frequency source, such as a DLL, crystal oscillator circuit, etc. Multiplier 306 also includes an input for receiving a signal from a dithering circuit or (e.g., delta-sigma modulator 302). Dithering circuit or modulator 302 provides a signal to multiplier 306 through sum circuit 307. Sum circuit 307 receives an integer from integer input 309.
  • Sum circuit 307 adds the integer from input 309 to the fractional value from modulator 302. The integer is a suitable stable integer number so that the desired frequency output signal is provided at its output. In this implementation, the dithering circuit or delta sigma modulator 302 provides a sequence of integer numbers whose average represents the fraction provided by input 304. Each number in the sequence is added to the integer number which is then fed as input the clock frequency multiplier 306.
  • Multiplier 306 preferably functions in the following way: the output frequency is a multiple of the input clock frequency. The multiple is determined by the second input of the multiplier 306. For example, if the clock frequency is 7 MHz and the multiplication number is 100, then the output frequency is 7*100=700 MHz. If this number keeps on varying for each output pulse (or at a slower rate, but still related to the output pulse), then synthesizer 300 is able to generate the signals 202 or 208. Dithering/delta-sigma modulator circuits are discussed in more detail above with reference to FIG. 2.
  • Dithering circuit or delta-sigma modulator 302 can be clocked by the output signal from multiplier 306 or via an external clock signal. A fraction input 304 provides the appropriate fractional input for delta-sigma modulator 302.
  • With reference to FIG. 6, a frequency synthesizer 318 is similar to synthesizer 10 and can achieve similar advantages. Synthesizer 318 includes a frequency source 322, such as a crystal oscillator circuit. Synthesizer 318 also includes a frequency multiplier 326, a dithering circuit or delta-sigma modulator 320, a fractional input 321 and a frequency divider (or counter) 328. Synthesizer 318 also can include an integer input 329 and a sum circuit 327. Divider 328 provides an output signal at a desired frequency. Dithering circuit (e.g., delta-sigma modulator 320) is coupled to divider 328 through sum circuit 327. Sum circuit adds the fractional output from modulator 320 to the integer from input 329.
  • Dithering circuit/delta-sigma modulator 320 controls divider 328 so that divider 328 provides the output signal at the desired frequency. Preferably, multiplier 326 is an integer multiplier. For example, if the required output frequency is 900 MHz, then in one implementation, the multiplier 326 preferably multiplies the signal from crystal 322 to a very high frequency such as approximately 9 GHz.
  • Divider 328 divides the signal down to a desired frequency such as 905 MHz. This is accomplished by dithering (or delta-sigma modulating) the divider input so that the desired frequency and jitter is present at the output. The functionality is very similar to synthesizer 300 (described above), except for the fact that a clock multiplier is used to generate the signals 202 or 208, while in synthesizer 318, a frequency divider is used to generate signals 202 or 208.
  • In one embodiment, multiplier 326 is a fixed multiplier and divider 328 is a variable divider controlled by a dithering circuit (e.g., delta-sigma modulator 320). Modulator 320 receives a signal to set the division for divider 328 from circuit 321.
  • With reference to FIG. 7, digital frequency synthesizer 352 can be coupled to clean-up synthesizer or phase locked loop 348. This clean-up synthesizer may be required to remove the jitter inherently present in synthesizers 10, 300, or 318. Synthesizer 352 can be implemented as any of synthesizers 10, 300 or 318. Synthesizer 352 provides a signal to phase locked loop 348. Phase locked loop 348 is a clean up phase locked loop for removing jitter and changing waveform 202 to 206 or 208 to 210. (FIGS. 3 and 4).
  • Phase locked loop 348 includes a Phase detector/Phase-frequency detector, or mixer 360, a voltage controller oscillator 362, a loop filter 361 and an integer divider 350. The use of integer divider 350 as opposed to a fractional divider provides easier implementation. Note that the integer division may be a division of 1. For this case, no physical circuit is needed since the input and output frequencies are the same. For systems, like Global System for Mobile Communications (GSM) where phase noise or jitter requirements are very difficult to achieve, loop 348 can be very advantageous. Other systems may not require loop 348. This separation of functions (filtering and fractional signal generation) allows digital implementation integrated in CMOS.
  • Applicants believe that the architecture of synthesizers 10, 300 and 318 allows them to be made much less expensively than a conventional PLL system. Applicants believe that synthesizers 10, 300 or 318 have lower power consumption than a conventional PLL and are completely digital and more resistant to switching noise. Modulation can be very effectively performed since the method is effectively open looped and there are fewer loop stability considerations. Applicants believe that synthesizer 10 provides better phase noise or jitter performance. Applicants believe that synthesizer 300 and 318 provide easier implementation at a reduced power consumption.
  • It is understood that, while the detailed drawings, specific examples, and particular component values given describe preferred exemplary embodiments of the present invention, they serve the purpose of illustration only. The apparatus and method of the invention is not limited to the precise details and conditions disclosed. Further, although particular types of frequency sources are discussed, various other components could be utilized for the digital frequency synthesizer. Other substitutions, modifications, changes, and omissions may be made in the design, operating conditions, and arrangement of the preferred embodiments without departing from the spirit of the invention as expressed in the appended claims.

Claims (20)

1. A digital frequency synthesizer, comprising:
a frequency multiplier coupled to at least one source for providing a digital frequency signal, wherein the frequency multiplier is configured to receive the digital frequency signal and a second multiplier input and to provide a multiplier output;
a delta sigma modulator configured to receive a fractional input and to provide a modulator output, wherein the modulator output is a sequence of integers whose average represents the fractional input, wherein the delta sigma modulator includes a clock input for receiving a clock signal, wherein the clock signal is the multiplier output signal or is derived from the multiplier output signal; and
a summer circuit configured to receive the modulator output from the delta sigma modulator and an integer input and to provide a summer output, wherein the summer output is provided as the second multiplier input to the frequency multiplier.
2. The digital frequency synthesizer of claim 1, wherein the sequence of integers whose average represents the fractional input are all added to the integer input to generate the summer output.
3. The digital frequency synthesizer of claim 1, wherein the digital synthesizer is utilized in a wireless communication device.
4. The digital frequency synthesizer of claim 1, wherein wideband modulation is obtained.
5. The digital frequency synthesizer of claim 1, wherein the multiplier output signal is provided to a clean-up phase locked loop.
6. The digital frequency synthesizer of claim 1, wherein the digital frequency synthesizer is entirely integrated on at least one of a CMOS, bi-CMOS, silicon germanium, gallium arsenide device.
7. A frequency synthesizer, comprising:
an operator receiving a first signal at a first operator input and a sum signal at a second operator input and providing an output signal at a first output, wherein the operator is a divider or multiplier;
a summer receiving a modulator signal at a first input and an integer signal at a second summer input and providing the sum signal at a summer output; and
a modulator providing the modulator signal and receiving a fraction signal at a fraction input.
8. The frequency synthesizer of claim 7, wherein the modulator is a delta- sigma modulator.
9. The frequency synthesizer of claim 7, wherein wideband modulation is obtained.
10. The frequency synthesizer of claim 7, further comprising:
providing the output signal to a clean-up phase locked loop.
11. The frequency synthesizer of claim 7, wherein the operator is a multiplier and the output signal is coupled to a clock input of the modulator.
12. The frequency synthesizer of claim 11, wherein the modulator is a delta-sigma modulator.
13. The frequency synthesizer of claim 7, wherein the operator is a divider.
14. The digital frequency synthesizer of claim 13, wherein a multiplier is coupled to the first input.
15. A digital frequency synthesizer, comprising:
an operator receiving a sum signal and a clock signal and providing an output signal;
a control circuit providing a first signal in response to a fraction signal; and
a summer providing the sum signal in response to the first signal and frequency input.
16. The digital frequency synthesizer of claim 15, wherein the control circuit includes a dithering circuit.
17. The digital frequency synthesizer of claim 16, wherein the control comprises a delta-sigma modulator.
18. The digital frequency synthesizer of claim 17, wherein wideband modulation is achieved.
19. The digital frequency synthesizer of claim 15, wherein the operator is a multiplier.
20. The digital frequency synthesizer of claim 15, wherein output signal is provided as a clock input to the control circuit.
US13/028,049 2005-12-29 2011-02-15 Novel method of frequency synthesis for fast switching Abandoned US20110133797A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US11/321,110 US7482885B2 (en) 2005-12-29 2005-12-29 Method of frequency synthesis for fast switching
US12/334,359 US7898345B2 (en) 2005-12-29 2008-12-12 Method of frequency synthesis for fast switching
US13/028,049 US20110133797A1 (en) 2005-12-29 2011-02-15 Novel method of frequency synthesis for fast switching

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/028,049 US20110133797A1 (en) 2005-12-29 2011-02-15 Novel method of frequency synthesis for fast switching

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/334,359 Division US7898345B2 (en) 2005-12-29 2008-12-12 Method of frequency synthesis for fast switching

Publications (1)

Publication Number Publication Date
US20110133797A1 true US20110133797A1 (en) 2011-06-09

Family

ID=38223729

Family Applications (3)

Application Number Title Priority Date Filing Date
US11/321,110 Active US7482885B2 (en) 2005-12-29 2005-12-29 Method of frequency synthesis for fast switching
US12/334,359 Active 2026-02-08 US7898345B2 (en) 2005-12-29 2008-12-12 Method of frequency synthesis for fast switching
US13/028,049 Abandoned US20110133797A1 (en) 2005-12-29 2011-02-15 Novel method of frequency synthesis for fast switching

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US11/321,110 Active US7482885B2 (en) 2005-12-29 2005-12-29 Method of frequency synthesis for fast switching
US12/334,359 Active 2026-02-08 US7898345B2 (en) 2005-12-29 2008-12-12 Method of frequency synthesis for fast switching

Country Status (5)

Country Link
US (3) US7482885B2 (en)
EP (1) EP1969725B1 (en)
JP (1) JP5165585B2 (en)
KR (1) KR20080096526A (en)
WO (1) WO2007079098A2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011120769A1 (en) 2011-12-10 2013-06-13 Imst Gmbh Synchronous modulated-fully digital delta-sigma modulator circuit for use in fractional N-phase locked loop frequency synthesizer, has digital un-modulated fractional-control signal processing full-digital delta-sigma modulator circuit
US20150171918A1 (en) * 2013-12-17 2015-06-18 National Applied Research Laboratories Spread spectrum clock generator and method for generating spread spectrum clock signal
CN106301357A (en) * 2016-07-25 2017-01-04 南方科技大学 All-digital phase-locked loop

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7482885B2 (en) * 2005-12-29 2009-01-27 Orca Systems, Inc. Method of frequency synthesis for fast switching
US7519349B2 (en) * 2006-02-17 2009-04-14 Orca Systems, Inc. Transceiver development in VHF/UHF/GSM/GPS/bluetooth/cordless telephones
US20080021944A1 (en) * 2006-07-20 2008-01-24 Texas Instruments Incorporated Method and apparatus for reducing jitter in output signals from a frequency synthesizer using a control word having a fractional bit
KR100819390B1 (en) * 2006-09-21 2008-04-04 지씨티 세미컨덕터 인코포레이티드 Frequency synthesizer using two phase locked loop
FR2918820B1 (en) * 2007-07-12 2009-11-27 St Microelectronics Sa Device for providing an alternating signal.
US8059706B2 (en) * 2007-09-24 2011-11-15 Broadcom Corporation Method and system for transmission and/or reception of signals utilizing a delay circuit and DDFS
US7929929B2 (en) * 2007-09-25 2011-04-19 Motorola Solutions, Inc. Method and apparatus for spur reduction in a frequency synthesizer
US7911247B2 (en) * 2008-02-26 2011-03-22 Qualcomm Incorporated Delta-sigma modulator clock dithering in a fractional-N phase-locked loop
US8044742B2 (en) 2009-03-11 2011-10-25 Qualcomm Incorporated Wideband phase modulator
JP5229081B2 (en) * 2009-04-10 2013-07-03 富士通株式会社 Semiconductor device
US8588720B2 (en) * 2009-12-15 2013-11-19 Qualcomm Incorproated Signal decimation techniques
US8188796B2 (en) * 2010-07-19 2012-05-29 Analog Devices, Inc. Digital phase-locked loop clock system
US8432231B2 (en) * 2010-07-19 2013-04-30 Analog Devices, Inc. Digital phase-locked loop clock system
US9000858B2 (en) 2012-04-25 2015-04-07 Qualcomm Incorporated Ultra-wide band frequency modulator
DE102014108774A1 (en) 2014-06-24 2016-01-07 Intel IP Corporation Apparatus and method for generating an oscillator signal

Citations (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0048935A2 (en) * 1980-09-29 1982-04-07 Siemens Aktiengesellschaft Circuit for the correct-phase starting of a quartz-controlled clock pulse oscillator
US4609881A (en) * 1983-05-17 1986-09-02 Marconi Instruments Limited Frequency synthesizers
US5038117A (en) * 1990-01-23 1991-08-06 Hewlett-Packard Company Multiple-modulator fractional-N divider
US5053728A (en) * 1989-11-28 1991-10-01 Rohde & Schwarz Gmbh & Co., Kg Phase locked loop frequency modulator using data modulated digital synthesizer as reference
US5055802A (en) * 1990-04-30 1991-10-08 Motorola, Inc. Multiaccumulator sigma-delta fractional-n synthesis
US5055800A (en) * 1990-04-30 1991-10-08 Motorola, Inc. Fractional n/m synthesis
US5070310A (en) * 1990-08-31 1991-12-03 Motorola, Inc. Multiple latched accumulator fractional N synthesis
US5093632A (en) * 1990-08-31 1992-03-03 Motorola, Inc. Latched accumulator fractional n synthesis with residual error reduction
US5111162A (en) * 1991-05-03 1992-05-05 Motorola, Inc. Digital frequency synthesizer having AFC and modulation applied to frequency divider
US5146186A (en) * 1991-05-13 1992-09-08 Microsource, Inc. Programmable-step, high-resolution frequency synthesizer which substantially eliminates spurious frequencies without adversely affecting phase noise
US5266907A (en) * 1991-06-25 1993-11-30 Timeback Fll Continuously tuneable frequency steerable frequency synthesizer having frequency lock for precision synthesis
US5430890A (en) * 1992-11-20 1995-07-04 Blaupunkt-Werke Gmbh Radio receiver for mobile reception with sampling rate oscillator frequency being an integer-number multiple of reference oscillation frequency
US5786715A (en) * 1996-06-21 1998-07-28 Sun Microsystems, Inc. Programmable digital frequency multiplier
US6044124A (en) * 1997-08-22 2000-03-28 Silicon Systems Design Ltd. Delta sigma PLL with low jitter
US6219396B1 (en) * 1997-05-23 2001-04-17 Oki Electric Industry Co., Ltd. Jitter resistant clock regenerator
US20020168038A1 (en) * 2001-03-30 2002-11-14 Morten Damgaard System for controlling the frequency of an oscillator
US20030112915A1 (en) * 2001-12-14 2003-06-19 Epson Research And Development , Inc. Lock detector circuit for dejitter phase lock loop (PLL)
US6690215B2 (en) * 1999-03-17 2004-02-10 Tropian, Inc. Sigma-delta-based frequency synthesis
US6693494B2 (en) * 2001-08-20 2004-02-17 Koninklijke Philips Electronics N.V. Frequency synthesizer with three mode loop filter charging
US20040036509A1 (en) * 2002-07-12 2004-02-26 Sterling Smith Frequency synthesizer
US6704908B1 (en) * 1999-11-17 2004-03-09 Amadala Limited Method and apparatus for automatically generating a phase lock loop (PLL)
US6707855B2 (en) * 2002-06-20 2004-03-16 Nokia Corporation Digital delta sigma modulator in a fractional-N frequency synthesizer
US6708026B1 (en) * 2000-01-11 2004-03-16 Ericsson Inc. Division based local oscillator for frequency synthesis
US6710951B1 (en) * 2001-10-31 2004-03-23 Western Digital Technologies, Inc. Phase locked loop employing a fractional frequency synthesizer as a variable oscillator
US6710664B2 (en) * 2002-04-22 2004-03-23 Rf Micro Devices, Inc. Coarse tuning for fractional-N synthesizers
US6717998B2 (en) * 1999-12-13 2004-04-06 Matsushita Electric Industrial Co., Ltd. Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method
US20040066240A1 (en) * 2001-04-25 2004-04-08 Staszewski Robert B. Frequency synthesizer with digitally-controlled oscillator
US6822593B2 (en) * 2002-05-28 2004-11-23 Stmicroelectronics Sa. Digital to digital Sigma-Delta modulator and digital frequency synthesizer incorporating the same
US6823033B2 (en) * 2002-03-12 2004-11-23 Qualcomm Inc. ΣΔdelta modulator controlled phase locked loop with a noise shaped dither
US6825729B2 (en) * 2000-04-19 2004-11-30 Siemens Aktiengesellschaft Frequency synthesizer with sigma-delta modulation
US6829311B1 (en) * 2000-09-19 2004-12-07 Kaben Research Inc. Complex valued delta sigma phase locked loop demodulator
US6834183B2 (en) * 2002-11-04 2004-12-21 Motorola, Inc. VCO gain tracking for modulation gain setting calibration
US6836526B2 (en) * 2003-02-25 2004-12-28 Agency For Science, Technology And Research Fractional-N synthesizer with two control words
US6838951B1 (en) * 2002-06-12 2005-01-04 Rf Micro Devices, Inc. Frequency synthesizer having VCO bias current compensation
US6844836B1 (en) * 2000-10-10 2005-01-18 Samsung Electronics Co., Ltd. Single-bit sigma-delta modulated fractional-N frequency synthesizer
US20050042991A1 (en) * 2003-08-21 2005-02-24 The Chamberlain Group, Inc. Wireless transmit-only apparatus and method
US6873213B2 (en) * 2001-10-02 2005-03-29 Nec Compound Semiconductor Devices, Ltd. Fractional N frequency synthesizer
US20050085194A1 (en) * 2003-10-20 2005-04-21 Ian Robinson Frequency agile exciter
US6897796B2 (en) * 2003-07-11 2005-05-24 Infineon Technologies Ag Sigma-delta converter arrangement
US6931243B2 (en) * 2001-12-21 2005-08-16 Texas Instruments Incorporated Fully integrated low noise multi-loop synthesizer with fine frequency resolution for HDD read channel and RF wireless local oscillator applications
US6933798B2 (en) * 2001-02-22 2005-08-23 Infineon Technologies Ag Trimming method and trimming device for a PLL circuit for two-point modulation
US6941116B2 (en) * 2002-11-27 2005-09-06 Broadcom Corp. Linearization technique for phase locked loops employing differential charge pump circuitry
US6946330B2 (en) * 2001-10-11 2005-09-20 Semiconductor Energy Laboratory Co., Ltd. Designing method and manufacturing method for semiconductor display device
US6952138B2 (en) * 2001-09-12 2005-10-04 Telefonaktiebolaget Lm Ericsson (Publ) Generation of a phase locked loop output signal having reduced spurious spectral components
US7031686B2 (en) * 2001-03-14 2006-04-18 Integrant Technologies, Inc. Image rejection mixer with mismatch compensation
US20060141969A1 (en) * 2000-12-07 2006-06-29 Dubash Noshir B L1/L2 GPS receiver
US7154978B2 (en) * 2001-11-02 2006-12-26 Motorola, Inc. Cascaded delay locked loop circuit
US20070099588A1 (en) * 2005-11-02 2007-05-03 Ars Holding Corporation Method and apparatus for receiving and/or down converting high frequency signals in multi mode/ multi band applications, using mixer and sampler
US7482885B2 (en) * 2005-12-29 2009-01-27 Orca Systems, Inc. Method of frequency synthesis for fast switching
US7519349B2 (en) * 2006-02-17 2009-04-14 Orca Systems, Inc. Transceiver development in VHF/UHF/GSM/GPS/bluetooth/cordless telephones

Family Cites Families (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2019297A1 (en) 1990-01-23 1991-07-23 Brian M. Miller Multiple-modulator fractional-n divider
JPH0795687B2 (en) * 1991-01-18 1995-10-11 アンリツ株式会社 Frequency synthesizer
DE69315614T2 (en) * 1992-04-23 1998-07-02 Hitachi Ltd A frequency synthesizer
US5463337A (en) * 1993-11-30 1995-10-31 At&T Corp. Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein
US5563535A (en) * 1994-11-29 1996-10-08 Microunity Systems Engineering, Inc. Direct digital frequency synthesizer using sigma-delta techniques
EP0815648B1 (en) * 1995-03-16 2002-06-19 QUALCOMM Incorporated Direct digital synthesizer driven pll frequency synthesizer with clean-up pll
EP0788237A4 (en) 1995-08-03 1998-11-25 Anritsu Corp Rational frequency divider and frequency synthesizer using the frequency divider
US5805003A (en) * 1995-11-02 1998-09-08 Cypress Semiconductor Corp. Clock frequency synthesis using delay-locked loop
US5790612A (en) * 1996-02-29 1998-08-04 Silicon Graphics, Inc. System and method to reduce jitter in digital delay-locked loops
US5604468A (en) * 1996-04-22 1997-02-18 Motorola, Inc. Frequency synthesizer with temperature compensation and frequency multiplication and method of providing the same
US5802463A (en) * 1996-08-20 1998-09-01 Advanced Micro Devices, Inc. Apparatus and method for receiving a modulated radio frequency signal by converting the radio frequency signal to a very low intermediate frequency signal
US5920233A (en) * 1996-11-18 1999-07-06 Peregrine Semiconductor Corp. Phase locked loop including a sampling circuit for reducing spurious side bands
US6008703A (en) * 1997-01-31 1999-12-28 Massachusetts Institute Of Technology Digital compensation for wideband modulation of a phase locked loop frequency synthesizer
US5894592A (en) * 1997-04-17 1999-04-13 Motorala, Inc. Wideband frequency synthesizer for direct conversion transceiver
US5777521A (en) * 1997-08-12 1998-07-07 Motorola Inc. Parallel accumulator fractional-n frequency synthesizer
US6094569A (en) * 1997-08-12 2000-07-25 U.S. Philips Corporation Multichannel radio device, a radio communication system, and a fractional division frequency synthesizer
JPH1174807A (en) * 1997-08-29 1999-03-16 Mitsubishi Electric Corp Phase synchronization device
US6047029A (en) * 1997-09-16 2000-04-04 Telefonaktiebolaget Lm Ericsson Post-filtered delta sigma for controlling a phase locked loop modulator
US6219397B1 (en) * 1998-03-20 2001-04-17 Samsung Electronics Co., Ltd. Low phase noise CMOS fractional-N frequency synthesizer for wireless communications
CA2233831A1 (en) * 1998-03-31 1999-09-30 Tom Riley Digital-sigma fractional-n synthesizer
US6008704A (en) * 1998-06-09 1999-12-28 Rockwell Collins, Inc. Fractional frequency synthesizer with modulation linearizer
AU4726099A (en) * 1998-06-30 2000-01-17 Qualcomm Incorporated System for generating an accurate low-noise periodic signal
US6321075B1 (en) * 1998-07-30 2001-11-20 Qualcomm Incorporated Hardware-efficient transceiver with delta-sigma digital-to-analog converter
DE19840241C1 (en) * 1998-09-03 2000-03-23 Siemens Ag Digital PLL (Phase Locked Loop) -Frequenzsynthesizer
US6525609B1 (en) * 1998-11-12 2003-02-25 Broadcom Corporation Large gain range, high linearity, low noise MOS VGA
US6066989A (en) * 1998-12-21 2000-05-23 Cts Corporation Frequency synthesizer module for dual band radio
US6172579B1 (en) * 1999-02-02 2001-01-09 Cleveland Medical Devices Inc. Three point modulated phase locked loop frequency synthesis system and method
US6094101A (en) * 1999-03-17 2000-07-25 Tropian, Inc. Direct digital frequency synthesis enabling spur elimination
CA2281522C (en) * 1999-09-10 2004-12-07 Philsar Electronics Inc. Delta-sigma based two-point angle modulation scheme
AU7834700A (en) * 1999-09-27 2001-04-30 Parthus Technologies Plc Method and apparatus for a frequency synthesizer having a compensated sigma delta modulator output signal
JP3364206B2 (en) 1999-12-13 2003-01-08 松下電器産業株式会社 Frequency synthesizer device, a communication device, a frequency modulation apparatus and a frequency modulation method
CA2295435C (en) * 2000-01-06 2004-03-30 Thomas Riley Linear low noise phase locked loop frequency synthesizer using controlled divider pulse widths
US6433643B1 (en) * 2000-02-22 2002-08-13 Rockwell Collins, Inc. Reduced latency differentiator
US6414555B2 (en) * 2000-03-02 2002-07-02 Texas Instruments Incorporated Frequency synthesizer
JP2001284531A (en) * 2000-03-29 2001-10-12 Advantest Corp Clock changer
US6483388B2 (en) * 2000-06-21 2002-11-19 Research In Motion Limited Direct digital frequency synthesizer and a hybrid frequency synthesizer combining a direct digital frequency synthesizer and a phase locked loop
US6326851B1 (en) * 2000-06-26 2001-12-04 Texas Instruments Incorporated Digital phase-domain PLL frequency synthesizer
US6429693B1 (en) * 2000-06-30 2002-08-06 Texas Instruments Incorporated Digital fractional phase detector
JP3415574B2 (en) * 2000-08-10 2003-06-09 Necエレクトロニクス株式会社 Pll circuit
US6542044B1 (en) * 2000-09-11 2003-04-01 Rockwell Collins, Inc. Integrated frequency source
US6941330B2 (en) * 2000-09-27 2005-09-06 Hughes Electronics Corporation Feed forward sigma delta interpolator for use in a fractional-N synthesizer
EP1193879A1 (en) * 2000-09-29 2002-04-03 Philips Electronics N.V. Low noise frequency synthesizer with rapid response and corresponding method for frequency synthesis
US6553089B2 (en) * 2001-03-20 2003-04-22 Gct Semiconductor, Inc. Fractional-N frequency synthesizer with fractional compensation method
US6429707B1 (en) * 2001-04-27 2002-08-06 Semtech Corporation Reference signal switchover clock output controller
US6504437B1 (en) * 2001-06-26 2003-01-07 Agere Systems Inc. Low-noise, fast-lock phase-lock loop with “gearshifting” control
JP4493887B2 (en) * 2001-08-03 2010-06-30 セイコーNpc株式会社 Fractional n frequency synthesizer and a method of operating the same
US6570452B2 (en) * 2001-09-26 2003-05-27 Ashvattha Semiconductor, Inc. Fractional-N type frequency synthesizer
JP3995142B2 (en) * 2001-11-12 2007-10-24 沖電気工業株式会社 The semiconductor integrated circuit
US6600378B1 (en) * 2002-01-18 2003-07-29 Nokia Corporation Fractional-N frequency synthesizer with sine wave generator
US6946884B2 (en) * 2002-04-25 2005-09-20 Agere Systems Inc. Fractional-N baseband frequency synthesizer in bluetooth applications
US6946915B2 (en) * 2003-03-17 2005-09-20 Xiaopin Zhang Maximally digitized fractional-N frequency synthesizer and modulator with maximal fractional spurs removing
DE102004023484B4 (en) * 2003-12-12 2006-10-12 Technische Universität Dresden Oscillator system for generating a clock signal

Patent Citations (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0048935A2 (en) * 1980-09-29 1982-04-07 Siemens Aktiengesellschaft Circuit for the correct-phase starting of a quartz-controlled clock pulse oscillator
US4609881A (en) * 1983-05-17 1986-09-02 Marconi Instruments Limited Frequency synthesizers
US5053728A (en) * 1989-11-28 1991-10-01 Rohde & Schwarz Gmbh & Co., Kg Phase locked loop frequency modulator using data modulated digital synthesizer as reference
US5038117A (en) * 1990-01-23 1991-08-06 Hewlett-Packard Company Multiple-modulator fractional-N divider
US5055802A (en) * 1990-04-30 1991-10-08 Motorola, Inc. Multiaccumulator sigma-delta fractional-n synthesis
US5055800A (en) * 1990-04-30 1991-10-08 Motorola, Inc. Fractional n/m synthesis
US5070310A (en) * 1990-08-31 1991-12-03 Motorola, Inc. Multiple latched accumulator fractional N synthesis
US5093632A (en) * 1990-08-31 1992-03-03 Motorola, Inc. Latched accumulator fractional n synthesis with residual error reduction
US5111162A (en) * 1991-05-03 1992-05-05 Motorola, Inc. Digital frequency synthesizer having AFC and modulation applied to frequency divider
US5146186A (en) * 1991-05-13 1992-09-08 Microsource, Inc. Programmable-step, high-resolution frequency synthesizer which substantially eliminates spurious frequencies without adversely affecting phase noise
US5266907A (en) * 1991-06-25 1993-11-30 Timeback Fll Continuously tuneable frequency steerable frequency synthesizer having frequency lock for precision synthesis
US5430890A (en) * 1992-11-20 1995-07-04 Blaupunkt-Werke Gmbh Radio receiver for mobile reception with sampling rate oscillator frequency being an integer-number multiple of reference oscillation frequency
US5786715A (en) * 1996-06-21 1998-07-28 Sun Microsystems, Inc. Programmable digital frequency multiplier
US6219396B1 (en) * 1997-05-23 2001-04-17 Oki Electric Industry Co., Ltd. Jitter resistant clock regenerator
US6044124A (en) * 1997-08-22 2000-03-28 Silicon Systems Design Ltd. Delta sigma PLL with low jitter
US6690215B2 (en) * 1999-03-17 2004-02-10 Tropian, Inc. Sigma-delta-based frequency synthesis
US6704908B1 (en) * 1999-11-17 2004-03-09 Amadala Limited Method and apparatus for automatically generating a phase lock loop (PLL)
US6717998B2 (en) * 1999-12-13 2004-04-06 Matsushita Electric Industrial Co., Ltd. Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method
US6708026B1 (en) * 2000-01-11 2004-03-16 Ericsson Inc. Division based local oscillator for frequency synthesis
US6825729B2 (en) * 2000-04-19 2004-11-30 Siemens Aktiengesellschaft Frequency synthesizer with sigma-delta modulation
US6829311B1 (en) * 2000-09-19 2004-12-07 Kaben Research Inc. Complex valued delta sigma phase locked loop demodulator
US6844836B1 (en) * 2000-10-10 2005-01-18 Samsung Electronics Co., Ltd. Single-bit sigma-delta modulated fractional-N frequency synthesizer
US20060141969A1 (en) * 2000-12-07 2006-06-29 Dubash Noshir B L1/L2 GPS receiver
US6933798B2 (en) * 2001-02-22 2005-08-23 Infineon Technologies Ag Trimming method and trimming device for a PLL circuit for two-point modulation
US7031686B2 (en) * 2001-03-14 2006-04-18 Integrant Technologies, Inc. Image rejection mixer with mismatch compensation
US20020168038A1 (en) * 2001-03-30 2002-11-14 Morten Damgaard System for controlling the frequency of an oscillator
US20040066240A1 (en) * 2001-04-25 2004-04-08 Staszewski Robert B. Frequency synthesizer with digitally-controlled oscillator
US6734741B2 (en) * 2001-04-25 2004-05-11 Texas Instruments Incorporated Frequency synthesizer with digitally-controlled oscillator
US6791422B2 (en) * 2001-04-25 2004-09-14 Texas Instruments Incorporated Frequency synthesizer with digitally-controlled oscillator
US6693494B2 (en) * 2001-08-20 2004-02-17 Koninklijke Philips Electronics N.V. Frequency synthesizer with three mode loop filter charging
US6952138B2 (en) * 2001-09-12 2005-10-04 Telefonaktiebolaget Lm Ericsson (Publ) Generation of a phase locked loop output signal having reduced spurious spectral components
US6873213B2 (en) * 2001-10-02 2005-03-29 Nec Compound Semiconductor Devices, Ltd. Fractional N frequency synthesizer
US6946330B2 (en) * 2001-10-11 2005-09-20 Semiconductor Energy Laboratory Co., Ltd. Designing method and manufacturing method for semiconductor display device
US6710951B1 (en) * 2001-10-31 2004-03-23 Western Digital Technologies, Inc. Phase locked loop employing a fractional frequency synthesizer as a variable oscillator
US7154978B2 (en) * 2001-11-02 2006-12-26 Motorola, Inc. Cascaded delay locked loop circuit
US20030112915A1 (en) * 2001-12-14 2003-06-19 Epson Research And Development , Inc. Lock detector circuit for dejitter phase lock loop (PLL)
US6931243B2 (en) * 2001-12-21 2005-08-16 Texas Instruments Incorporated Fully integrated low noise multi-loop synthesizer with fine frequency resolution for HDD read channel and RF wireless local oscillator applications
US6823033B2 (en) * 2002-03-12 2004-11-23 Qualcomm Inc. ΣΔdelta modulator controlled phase locked loop with a noise shaped dither
US6710664B2 (en) * 2002-04-22 2004-03-23 Rf Micro Devices, Inc. Coarse tuning for fractional-N synthesizers
US6822593B2 (en) * 2002-05-28 2004-11-23 Stmicroelectronics Sa. Digital to digital Sigma-Delta modulator and digital frequency synthesizer incorporating the same
US6838951B1 (en) * 2002-06-12 2005-01-04 Rf Micro Devices, Inc. Frequency synthesizer having VCO bias current compensation
US6707855B2 (en) * 2002-06-20 2004-03-16 Nokia Corporation Digital delta sigma modulator in a fractional-N frequency synthesizer
US20040036509A1 (en) * 2002-07-12 2004-02-26 Sterling Smith Frequency synthesizer
US6844758B2 (en) * 2002-07-12 2005-01-18 Mstar Semiconductor Inc. Frequency synthesizer
US6834183B2 (en) * 2002-11-04 2004-12-21 Motorola, Inc. VCO gain tracking for modulation gain setting calibration
US6941116B2 (en) * 2002-11-27 2005-09-06 Broadcom Corp. Linearization technique for phase locked loops employing differential charge pump circuitry
US6836526B2 (en) * 2003-02-25 2004-12-28 Agency For Science, Technology And Research Fractional-N synthesizer with two control words
US6897796B2 (en) * 2003-07-11 2005-05-24 Infineon Technologies Ag Sigma-delta converter arrangement
US20050042991A1 (en) * 2003-08-21 2005-02-24 The Chamberlain Group, Inc. Wireless transmit-only apparatus and method
US20050085194A1 (en) * 2003-10-20 2005-04-21 Ian Robinson Frequency agile exciter
US7146144B2 (en) * 2003-10-20 2006-12-05 Northrop Grumman Corporation Frequency agile exciter
US20070099588A1 (en) * 2005-11-02 2007-05-03 Ars Holding Corporation Method and apparatus for receiving and/or down converting high frequency signals in multi mode/ multi band applications, using mixer and sampler
US7482885B2 (en) * 2005-12-29 2009-01-27 Orca Systems, Inc. Method of frequency synthesis for fast switching
US7519349B2 (en) * 2006-02-17 2009-04-14 Orca Systems, Inc. Transceiver development in VHF/UHF/GSM/GPS/bluetooth/cordless telephones

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Analog Devices, "800 MHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs", AD9510 data sheet, November 2004. *
Olsson et al., "An all-Digital PLL Clock Multiplier", ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on. IEEE, 2002. *
Remco et al., "A 2.5-10-GHz Clock Multiplier Unit With 0.22-ps RMS Jitter in Standard 0.18-um CMOS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004, pp 1862-1874 *
Stephens, "Phase Locked Loops for Wireless Communications", Analog Phase-Locked Loops, ISBN 978-1-4613-7618-7, Springer, 1998, pp 9-17 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011120769A1 (en) 2011-12-10 2013-06-13 Imst Gmbh Synchronous modulated-fully digital delta-sigma modulator circuit for use in fractional N-phase locked loop frequency synthesizer, has digital un-modulated fractional-control signal processing full-digital delta-sigma modulator circuit
DE102011120769B4 (en) 2011-12-10 2018-09-20 Imst Gmbh Synchronously modulated full-digital delta-sigma modulator circuit
US20150171918A1 (en) * 2013-12-17 2015-06-18 National Applied Research Laboratories Spread spectrum clock generator and method for generating spread spectrum clock signal
US9191128B2 (en) * 2013-12-17 2015-11-17 National Applied Research Laboratories Spread spectrum clock generator and method for generating spread spectrum clock signal
CN106301357A (en) * 2016-07-25 2017-01-04 南方科技大学 All-digital phase-locked loop

Also Published As

Publication number Publication date
KR20080096526A (en) 2008-10-30
WO2007079098A2 (en) 2007-07-12
JP5165585B2 (en) 2013-03-21
JP2009522875A (en) 2009-06-11
WO2007079098A3 (en) 2007-09-13
US7482885B2 (en) 2009-01-27
EP1969725A2 (en) 2008-09-17
EP1969725A4 (en) 2011-06-29
US7898345B2 (en) 2011-03-01
EP1969725B1 (en) 2012-09-19
US20070152757A1 (en) 2007-07-05
US20090146747A1 (en) 2009-06-11

Similar Documents

Publication Publication Date Title
JP4074166B2 (en) Emi reduction pll
KR100418236B1 (en) Phase-locking loop
US6229399B1 (en) Multiple frequency band synthesizer using a single voltage control oscillator
US8024598B2 (en) Apparatus and method for clock generation with piecewise linear modulation
EP1254517B2 (en) Frequency division/multiplication with jitter minimization
US5521948A (en) Frequency synthesizer
EP0988691B1 (en) Frequency synthesis circuit tuned by digital words
US20020136342A1 (en) Sample and hold type fractional-N frequency synthesezer
US20040196108A1 (en) Delay-compensated fractional-N frequency synthesizer
EP1609243B1 (en) Method and system of jitter compensation
US6064272A (en) Phase interpolated fractional-N frequency synthesizer with on-chip tuning
US20060245531A1 (en) Phase-locked loop using multi-phase feedback signals
US5146186A (en) Programmable-step, high-resolution frequency synthesizer which substantially eliminates spurious frequencies without adversely affecting phase noise
US7405628B2 (en) Technique for switching between input clocks in a phase-locked loop
US7881419B2 (en) Semiconductor device, spread spectrum clock generator and method thereof
Park et al. A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching
EP1104111B1 (en) Phase-locked loop with digitally controlled, frequency-multiplying oscilator
CN1158768C (en) Fractional-N frequency synthesizer with jitter compensation
EP1536565A1 (en) Signal processing device, signal processing method, delta-sigma modulation type fractional division pll frequency synthesizer, radio communication device, delta-sigma modulation type d/a converter
US6414555B2 (en) Frequency synthesizer
US6952125B2 (en) System and method for suppressing noise in a phase-locked loop circuit
US8331520B2 (en) Phase-locked loop circuit and communication apparatus
JP2526847B2 (en) Digitally radiotelephone
US7885369B2 (en) PLL frequency generator
KR20020039355A (en) Phase-locking loop

Legal Events

Date Code Title Description
AS Assignment

Owner name: ORCA SYSTEMS, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SRIDHARAN, KARTIK M.;REEL/FRAME:025826/0494

Effective date: 20081217

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION