DE102011111032A1 - Method for manufacturing power-semiconductor module, involves copper layer made of electrically conductive material differs from material and isolated on connecting surfaces and bonding wires - Google Patents

Method for manufacturing power-semiconductor module, involves copper layer made of electrically conductive material differs from material and isolated on connecting surfaces and bonding wires Download PDF

Info

Publication number
DE102011111032A1
DE102011111032A1 DE102011111032A DE102011111032A DE102011111032A1 DE 102011111032 A1 DE102011111032 A1 DE 102011111032A1 DE 102011111032 A DE102011111032 A DE 102011111032A DE 102011111032 A DE102011111032 A DE 102011111032A DE 102011111032 A1 DE102011111032 A1 DE 102011111032A1
Authority
DE
Germany
Prior art keywords
electrically conductive
layer
power semiconductor
semiconductor module
bonding wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE102011111032A
Other languages
German (de)
Inventor
Stefan Schuler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semikron GmbH and Co KG
Semikron Elektronik GmbH and Co KG
Original Assignee
Semikron GmbH and Co KG
Semikron Elektronik GmbH and Co KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semikron GmbH and Co KG, Semikron Elektronik GmbH and Co KG filed Critical Semikron GmbH and Co KG
Priority to DE102011111032A priority Critical patent/DE102011111032A1/en
Publication of DE102011111032A1 publication Critical patent/DE102011111032A1/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48717—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48724—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H01L2224/48996—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/48997—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/495—Material
    • H01L2224/49505—Connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

The method involves arranging a power-semiconductor element (13) on a support substrate (11). The element is provided with insulated gate bipolar transistor-emitter and gate connecting surfaces that face away from the substrate provided with emitter-and gate contact surfaces (16, 17) and a strip conductor. The connecting surfaces are connected with the contact surfaces by bonding wires (18, 19), where the wires are made of material. A copper layer (20) is made of electrically conductive material that is different from the material and isolated on the connecting surfaces and wires. An independent claim is also included for a power-semiconductor module.

Description

Die Erfindung betrifft ein Verfahren zum Aufbau von Leistungs-Halbleitermodulen sowie ein nach dem Verfahren hergestelltes Leistungs-Halbleitermodul.The invention relates to a method for constructing power semiconductor modules and to a power semiconductor module produced by the method.

Leistungs-Halbleitermodule können einen oder mehrere Leistungs-Halbleiterbauelemente, beispielsweise IGBT (Insulated Gate Bipolar Transistor) aufweisen, die auf ein DCB-Substrat (DCB: Direct Copper Bonded) durch stoffschlüssige Verbindungen, wie Löten oder Sintern aufgebracht und elektrisch leitend verbunden werden. Diese Leistungs-Halbleiterbauelemente weisen hierbei auf der dem Substrat abgewandten Oberfläche Metallisierungsflächen auf, die beispielsweise die Gate-Anschlussfläche und die Emitter-Anschlussfläche eines IGBT ausbilden, die mittels Bonddrähten mit auf dem DCB-Substrat angeordneten Leiterbahnen verbunden werden. Im Bereich der Leistungselektronik kommen als Material für die Bonddrähte insbesondere reine Aluminium-Materialien mit einer Reinheit von 99% und höher zur Anwendung.Power semiconductor modules may comprise one or more power semiconductor devices, for example IGBTs (Insulated Gate Bipolar Transistor), which are applied to and electrically conductively connected to a DCB (Direct Copper Bonded) substrate by bonded connections, such as soldering or sintering. In this case, these power semiconductor components have metallization surfaces on the surface remote from the substrate, which form, for example, the gate pad and the emitter pad of an IGBT, which are connected by means of bond wires to printed conductors arranged on the DCB substrate. In the field of power electronics come as a material for the bonding wires in particular pure aluminum materials with a purity of 99% and higher used.

Um das Bonden mit Aluminium-Bonddrähten zu ermöglichen, weisen die Gate- und Emitter-Anschlussflächen der IGBT bevorzugt eine Aluminium-Metallisierung auf. Das Bonden mit Aluminium-Bonddrähten ist zwar eine ausgereifte Technologie, weist jedoch den Nachteil auf, dass die Lebensdauer der Bondverbindungen mit steigender zulässiger Sperrschichttemperatur der IGBT absinkt. IGBT einer neuen Generation werden anstelle der bisher üblichen Sperrschichttemperatur von 150°C eine Sperrschichttemperatur von 200°C aufweisen, so dass die dann vergleichsweise geringe erreichbare Lebensdauer im Nennbetrieb ein großes Problem darstellen wird.In order to enable bonding with aluminum bonding wires, the gate and emitter pads of the IGBT preferably have an aluminum metallization. Although bonding with aluminum bonding wires is a mature technology, it has the disadvantage that the life of the bonding connections decreases as the permissible junction temperature of the IGBT increases. IGBT a new generation will have a junction temperature of 200 ° C instead of the usual barrier layer temperature of 150 ° C, so that then comparatively low achievable life in nominal operation will be a major problem.

Aufgabe der vorliegenden Erfindung ist es, ein Verfahren für eine verbesserte Verbindung zwischen Leistungs-Halbleiterbauelement und Substrat sowie ein mit diesem Verfahren hergestelltes verbessertes Leistungs-Halbleitermodul anzugeben.The object of the present invention is to specify a method for an improved connection between power semiconductor component and substrate as well as an improved power semiconductor module produced by this method.

Erfindungsgemäß wird diese Aufgabe mit einem Verfahren zur Herstellung eines Leistungs-Halbleitermoduls gelöst, das mindestens ein auf einem Trägersubstrat angeordnetes Leistungs-Halbleiterbauelement mit von dem Trägersubstrat abgewandten Anschlussflächen umfasst, wobei das Trägersubstrat Kontaktflächen und Leiterbahnen umfasst, wobei die Anschlussflächen mittels Bonddrähten aus einem ersten Material mit den Kontaktflächen stoffschlüssig verbunden sind, wobei vorgesehen ist, dass auf den Anschlussflächen und den Bonddrähten eine von dem ersten Material verschiedene Schicht aus einem elektrisch leitfähigen zweiten Material abgeschieden wird.According to the invention, this object is achieved with a method for producing a power semiconductor module which comprises at least one power semiconductor component arranged on a carrier substrate with connection surfaces facing away from the carrier substrate, the carrier substrate comprising contact surfaces and conductor tracks, wherein the connection surfaces are made of a first material by means of bonding wires are materially connected to the contact surfaces, wherein it is provided that a different layer of the first material of an electrically conductive second material is deposited on the pads and the bonding wires.

Weiter wird die Aufgabe mit einem Leistungs-Halbleitermodul gelöst, das mindestens ein auf einem Trägersubstrat angeordnetes Leistungs-Halbleiterbauelement mit von dem Trägersubstrat abgewandten Anschlussflächen umfasst, wobei das Trägersubstrat Kontaktflächen und Leiterbahnen umfasst, wobei die Anschlussflächen mittels Bonddrähten aus einem ersten Material mit den Kontaktflächen stoffschlüssig verbunden sind, wobei vorgesehen ist, dass auf den Anschlussflächen und den Bonddrähten eine von dem ersten Material verschiedene Schicht aus einem elektrisch leitfähigen zweiten Material ausgebildet ist.Furthermore, the object is achieved with a power semiconductor module which comprises at least one power semiconductor component arranged on a carrier substrate with connection surfaces facing away from the carrier substrate, wherein the carrier substrate comprises contact surfaces and conductor tracks, wherein the connection surfaces are bonded by means of bonding wires of a first material to the contact surfaces are provided, it being provided that on the pads and the bonding wires a different layer of the first material is formed from an electrically conductive second material.

Die auf den Anschlussflächen des mindestens einen aus einem Silizium-Chip bestehenden Leistungs-Halbleiterbauelements sowie auf den Kontaktflächen und den Bonddrähten des Leistungs-Halbleitermoduls aufgebrachte Schicht aus dem zweiten elektrisch leitfähigen Material verbessert unter anderem die Leitfähigkeit der zumeist aus Aluminium ausgebildeten Bonddrähte, senkt dadurch deren relative Strombelastung und ermöglicht so die Verwendung dünnerer Bonddrähte oder die Erhöhung der Zuverlässigkeit von Bonddrähten üblicher Dimensionen. Zugleich wird die mechanische Festigkeit der Bonddrähte erhöht und es werden mechanische Spannungen besser ausgeglichen, die durch die unterschiedliche Ausdehnung von Silizium und Bonddraht-Material bei thermischer Belastung entstehen. Das ist ein weiterer Vorteil im Hinblick darauf, dass mit neuen Bauelementegenerationen mehrfach auch die zulässige Betriebstemperatur der Chips erhöht wurde.The layer of the second electrically conductive material applied to the connecting surfaces of the at least one silicon-chip power semiconductor component and the contact surfaces and bonding wires of the power semiconductor module improves, inter alia, the conductivity of the bonding wires, which are generally made of aluminum, thereby lowering their conductivity Relative current load and thus allows the use of thinner bonding wires or increasing the reliability of bonding wires of conventional dimensions. At the same time, the mechanical strength of the bonding wires is increased and it is better balanced mechanical stresses caused by the different expansion of silicon and bonding wire material under thermal stress. This is a further advantage in view of the fact that with new component generations, the permissible operating temperature of the chips has also been increased several times.

Der Ausgangspunkt für die Erfindung ist nicht nur die Bondverbindung als solche, sondern sind auch verwandte Verbindungstechniken, beispielsweise Bändchenbonden und Lötbrücken. Es könnte sogar eine nichtleitende Verbindung Ausgangspunkt sein, die dann mit dem elektrisch leitfähigen zweiten Material beschichtet wird und somit quasi ein Analogon zu einem Bonddraht bildet.The starting point for the invention is not only the bond as such, but are also related bonding techniques, such as ribbon bonding and solder bridges. It could even be a non-conductive connection starting point, which is then coated with the electrically conductive second material and thus virtually forms an analogue to a bonding wire.

Es kann vorgesehen sein, dass weiter auf den Kontaktflächen die von dem ersten Material verschiedene Schicht aus dem elektrisch leitfähigen zweiten Material abgeschieden wird.It can be provided that the layer of the electrically conductive second material which is different from the first material is further deposited on the contact surfaces.

Es kann weiter vorgesehen sein, dass das elektrisch leitfähige zweite Material aus einer Gruppe gebildet ist, die die Metalle Kupfer, Silber und Gold sowie Legierungen, die mit einem oder mehreren dieser Metalle gebildet sind, umfasst. Wegen der guten Leitfähigkeit und des vergleichsweise geringen Preises kann als Material Kupfer bevorzugt sein.It may further be provided that the electrically conductive second material is formed from a group comprising the metals copper, silver and gold and alloys which are formed with one or more of these metals. Because of the good conductivity and the relatively low price may be preferred as a material copper.

Es kann vorgesehen sein, dass die Schicht aus dem elektrisch leitfähigen zweiten Material galvanisch aufgebracht wird.It can be provided that the layer of the electrically conductive second material is applied galvanically.

Alternativ kann vorgesehen sein, dass die Schicht aus dem elektrisch leitfähigen zweiten Material durch physikalische Gasphasenabscheidung aufgebracht wird. Die physikalische Gasphasenabscheidung, auch als PVD (Physical Vapour Deposition) bezeichnet, beruht auf physikalischen Wirkungsverfahren und wird in einer Schutzgasatmosphäre unter geringem Druck oder im Vakuum durchgeführt. Alternatively it can be provided that the layer of the electrically conductive second material is applied by physical vapor deposition. Physical vapor deposition, also referred to as PVD (Physical Vapor Deposition), is based on physical working methods and is carried out in a protective gas atmosphere under low pressure or in vacuo.

Es kann vorgesehen sein, dass die Schicht aus dem elektrisch leitfähigen zweiten Material durch Kathodenzerstäubung aufgebracht wird. Die Kathodenzerstäubung wird mittels einer hohen Gleichspannung durchgeführt, wobei das zu zerstäubende Material die Kathode bildet und die zu beschichtenden Metallflächen elektrisch miteinander verbunden sind und die Anode bilden. Eine andere Bezeichnung für Kathodenzerstäubung ist Sputtern. Die aus der Kathode herausgeschlagenen Atome werden auf den zu beschichtenden Metallflächen abgeschieden.It can be provided that the layer of the electrically conductive second material is applied by cathode sputtering. The sputtering is carried out by means of a high DC voltage, wherein the material to be sputtered forms the cathode and the metal surfaces to be coated are electrically connected to each other and form the anode. Another name for sputtering is sputtering. The atoms knocked out of the cathode are deposited on the metal surfaces to be coated.

Es kann vorgesehen sein, dass die Schicht aus dem elektrisch leitfähigen zweiten Material durch DC-Dioden-Sputtern aufgebracht wird. Das DC-Dioden-Sputtern, bei dem mit einer Beschleunigungsgleichspannung von 500 bis 1000 V ein Argon-Niederdruckplasma zwischen dem Target und den zu beschichtenden Metallflächen gezündet wird, hat sich als besonders geeignet erwiesen.It can be provided that the layer of the electrically conductive second material is applied by DC diode sputtering. The DC diode sputtering, in which an argon low-pressure plasma is ignited between the target and the metal surfaces to be coated with an acceleration DC voltage of 500 to 1000 V, has proved to be particularly suitable.

Es kann weiter vorgesehen sein, dass die Schicht aus dem elektrisch leitfähigen zweiten Material durch Ionenplattieren aufgebracht wird. Beim Ionenplattieren wird das aufzutragende Material beispielsweise durch eine Bogenentladung in ein Plasma überführt. Dort ionisiert ein Teil der Materialdampfwolke und wird in Richtung der zu beschichtenden Flächen geführt.It can further be provided that the layer of the electrically conductive second material is applied by ion plating. In ion plating, the material to be applied is transferred, for example, by an arc discharge into a plasma. There ionizes a part of the material vapor cloud and is guided in the direction of the surfaces to be coated.

Es kann auch vorgesehen sein, dass die Schicht aus dem elektrisch leitfähigen zweiten Material durch thermisches Verdampfen aufgebracht wird. Dabei liegt das abzuscheidende Material in fester Form in der meist evakuierten Beschichtungskammer vor. Durch den Beschuss mit Laserstrahlen, magnetisch abgelenkten Ionen oder Elektronen sowie durch Lichtbogenentladung wird das Material verdampft. Das verdampfte Material bewegt sich entweder ballistisch oder durch elektrische Felder geführt durch die Kammer und trifft dabei auf die zu beschichtenden Teile, wo es zur Schichtbildung kommt. Das geschieht bei Unterdruck, typischerweise im Bereich von 10–4 Pa bis ca. 10 Pa.It can also be provided that the layer of the electrically conductive second material is applied by thermal evaporation. In this case, the material to be deposited is in solid form in the most evacuated coating chamber. By bombarding with laser beams, magnetically deflected ions or electrons and by arc discharge, the material is vaporized. The vaporized material moves either ballistically or by electric fields guided through the chamber and strikes the parts to be coated, where it comes to film formation. This occurs at negative pressure, typically in the range of 10 -4 Pa to about 10 Pa.

Hierbei hat sich bewährt, dass die Schicht aus dem elektrisch leitfähigen zweiten Material durch Clusterstrahltechnik aufgebracht wird. Die Clusterstrahltechnik wird auch als ICBD (Ionized Cluster Beam Deposition) bezeichnet. In einem geschlossenen Tiegel wird Verdampfungsmaterial erhitzt, das dampfförmig durch eine Düse abgelassen werden kann. Dabei kommt es durch eine adiabatische Expansion zu einer plötzlichen Abkühlung. Es bilden sich neutrale Atomhaufen, sogenannte Cluster, die sich beim Auftreffen auf der zu beschichtenden Fläche teilweise auflösen und über die Oberfläche verteilt abscheiden.It has been proven that the layer of the electrically conductive second material is applied by cluster beam technology. The cluster beam technique is also referred to as ICBD (Ionized Cluster Beam Deposition). In a closed crucible evaporation material is heated, which can be discharged in vapor form through a nozzle. It comes through an adiabatic expansion to a sudden cooling. It forms neutral atomic clusters, so-called clusters, which partially dissolve when deposited on the surface to be coated and deposited distributed over the surface.

Es hat sich bewährt, dass die Schicht aus dem elektrisch leitfähigen zweiten Material eine Dicke im Bereich von 0,2 μm bis 20 μm, insbesondere von 0,5 μm bis 3 μm aufweist.It has been found that the layer of the electrically conductive second material has a thickness in the range from 0.2 μm to 20 μm, in particular from 0.5 μm to 3 μm.

Die Erfindung wird nun anhand von Ausführungsbeispielen näher erläutert. Es zeigenThe invention will now be explained in more detail with reference to exemplary embodiments. Show it

1 ein erfindungsgemäßes Leistungs-Halbleitermodul in einer schematischen Schnittdarstellung längs der Schnittlinie I-I in 2; 1 a power semiconductor module according to the invention in a schematic sectional view along the section line II in 2 ;

2 das Leistungs-Halbleitermodul in 1 in der Draufsicht; 2 the power semiconductor module in 1 in the plan view;

3a einen vergrößerten Ausschnitt eines ersten Ausführungsbeispiels eines beschichteten Bonddrahtes in schematischer Darstellung; 3a an enlarged detail of a first embodiment of a coated bonding wire in a schematic representation;

3b einen vergrößerten Ausschnitt eines zweiten Ausführungsbeispiels eines beschichteten Bonddrahtes in schematischer Darstellung; 3b an enlarged detail of a second embodiment of a coated bonding wire in a schematic representation;

4 einen vergrößerten Ausschnitt einer Bonddrahtverbindung in 1 in schematischer Darstellung. 4 an enlarged section of a bonding wire connection in 1 in a schematic representation.

Die 1 und 2 zeigen ein Leistungs-Halbleitermodul 1 mit einem keramischen Trägersubstrat 11, auf dem ein IGBT (Insulated Gate Bipolar Transistor) 13 angeordnet ist.The 1 and 2 show a power semiconductor module 1 with a ceramic carrier substrate 11 on which an IGBT (Insulated Gate Bipolar Transistor) 13 is arranged.

Das Trägersubstrat 11 besteht in diesem Anwendungsbeispiel aus einer Al2O3-Platte mit einer Dicke von 300 μm. Die Rückseite des Trägersubstrats 11 ist mit einer Metallschicht 12 aus Kupfer mit einer Dicke von 300 μm beschichtet. Die Vorderseite des Trägersubstrats 11 weist Leiterbahnen und Kontaktflächen aus Kupfer mit einer Dicke von 300 μm auf. Es handelt sich dabei beispielhaft um eine Kollektor-Kontaktfläche 15, auf der der IGBT 13 so angeordnet ist, dass dessen Kollektor-Anschlussfläche mittels einer Lotschicht 14 oder einer anderen geeigneten stoffschlüssigen Verbindung mit der Kollektor-Kontaktfläche 15 elektrisch und thermisch leitend verbunden ist und um eine Emitter-Kontaktfläche 16 sowie eine Gate-Kontaktfläche 17. Neben den Kontaktflächen können weitere elektrische Leiterbahnen auf dem Trägersubstrat 11 angeordnet sein, die in dem in 1 und 2 dargestellten Ausführungsbeispiel nicht dargestellt sind.The carrier substrate 11 consists in this application example of an Al 2 O 3 plate with a thickness of 300 microns. The back side of the carrier substrate 11 is with a metal layer 12 made of copper coated with a thickness of 300 microns. The front side of the carrier substrate 11 has traces and contact surfaces made of copper with a thickness of 300 microns. By way of example, this is a collector contact surface 15 on the IGBT 13 is arranged so that its collector pad by means of a solder layer 14 or another suitable cohesive connection with the collector contact surface 15 electrically and thermally conductively connected and to an emitter contact surface 16 and a gate contact area 17 , In addition to the contact surfaces can further electrical traces on the carrier substrate 11 be arranged in the in 1 and 2 illustrated embodiment are not shown.

Auf der der Kollektor-Anschlussfläche abgewandten Oberseite des IGBT 13 sind eine Emitter-Anschlussfläche 13e und eine Gate-Anschlussfläche 13g angeordnet, die mittels Bonddrähten 18 und 19 mit der Emitter-Kontaktfläche 16 bzw. mit der Gate-Kontaktfläche 17 elektrisch verbunden sind. Die Bonddrähte 18 und 19 sind aus Aluminium ausgebildet. Ebenso sind mindestens die Oberflächen der Emitter-Anschlussfläche 13e und der Gate-Anschlussfläche 13g aus Aluminium ausgebildet, so dass die Bondverbindung ohne Probleme ausgebildet werden kann. Als Bondverfahren kann das Ultraschallbonden vorgesehen sein. On the collector pad opposite the top of the IGBT 13 are an emitter pad 13e and a gate pad 13g arranged by means of bonding wires 18 and 19 with the emitter contact surface 16 or with the gate contact surface 17 are electrically connected. The bonding wires 18 and 19 are made of aluminum. Likewise, at least the surfaces of the emitter pad are 13e and the gate pad 13g made of aluminum, so that the bond can be formed without problems. As a bonding method, the ultrasonic bonding may be provided.

Die Emitter-Bonddrähte 18 sind für einen Strom von etwa 10 A ausgelegt und weisen einen Durchmesser von 300 μm auf. Zur Verbindung der Emitter-Anschlussfläche 13e mit der Emitter-Kontaktfläche 16 sind 8 Emitter-Bonddrähte 18 vorgesehen.The emitter bonding wires 18 are designed for a current of about 10 A and have a diameter of 300 microns. To connect the emitter pad 13e with the emitter contact surface 16 are 8 emitter bonding wires 18 intended.

Der Gate-Bonddraht 19 weist einen Durchmesser von 75 μm auf. Zur Verbindung der Gate-Anschlussfläche 13g mit der Gate-Kontaktfläche 17 ist 1 Gate-Bonddraht 19 vorgesehen.The gate bonding wire 19 has a diameter of 75 microns. To connect the gate pad 13g with the gate contact area 17 is 1 gate bonding wire 19 intended.

Zwecks besserer Darstellung sind die Bonddrähte und Schichtdicken in 1 und 2 nicht maßstäblich dargestellt.For better illustration, the bonding wires and layer thicknesses are in 1 and 2 not shown to scale.

Sowohl die Bonddrähte 18 und 19, als auch die Emitter-Kontaktfläche 16 und die Gate-Kontaktfläche 17 sind mit einer Kupferschicht 20 beschichtet, die eine Dicke von etwa 20 μm aufweist. Die Kupferschicht 20 verbessert sowohl das mechanische als auch das elektrische Verhalten der Bonddrähte 18 und 19. Weil während des Schaltens des IGBT 13 eine hohe Änderung der Spannung und/oder des Stromes pro Zeiteinheit auftritt, verläuft in diesen Zeitabschnitten wegen des Skin-Effekts die Elektronenleitung bevorzugt in der Kupferschicht 20, die eine deutlich bessere elektrische Leitfähigkeit als der Bonddrahtwerkstoff Aluminium aufweist.Both the bonding wires 18 and 19 , as well as the emitter contact surface 16 and the gate contact area 17 are with a copper layer 20 coated, which has a thickness of about 20 microns. The copper layer 20 improves both the mechanical and the electrical behavior of the bonding wires 18 and 19 , Because while switching the IGBT 13 a high change in the voltage and / or the current per unit time occurs, in these periods, due to the skin effect, the electron conduction preferably proceeds in the copper layer 20 , which has a significantly better electrical conductivity than the bonding wire material aluminum.

Die zur Beschichtung der Bonddrähte und der Kontaktflächen vorgesehene Metallschicht, hier Kupfer, kann sowohl galvanisch als auch durch physikalische Gasphasenabscheidung aufgebracht werden.The metal layer provided for coating the bonding wires and the contact surfaces, in this case copper, can be applied both galvanically and by physical vapor deposition.

Die physikalische Gasphasenabscheidung, auch als PVD bezeichnet, beruht auf physikalischen Wirkungsverfahren und wird in einer Schutzgasatmosphäre unter geringem Druck oder im Vakuum durchgeführt.Physical vapor deposition, also referred to as PVD, is based on physical action and is carried out in a protective gas atmosphere under low pressure or in vacuo.

Die Metallschicht kann beispielsweise durch Kathodenzerstäubung aufgebracht werden. Dazu werden die zu beschichtenden Metallflächen elektrisch miteinander verbunden und bilden eine Anode. Ein über den zu beschichtenden Metallflächen angeordnetes Target aus dem abzuscheidenden Metall bildet eine Kathode, aus der durch ein ionisiertes Gas Atome herausgeschlagen werden, die auf den zu beschichtenden Metallflächen abgeschieden werden.The metal layer can be applied, for example, by sputtering. For this purpose, the metal surfaces to be coated are electrically connected to each other and form an anode. A target of the metal to be deposited, which is arranged above the metal surfaces to be coated, forms a cathode from which atoms are ejected by an ionized gas, which atoms are deposited on the metal surfaces to be coated.

Als vorteilhaft hat sich das sogenannte DC-Dioden-Sputtern erwiesen, bei dem mit einer Beschleunigungsgleichspannung von 500 bis 1000 V ein Argon-Niederdruckplasma zwischen dem Target und den zu beschichtenden Metallflächen gezündet wird.Advantageous is the so-called DC diode sputtering, in which an acceleration DC voltage of 500 to 1000 V ignites an argon low-pressure plasma between the target and the metal surfaces to be coated.

Es kann auch vorgesehen sein, dass die Metallschicht durch Ionenplattieren aufgebracht wird. Beim Ionenplattieren wird das aufzutragende Metall beispielsweise durch eine Bogenentladung in ein Plasma überführt. Dort ionisiert ein Teil der Metalldampfwolke und wird in Richtung der zu beschichtenden Metallflächen geführt.It can also be provided that the metal layer is applied by ion plating. In ion plating, the metal to be applied is transferred to a plasma, for example, by an arc discharge. There ionizes a part of the metal vapor cloud and is guided in the direction of the metal surfaces to be coated.

Weiter kann die Metallschicht durch thermisches Verdampfen aufgebracht werden, beispielsweise mittels Clusterstrahltechnik, auch als ICBD bezeichnet.Furthermore, the metal layer can be applied by thermal evaporation, for example by means of cluster beam technology, also referred to as ICBD.

In einem geschlossenen Tiegel wird Verdampfungsmaterial erhitzt, das dampfförmig durch eine Düse abgelassen werden kann. Dabei kommt es durch eine adiabatische Expansion zu einer plätzlichen Abkühlung. Es bilden sich neutrale Atomhaufen, sogenannte Cluster, die sich beim Auftreffen auf der zu beschichtenden Metallfläche teilweise auflösen und über die Oberfläche verteilt abscheiden.In a closed crucible evaporation material is heated, which can be discharged in vapor form through a nozzle. It comes through an adiabatic expansion to a sudden cooling. It forms neutral atomic clusters, so-called clusters, which dissolve when hitting the metal surface to be coated partially and deposited distributed over the surface.

Zur Begrenzung der Metallabscheidung auf die zu beschichtenden Metallschichten können Masken vorgesehen sein, die über dem Leistungs-Halbleitermodul 1 angeordnet sind.In order to limit the metal deposition on the metal layers to be coated, masks may be provided which are above the power semiconductor module 1 are arranged.

Die 3a und 3b zeigen vergrößerte Ausschnitte eines beschichteten Bonddrahtes in schematischer Darstellung.The 3a and 3b show enlarged sections of a coated bonding wire in a schematic representation.

3a zeigt ein erstes Ausführungsbeispiel, bei dem die Strahlrichtung der Beschichtung (durch Pfeile angedeutet) senkrecht auf die Oberfläche des Leistungs-Halbleitermoduls gerichtet ist. Folglich weist die auf dem oberen, von der Oberfläche des Leistungs-Halbleitermoduls abgewandten Abschnitt des Bonddrahtes 18, 19 abgeschiedenen Kupferschicht 20 eine höhere Schichtdicke auf als die auf dem unteren Abschnitt des Bonddrahtes 18, 19 abgeschiedenen Kupferschicht 20. 3a shows a first embodiment in which the beam direction of the coating (indicated by arrows) is directed perpendicular to the surface of the power semiconductor module. Consequently, the portion of the bonding wire facing away from the upper surface of the power semiconductor module has the same 18 . 19 deposited copper layer 20 a higher layer thickness than that on the lower portion of the bonding wire 18 . 19 deposited copper layer 20 ,

Dagegen zeigt 3b ein Ausführungsbeispiel, bei der die Beschichtung halbkreisförmig erfolgt, so dass auf dem Bonddraht 18, 19 eine Kupferschicht 20 mit annähernd gleicher Schichtdicke ausgebildet wird.On the other hand shows 3b an embodiment in which the coating is semicircular, so that on the bonding wire 18 . 19 a copper layer 20 is formed with approximately the same layer thickness.

4 zeigt einen vergrößerten Ausschnitt einer Bonddrahtverbindung in 1 in schematischer Darstellung. Die Kupferschicht 20 umhüllt den Bonddraht 18, 19 vollständig und bedeckt zugleich die Emitter-Kontaktfläche 16. Damit wäre es auch möglich, nichtleitende Bondverbindungen auszubilden, die durch die Umhüllung mit der Kupferschicht 20 in eine elektrisch leitfähige Bondverbindung umgewandelt würden. 4 shows an enlarged section of a bonding wire connection in 1 in a schematic representation. The copper layer 20 envelops the bonding wire 18 . 19 complete and at the same time covers the emitter contact surface 16 , Thus, it would also be possible to form nonconductive bonds, through the cladding with the copper layer 20 would be converted into an electrically conductive bond.

Die weiter oben in der Beschreibung zur Fig. genannten Größenangaben für das IGBT 13 entsprechen dem Stand der Technik. Erfindungswesentlich ist aber, dass gemäß der Erfindung der Bonddraht dünner, oder im Extremfall sogar aus einem Nichtleiter ausgebildet sein kann. Durch die Umhüllung mit einem vorzugsweise als ein Metall mit einem geringen spezifischen Widerstand ausgebildeten Material (hier Kupferschicht 20) wird die Stromtragfähigkeit auch bei geringerem Bonddrahtdurchmesser erhöht. Es kann sich auch die Zuverlässigkeit der Verbindung des Bonddrahtes zu Kontaktflächen oder Anschlussflächen verbessern.The size specifications for the IGBT mentioned above in the description of FIG 13 correspond to the state of the art. However, it is essential to the invention that, according to the invention, the bonding wire can be made thinner or, in the extreme case, even made of a nonconductor. By wrapping with a preferably formed as a metal with a low resistivity material (here copper layer 20 ), the current carrying capacity is increased even with a smaller bond wire diameter. It may also improve the reliability of the connection of the bonding wire to contact surfaces or pads.

So ermöglicht die erfindungsgemäße Lösung auch zuverlässige Bonddrahtverbindungen bei höheren Sperrschichttemperaturen, wie sie bei Leistungs-Halbleiterbaulementen neuer Generationen vorgesehen sind.Thus, the solution according to the invention also enables reliable bonding wire connections at higher junction temperatures, as provided in power semiconductor devices of new generations.

BezugszeichenlisteLIST OF REFERENCE NUMBERS

11
Leistungs-HalbleitermodulPower semiconductor module
1111
Trägersubstratcarrier substrate
1212
Metallschichtmetal layer
1313
IGBT (Insulated Gate Bipolar Transistor)IGBT (Insulated Gate Bipolar Transistor)
13e13e
Emitter-AnschlussflächeEmitter pad
13g13g
Gate-AnschlussflächeGate pad
1414
Lotschichtsolder layer
1515
Kollektor-KontaktflächeCollector contact surface
1616
Emitter-KontaktflächeEmitter contact area
1717
Gate-KontaktflächeGate pad
1818
Emitter-BonddrahtEmitter bonding wire
1919
Gate-BonddrahtGate bonding wire
2020
Kupferschichtcopper layer

Claims (15)

Verfahren zur Herstellung eines Leistungs-Halbleitermoduls (1), das mindestens ein auf einem Trägersubstrat (11) angeordnetes Leistungs-Halbleiterbauelement (13) mit von dem Trägersubstrat (11) abgewandten Anschlussflächen (13e, 13g) umfasst, wobei das Trägersubstrat (11) Kontaktflächen (16, 17) und Leiterbahnen umfasst, wobei die Anschlussflächen (13e, 13g) mittels Bonddrähten (18, 19) aus einem ersten Material mit den Kontaktflächen (16, 17) stoffschlüssig verbunden sind, dadurch gekennzeichnet, dass auf den Anschlussflächen (13e, 13g) und den Bonddrähten (18, 19) eine von dem ersten Material verschiedene Schicht (20) aus einem elektrisch leitfähigen zweiten Material abgeschieden wird.Method for producing a power semiconductor module ( 1 ), which at least one on a carrier substrate ( 11 ) power semiconductor device ( 13 ) with the carrier substrate ( 11 ) facing away pads ( 13e . 13g ), wherein the carrier substrate ( 11 ) Contact surfaces ( 16 . 17 ) and tracks, wherein the pads ( 13e . 13g ) by means of bonding wires ( 18 . 19 ) of a first material with the contact surfaces ( 16 . 17 ) are materially connected, characterized in that on the connecting surfaces ( 13e . 13g ) and the bonding wires ( 18 . 19 ) a layer different from the first material ( 20 ) is deposited from an electrically conductive second material. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass weiter auf den Kontaktflächen (16, 17) die von dem ersten Material verschiedene Schicht (20) aus dem elektrisch leitfähigen zweiten Material abgeschieden wird.Method according to claim 1, characterized in that further on the contact surfaces ( 16 . 17 ) the layer different from the first material ( 20 ) is deposited from the electrically conductive second material. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass das elektrisch leitfähige zweite Material aus einer Gruppe gebildet ist, die die Metalle Kupfer, Silber und Gold sowie Legierungen, die mit einem oder mehreren dieser Metalle gebildet sind, umfasst.A method according to claim 1 or 2, characterized in that the electrically conductive second material is formed from a group comprising the metals copper, silver and gold and alloys formed with one or more of these metals. Verfahren nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, dass die Schicht (20) aus dem elektrisch leitfähigen zweiten Material galvanisch aufgebracht wird.Method according to one of claims 1 to 3, characterized in that the layer ( 20 ) is applied galvanically from the electrically conductive second material. Verfahren nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, dass die Schicht (20) aus dem elektrisch leitfähigen zweiten Material durch physikalische Gasphasenabscheidung aufgebracht wird.Method according to one of claims 1 to 3, characterized in that the layer ( 20 ) is applied from the electrically conductive second material by physical vapor deposition. Verfahren nach Anspruch 5, dadurch gekennzeichnet, dass die Schicht (20) aus dem elektrisch leitfähigen zweiten Material durch Kathodenzerstäubung aufgebracht wird.Method according to claim 5, characterized in that the layer ( 20 ) is applied from the electrically conductive second material by sputtering. Verfahren nach Anspruch 6, dadurch gekennzeichnet, dass die Schicht (20) aus dem elektrisch leitfähigen zweiten Material durch DC-Dioden-Sputtern aufgebracht wird.Method according to claim 6, characterized in that the layer ( 20 ) is applied from the electrically conductive second material by DC diode sputtering. Verfahren nach Anspruch 5, dadurch gekennzeichnet, dass die Schicht (20) aus dem elektrisch leitfähigen zweiten Material durch Ionenplattieren aufgebracht wird.Method according to claim 5, characterized in that the layer ( 20 ) is applied from the electrically conductive second material by ion plating. Verfahren nach Anspruch 5, dadurch gekennzeichnet, dass die Schicht (20) aus dem zweiten Material durch thermisches Verdampfen aufgebracht wird.Method according to claim 5, characterized in that the layer ( 20 ) is applied from the second material by thermal evaporation. Verfahren nach Anspruch 9, dadurch gekennzeichnet, dass die Schicht (20) aus dem elektrisch leitfähigen zweiten Material durch Clusterstrahltechnik aufgebracht wird.Method according to claim 9, characterized in that the layer ( 20 ) is applied from the electrically conductive second material by cluster beam technology. Leistungs-Halbleitermodul (1), das mindestens ein auf einem Trägersubstrat (11) angeordnetes Leistungs-Halbleiterbauelement (13) mit von dem Trägersubstrat (11) abgewandten Anschlussflächen (13e, 13g) umfasst, wobei das Trägersubstrat (11) Kontaktflächen (16, 17) und Leiterbahnen umfasst, wobei die Anschlussflächen (13e, 13g) mittels Bonddrähten (18, 19) aus einem ersten Material mit den Kontaktflächen (16, 17) stoffschlüssig verbunden sind, dadurch gekennzeichnet, dass auf den Anschlussflächen (13e, 13g) und den Bonddrähten (18, 19) eine von dem ersten Material verschiedene Schicht (20) aus einem elektrisch leitfähigen zweiten Material aufgebracht ist.Power semiconductor module ( 1 ), which at least one on a carrier substrate ( 11 ) power semiconductor device ( 13 ) with the carrier substrate ( 11 ) facing away pads ( 13e . 13g ), wherein the carrier substrate ( 11 ) Contact surfaces ( 16 . 17 ) and tracks, wherein the pads ( 13e . 13g ) by means of bonding wires ( 18 . 19 ) of a first material with the contact surfaces ( 16 . 17 ) are materially connected, characterized in that on the connecting surfaces ( 13e . 13g ) and the bonding wires ( 18 . 19 ) a layer different from the first material ( 20 ) is applied from an electrically conductive second material. Leistungs-Halbleitermodul nach Anspruch 11, dadurch gekennzeichnet, dass auf den Kontaktflächen (16, 17) zumindest bereichsweise die von dem ersten Material verschiedene Schicht (20) aus dem elektrisch leitfähigen zweiten Material aufgebracht ist.Power semiconductor module according to claim 11, characterized in that on the contact surfaces ( 16 . 17 ) at least in regions, the different layer of the first material ( 20 ) is applied from the electrically conductive second material. Leistungs-Halbleitermodul nach Anspruch 11 oder 12, dadurch gekennzeichnet, dass das erste Material aus einer Gruppe gebildet ist, die Aluminium sowie Aluminium-Legierungen umfasst.Power semiconductor module according to claim 11 or 12, characterized in that the first material is formed from a group comprising aluminum and aluminum alloys. Leistungs-Halbleitermodul nach einem der Ansprüche 11 bis 13, dadurch gekennzeichnet, dass die Schicht (20) aus dem elektrisch leitfähigen zweiten Material eine Dicke im Bereich von 0,2 μm bis 20 μm, vorzugsweise im Bereich von 0,5 μm bis 3 μm, aufweist.Power semiconductor module according to one of Claims 11 to 13, characterized in that the layer ( 20 ) of the electrically conductive second material has a thickness in the range of 0.2 .mu.m to 20 .mu.m, preferably in the range of 0.5 .mu.m to 3 .mu.m. Leistungs-Halbleitermodul nach einem der Ansprüche 10 bis 14, dadurch gekennzeichnet, dass das elektrisch leitfähige zweite Material aus einer Gruppe gebildet ist, die die Metalle Kupfer, Silber und Gold sowie Legierungen, die mit einem oder mehreren dieser Metalle gebildet sind, umfasst.A power semiconductor module according to any one of claims 10 to 14, characterized in that the electrically conductive second material is formed from a group comprising the metals copper, silver and gold and alloys formed with one or more of these metals.
DE102011111032A 2011-08-19 2011-08-19 Method for manufacturing power-semiconductor module, involves copper layer made of electrically conductive material differs from material and isolated on connecting surfaces and bonding wires Withdrawn DE102011111032A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE102011111032A DE102011111032A1 (en) 2011-08-19 2011-08-19 Method for manufacturing power-semiconductor module, involves copper layer made of electrically conductive material differs from material and isolated on connecting surfaces and bonding wires

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102011111032A DE102011111032A1 (en) 2011-08-19 2011-08-19 Method for manufacturing power-semiconductor module, involves copper layer made of electrically conductive material differs from material and isolated on connecting surfaces and bonding wires

Publications (1)

Publication Number Publication Date
DE102011111032A1 true DE102011111032A1 (en) 2013-02-21

Family

ID=47625283

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102011111032A Withdrawn DE102011111032A1 (en) 2011-08-19 2011-08-19 Method for manufacturing power-semiconductor module, involves copper layer made of electrically conductive material differs from material and isolated on connecting surfaces and bonding wires

Country Status (1)

Country Link
DE (1) DE102011111032A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016107287A1 (en) 2016-04-20 2017-11-09 Semikron Elektronik Gmbh & Co. Kg Power semiconductor device and method for operating a power semiconductor device
CN112313781A (en) * 2018-06-27 2021-02-02 三菱电机株式会社 Power module, method for manufacturing same, and power conversion device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7656034B2 (en) * 2007-09-14 2010-02-02 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7656034B2 (en) * 2007-09-14 2010-02-02 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016107287A1 (en) 2016-04-20 2017-11-09 Semikron Elektronik Gmbh & Co. Kg Power semiconductor device and method for operating a power semiconductor device
CN112313781A (en) * 2018-06-27 2021-02-02 三菱电机株式会社 Power module, method for manufacturing same, and power conversion device
CN112313781B (en) * 2018-06-27 2024-05-24 三菱电机株式会社 Power module, method for manufacturing the same, and power conversion device

Similar Documents

Publication Publication Date Title
EP3704770A1 (en) Diode laser
DE102007027378A1 (en) Connection arrangement, has galvanically applied metallic layer extending between main surfaces and electrically connecting main surfaces, and spacer unit arranged in recess to space main surface from another main surface
DE102016212506A1 (en) Semiconductor device and method of manufacturing a semiconductor device
DE102014105000B4 (en) Method for manufacturing and equipping a circuit carrier
DE102014119386B4 (en) Method for producing a metal-ceramic substrate and associated metal-ceramic substrate
DE3638799C2 (en)
DE102015114521B4 (en) Method for soldering an insulating substrate onto a carrier
DE102015210061A1 (en) Method for electrical contacting of a component and component module
DE102011111032A1 (en) Method for manufacturing power-semiconductor module, involves copper layer made of electrically conductive material differs from material and isolated on connecting surfaces and bonding wires
DE102004027176A1 (en) Semiconductor device manufacturing method e.g. for diode, involves performing electro-less plating of nickel on aluminum electrode, after forming insulation film on open electrode
WO2020043863A1 (en) Method for producing conductive tracks, and electronic module
DE102004055534B4 (en) Power semiconductor module with an electrically insulating and thermally highly conductive layer
DE102015218842A1 (en) Method for contacting a contact surface of a semiconductor device and electronic module
WO2019063533A1 (en) Component, and method for the production thereof
DE102012110261A1 (en) Housing for an optoelectronic component and method for producing a housing
DE102010025311A1 (en) Formation of metallic layer on ceramic substrate or ceramic layer, involves melting interfacial layer formed from eutectic mixture formed using oxide of metallic material and alumina, on ceramic substrate or ceramic layer
DE10259292B4 (en) Method for producing a uniform contact and uniform contact made therewith
EP0143244B1 (en) Contact electrode for power semiconductor components
DE1283969B (en) Semiconductor component with an electrically insulating intermediate body between the semiconductor body and a housing part, and a method for its manufacture
DE102019211333A1 (en) Method for producing a conductor track, for producing an electronic module and electronic module
DE102004002743A1 (en) Cooling body for power electronics especially in automotive field has a thick coating of ceramic or hard material applied by thermal spraying or vapor deposition
EP0581152B1 (en) Method of manufacture of a multichip module using bump contacts
DE102004041417B4 (en) Electrical arrangement for microelectronics has component insulated from substrate by dielectric layer on conductive substrate
DE3106212A1 (en) Heat sink for a semiconductor cell, in particular a solar cell
DE102013114438A1 (en) Power electronics module and method for producing a power electronics module

Legal Events

Date Code Title Description
R012 Request for examination validly filed
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20140301