DE102011101172A1 - Method for multi-address recognition in actuator sensor interface network, involves releasing switching or warning signal during overlapping of response signals, arranging recognition logic in slaves for recognizing multi-addressing - Google Patents

Abstract

The method involves assigning a binary address to an addressing of slaves. A multi-addressing of the two slaves is recognized by a monitoring device. A switching or warning signal is released during overlapping of response signals of the two slaves. A recognition logic is arranged in the slaves, where the multi-addressing is recognized by the recognition logic. Transmission of one of the slaves to a master is stopped within an arbitrary preset time. A counter is associated to the slaves, where a number of calls of the master to the slaves is counted by the counter. An independent claim is also included for an actuator sensor (AS) interface network.

Description

The invention relates to an actuator-sensor interface system with a multiple address detection in such an AS-Interface network.

When setting up AS-Interface systems, the slaves to be connected are assigned an address manually when they are installed. With this assignment, there is a risk that the same address will be assigned to different slaves by mistake. In this case there is an unintentional multiple addressing.

On the other hand, the slaves are correctly set up if each slave exchanges data with the master in the time window assigned to it alone. All other slaves should not execute their own data traffic within this time window.

An undesired multiple addressing is present when in this time window not only the responsible slave exchanges data with the master, but a faulty with the same address equipped second or third slave. The master can then no longer distinguish which slave has sent.

Multiple addressing in AS-Interface networks (2 or more slaves have the same address incorrectly) therefore represent a danger to safe operation because they can not be reliably detected by the components involved (master, slave) according to the state of the art.

Currently, several solutions are known for the detection of multiple addressing:
The EP 1 312 991 B1 or DE 102 53 566 A1 measure the current that is taken from the power supply. If two slaves transmit undesirably at the same time, then the transmission current is increased. However, this method fails, for example, when a slave is placed in front of a repeater and the other slave is placed at the same address after a repeater, because then there is no increased current that could be detected. Thus, the method can not cover all cases occurring in reality safely.

The DE 10 20007 025 852 B3 is similar, except that not the transmission current is measured, but the impedance. This method also fails if one slave is arranged in front of a repeater and the other slave with the same address after a repeater.

The DE 10 2009 033 229 A1 is an evolution of the EP 1 312 991 B1 or the DE 102 53 566 A1 , is based on the same principle of recognition, and can therefore the mentioned disadvantage of EP 1 312 991 B1 or DE 102 53 566 A1 also do not eliminate.

Further attempts to avoid multiple addressing are known. They are based on the principle of preventing the occurrence of multiple addressing, such as by storing the network configuration in an addressing device. This method is also not suitable for reliably preventing multiple addressing, because it is always possible to connect an already incorrectly addressed slave to the network.

It is therefore an object of the invention to provide a method with which under all circumstances and in all conceivable configurations a multiple addressing can be detected and reported to the user.

The solution of the problem is achieved by the technical teaching of claim 1. Furthermore, the solution of the teaching is carried out by a slave configuration according to the independent claim. 8

An essential feature of the invention is that a novel technical features of a slave is given. Each slave is assigned according to the invention a recognition logic that recognizes a multiple addressing. This is new compared to the prior art, because there was the monitoring device to determine the multiple addressing either in the master or in a separate instance of the network. According to the detection logic for detecting a multiple addressing in the slave is now arranged.

A method for realizing the technical teaching of claim 1 consists essentially in the fact that each slave within an arbitrary predetermined time, which is adjustable by certain parameters, his transmission to the master sets and - although he would be entitled to a broadcast - does not broadcast a program but that he listens in this time window, the bus line and determines whether - illegally - sends another identically addressed slave in the time window of the intercepting slave.

In this case, there is an undesirable multiple addressing. As soon as the slave monitoring the bus line in its allocated time window detects the bus traffic of another identically addressed slave, it sets a status flag and / or sets its address to 0 and / or optionally issues an error message.

However, if no other slave is transmitting on the bus line during the listening period of the respective slave, then there is no case of multiple addressing and the slave listening on the bus line resets his counter and resumes his intended traffic with the master.

In normal operation, the slave sends its response to the master, with z. B. the timing is selected in normal operation so that, for example, 100 or 200 or 1000 emissions to the master from the side of the slave made and counted from his counter. During normal operation of the bus traffic between master and slave, therefore, a counter associated with each slave runs, which is incremented. In this counter, a specific start time is defined, which starts the listening phase of the slave after about 100 or 200 or 1000 transmissions to the master.

It is important that each slave individually for himself at completely different times - as comparatively other slaves - its Abhörphase depending on the count of Inkrementalzählers initiates and as soon as this start time is reached, he renounces his intended due due transmission to the master and listens instead the bus line off. He hears in this - only for him defined time window - from the bus line, whether not in this - reserved only for him period - illegally another slave sends. If this is the case, there is an undesirable multiple addressing.

The invention thus consists of the following features:

1. Multiple address detection

The multi-address recognition is carried out according to the teachings of the invention not in the master or another central network component, but in the slave. At z. B. each 100th, 200th or 1000th master call to its slave address does not answer the slave with inventive multi-address detection, but listening to the network, if possibly another slave (or more slaves) respond to exactly this call also responds.

It is only important that the slave response of the other slave (s) fall into the designated slave response window and not whether the other slave responds a little earlier, exactly at the same time or slightly later than the slave with multiple address detection. If a valid slave response of another slave falls within the time slot, then there is clearly a multiple address in that network.

If there is no multiple addressing, then the inventive method generates a certain artificial additional telegram repetition rate and thus a slightly increased telegram error number. It is therefore part of the teaching of this invention to perform the multiple address detection by not responding to a telegram not in data telegrams, but only in the cyclically repeated organizational telegrams (such as "Read ID code").

Telegram errors in these organizational calls are not considered as errors in most masters and diagnostic devices and are therefore not registered.

If, for example, every 200th "Read-ID-Code" telegram of the master would be used for multiple address recognition in a fully occupied network, then this would be recognized after one minute at the latest.

To reduce the risk that two similar slaves in the network at the same time suppress their slave response to perform the multi-address recognition described above, the multi-address recognition at irregular intervals, for. B. controlled by a random generator or depending on the operating voltage applied to the slave done.

2. Message of multiple addressing

If the slave has detected multiple addressing, it can display it locally (for example, by a red flashing LED) and withdraw from the active data exchange. At the same time, the slave with multiple address detection can set a flag in the status register. It is also conceivable that the slave, which has recognized a multiple addressing, deletes its own address. Thus, the master is alerted in any case, because in a normal network no slave with address 0 may occur. By evaluating the status flags, the master or the user can clearly identify the reason why the slave has redirected to the address 0. The deletion of the address should preferably not be permanent, so that the user can possibly reconstruct at which address the multiple addressing conflict has occurred.

It is possible that in this method only one of the two slaves sharing the same address in the network is readdressed to the address 0. Once this is done, the problem of multiple addressing no longer exists.

If the addressing conflict is not remedied by the user, then the multiple address recognition is repeated again after every voltage return.

• 1 Das vorgeschlagene Verfahren funktioniert in allen Netzwerken und Konfigurationen, auch solchen, die einen oder mehrere Repeater enthalten, zuverlässig und sicher.
• 2 Das Verfahren benötigt keine besonderen Master oder Netzteile, es funktioniert bei allen bisherigen und zukünftigen Master- und Netzteiltypen.
• 3 Das vorgeschlagene Verfahren funktioniert auch dann zuverlässig, wenn mehr als 2 Slaves in einem Netzwerk die gleiche Adresse aufweisen. Allerdings dauert die Erkennung dann entsprechend länger.
• 4 Das Verfahren funktioniert auch dann, wenn nur einer von zwei Slaves, die die gleiche Adresse aufweisen, mit der beschriebenen Funktion der Mehrfachadresserkennung ausgestattet ist. Es ist also auch in Netzwerken, in denen nicht alle Slaves mit dieser Funktion ausgestattet sind, bereits sinnvoll einsetzbar. In diesem Falle würde natürlich nur einer der beiden Slaves seine Adresse auf 0 ändern.

The advantages of the method compared to the prior art are summarized the following:

• 1 The proposed method works reliably and securely in all networks and configurations, including those containing one or more repeaters.
• 2 The process does not need special masters or power supplies; it works with all previous and future master and power supply types.
• 3 The proposed method works reliably even if more than 2 slaves in a network have the same address. However, the detection then takes longer.
• 4 The procedure works even if only one of two slaves with the same address is equipped with the described multi-address recognition function. So it is already useful in networks where not all slaves are equipped with this feature. In this case, of course, only one of the two slaves would change its address to 0.

The subject of the present invention results not only from the subject matter of the individual claims, but also from the combination of the individual claims with each other.

All information and features disclosed in the documents, including the abstract, in particular the spatial design shown in the drawings, are claimed to be essential to the invention insofar as they are novel individually or in combination with respect to the prior art.

In the following the invention will be explained in more detail with reference to drawings showing only one embodiment. Here are from the drawings and their description further features essential to the invention and advantages of the invention.

Show it:

1 : Schematic block diagram of an AS-Interface network with the case of double addressing of 2 slaves

2 : Program flowchart of a recognition logic, which is preferably assigned to each slave for the detection of multiple addresses

3 : An amplitude-time diagram showing a master call and a subsequent slave response in conjunction with the digital master information and the resulting slave information for the slave

In 1 a conventional AS-Interface network is shown, which essentially consists of a power supply 1 that exists over primary lines 2 . 3 connected to an energy source.

To the electricity supplier 1 close in a conventional manner, the bus lines 4 . 5 an actuator-sensor interface system in which at least one master 6 and a variety of slaves 7 . 8th . 9 are connected.

In the illustrated embodiment, it is shown that the slaves 7 . 8th have to be avoided multiple addressing.

For this it is shown that the address block 10 of the slave 7 and the address block 11 of the slave 8th each from a z. B. from 5-bit-wide slave address 13 exist and still add an address 14 is present in the form of a select bit.

As an accident of multiple addressing shows the 1 now that the address block 10 and 11 has the same digital information, resulting in a forbidden multiple addressing, which is avoided in the context of the present invention.

In a multiple addressing, so if the address blocks 10 and 11 are identical, send both slaves 7 . 8th in a forbidden way simultaneously in the direction of the arrow 15 their information to the master 6 back, and this can not determine which slave 7 or 8th just sent.

According to the invention, this fault should now be avoided by virtue of preferably each slave 7 . 8th . 9 its own recognition logic 16 is assigned, whose structure in 2 is explained in more detail.

In the context of the present invention, however, it is not necessary for the solution that each slave 7 . 8th . 9 such a recognition logic 16 having. It may also be sufficient for one or more slaves to have such recognition logic. Therefore, z. B. the slaves no recognition logic 16 be assigned, in which the risk of multiple addressing is not present.

The invention consists in that in the recognition logic 16 having slaves 7 . 8th the recognition logic 16 after the flowchart after 2 is working.

Starting with the starting block 17 the process is triggered and it is sent to the slave after receiving a master call 22 in the block 18 a counter increments (counts up).

The counter is incremented whenever a master call is made to the slave.

If a certain counter reading is reached, if z. For example, if 50, 100, or 1000 master calls to the slave have occurred, this will be in block 19 detected.

As long as the master calls have not yet led to the meter reading, it will go over the branch 46 the slave is triggered and sets its slave response as intended 28 in the block 41 to the master.

However, once the counter has reached a certain count that z. For example, if 100 master calls resulted in 100 slave responses of that particular slave, the branch becomes 47 in the block 19 go through and the slave is in the block 20 causes it to suppress its actually required slave response and instead (according to the block 40 ) the bus line 4 . 5 abzuhorchen.

During this period, in which he suppresses his slave response to the master, he instead hears the line (in the block 40 ) and determines if another slave has illegally sent during this period.

If this is in the block 21 is determined is on the branch 48 branched, because then the case of a double addressing exists. As a result, in the blocks 42 to 45 a status flag is set in the slave, and various possibilities are indicated for the display of such a fault, all of which are alternatively connected to each other by AND or optionally by OR-links with each other.

Either can in the block 42 a local LED placed in the slave can be displayed, and / or it can be in the slave in the block 43 a flag can be set in the status register, and / or it can be in the block 44 the setting of traffic to the master can be done, and / or it can be in the block 45 the slave address is set to 0.

All of the aforementioned options can thus be realized cumulatively or individually taken for themselves.

At the exit of the block 45 then is the end in the block 51 reached, and there is an intervention of the user is necessary because it can be found that the double addressing causing slave.

If, however, a double addressing in the block 21 is not detected in the transmission pause of the monitoring slave, it goes over the branch 52 in the block 53 continue, in which the counter is reset and a new process over the branch 54 to the reception block 22 he follows.

In 3 is the amplitude-time diagram of a master call 24 shown.

The Master Call consists of a pause and a series of positive and negative impulses 25 . 26 , which as digital translation the master information 31 contain appropriate digital information.

This master information 31 consists of a start bit 33 , a tax bill 34 , a 5-bit-wide slave address 13 (please refer 1 ) and an adjoining digital control information 35 ,

Conversely, the slave responds with its slave response 28 after going through a break 27 , where this slave response also consists of a series of positive and negative pulses 29 . 30 consists.

As a digital slave answer 32 the response diagram consists of a start bit 36 , a 4-bit-wide slave information 37 , a parity bit 38 and an end bit 39 ,

Important in the present invention is that a plurality of slaves a recognition logic 16 is assigned, which suppresses the slave response after a predetermined number of master calls and instead listening to the bus line and determines whether in the listening slave this time allocated another slave prohibited manner on the bus line sends.

Upon detection of this fault in the detection logic according to the invention then the aforementioned processes according to 2 (right branch) completed.

However, when a fault (multiple addressing) is displayed on a slave, it is not yet possible to decide which slave has generated the undesired multiple addressing. This can only be detected by the user himself by carrying out appropriate tests.

The error state of the multiple addressing of slaves can then be changed by changing the slave address permanently assigned by the user by readdressing the slave.

LIST OF REFERENCE NUMBERS

1

power supply

2

primary line

3

primary line

4

bus line

5

bus line

6

master

7

slave

8th

slave

9

slave

10

address block

11

address block

12

address block

13

Slave address

14

Address supplement (Select bit)

15

arrow

16

recognition logic

17

starting block

18

block

19

block

20

block

21

block

22

block

23

24

Master call

25

pulse

26

pulse

27

Break

28

Slave response

29

pulse

30

pulse

31

Master information

32

Slave response

33

start bit

34

control bit

35

tax information

36

start bit

37

Slave information

38

Parity bit

39

End Bit

40

block

41

block

42

block

43

block

44

block

45

block

46

branch

47

branch

48

branch

49

50

51

block

52

branch

53

block

54

branch

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• EP 1312991 B1 [0006, 0008, 0008]
• DE 10253566 A1 [0006, 0008, 0008]
• DE 20007025852 B3 [0007]
• DE 102009033229 A1 [0008]

Claims (10)

Method for multiple address recognition in AS-Interface networks with at least one to a bus line ( 4 . 5 ) connected master ( 6 ) and at least two connected slaves ( 7 - 9 ), each slave ( 7 - 9 ) a binary address ( 13 ) is assigned to its addressing, and a monitoring device for detecting a multiple addressing of at least two slaves is present, which triggers a switch or warning signal when superimposing the response signals of at least two slaves, characterized in that in at least one slave ( 7 - 9 ) a recognition logic ( 16 ), which recognizes a multiple addressing. Method according to Claim 1, characterized in that, to detect the multiple addressing, a specific slave ( 7 - 9 ) within an arbitrarily given time, which can be set by certain parameters, its transmission to the master ( 6 ) and that in this time window the bus line ( 4 . 5 ) and determines whether another slave is transmitting in the time window of the intercepting slave. Method according to claim 1 or 2, characterized in that as soon as the slave listening in its allocated time window detects a bus traffic of another slave it sets a status flag and / or sets its address to 0 and / or optionally outputs an error message and / or the Set traffic to the master. Method according to one of claims 1 to 3, characterized in that the slave ( 7 - 9 ) a separate counter (block 18 ), which determines the number of master calls to the master ( 6 ) to the slave ( 7 - 9 ) and that when a predefinable number of master calls is reached, the slave suppresses its transmission to the master and instead the bus line ( 4 . 5 ) listens to the transmission of another slave with the same address. Method according to one of Claims 1 to 4, characterized in that the multiple address recognition by non-response of a master telegram is not effected with data telegrams of the master, but with cyclically repeated organizational telegrams (eg "Read ID code"). Method according to one of claims 1 to 5, characterized in that to reduce the risk that two similar slaves ( 7 - 9 ) in the network ( 4 . 5 ) at exactly the same time suppress their slave response, the multiple address detection at irregular intervals, eg. B. controlled by a random number generator or depending on the voltage applied to the slave operating voltage occurs. Method according to one of claims 1 to 6, characterized in that when detecting a multiple address detection, the slave operates according to one or more of the following states: local fault indication on the slave and / or Setting the data traffic with the master and / or Set a flag in the status register and / or Delete his own address. AS-Interface network with multiple address detection with at least one to a bus line ( 4 . 5 ) connected master ( 6 ) and at least two connected slaves ( 7 - 9 ), each slave ( 7 - 9 ) a binary address ( 13 ) is assigned to its addressing, and a monitoring device for detecting a multiple addressing of at least two slaves is present, which in superposition of the response signals of at least two slaves ( 7 - 9 ) triggers a switching or warning signal, characterized in that the as recognition logic ( 16 ) trained monitoring device in the slave ( 7 - 9 ) is arranged. AS-Interface network according to claim 8, characterized in that the recognition logic ( 16 ) in the slave ( 7 - 9 ) consists of an incremental counter, which counts the master calls, which, when a predefinable counter reading has been reached, receives the slave response to the master ( 6 ) and that the recognition logic ( 16 ) instead the bus line ( 4 . 5 ) listens for another slave ( 7 - 9 ) also responds to this call and that if the slave response of another slave falls within the time window, a switching signal can be generated as a criterion of multiple addressing. AS-Interface according to one of claims 8 to 9 for carrying out the method according to at least one or more of claims 1 to 7, characterized in that in the slave ( 7 - 9 ) arranged incremental counter exclusively recognizes the transmitted by the master organizational data telegrams (eg Read ID code) and counts.

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