DE102011087133B4 - Device and method for monitoring global pixel control - Google Patents

Abstract

Semiconductor component with a pixel array (200) which, for global control of the pixels (201.1 -.20) of the pixel array (200), switching signal lines (210.1 - 210.4, 211.1 - 211.4) for the control of reset and hold switches (210s, 211s) These switching signal lines (210.1-210.4, 211.1-211.4), which are assigned to a specific global control function (210, 211), on an output side (220.1-220.4, 221.1-221.4) of the pixel array (200) with comparison logic (300 ) are connected, the comparison logic (300) being designed such that an error signal is generated if the outputs of the switching signal lines have different switching signals, and the comparison logic (300) consists of at least one AND gate (310, 311), an OR Gate (320, 321) and an XOR gate (330, 331) is formed, wherein the at least one AND gate (310, 311) and the at least one OR gate (320, 321) have an additional input, which in a test mod us can be supplied with a test signal.

Description

The invention is based on a semiconductor component with a pixel array for detecting light signals, which has switching signal lines for global control of the pixels of the pixel array, and a method for operating such a pixel array according to the type of the independent claims.

Such pixel arrays are, for example, from the DE 602 04 968 T2 for capturing light signals or image information or from the DE 197 04 496 already known for capturing depth information. Thus, the invention is particularly suitable for time-of-flight cameras that use, for example, a photosensor or pixel array based on the PMD principle.

Furthermore, the publication "Ull, Dominik: Structural Field Tests of Complex ASICs, University of Stuttgart, Institute for Technical Computer Science, Diploma Thesis No. 3146, August 2011, Suttgart: Uni Stuttgart, 2011" generally describes the procedure for a typical Build In Soap Test (BIST) described. In this context, reference is made in particular to so-called concurrent tests, which can also be carried out online during normal system operation.

From the WO 2008/027 193 A2 In principle, an image sensor is known in which the outputs of the columns of the pixel array are connected to a comparator circuit. The output signal of this circuit is used to reset the pixel and to determine a value for the floating diffusion region.

The global activation of the switches or functions in the individual pixels of the pixel array can be disturbed under certain circumstances and leads to incorrect behavior of the individual pixels and, as a result, to an incorrect reading of the image or depth information from the pixel array, which is not necessarily caused by a subsequent image processing or evaluation can be recognized.

The object of the invention is to improve the reliability of the pixel information.

The object is advantageously achieved by the independent claims.

A semiconductor component with a pixel array is advantageously provided, which has switching signal lines for global control of the pixels of the pixel array, the switching signal lines, which are assigned to a specific global control function, being connected to comparison logic on an output side of the pixel array. This procedure ensures that errors in the global control or in the pixel array are reliably detected.

The comparison logic is preferably designed such that an error signal is generated if the outputs of the switching signal lines have different switching signals, in a typical embodiment the comparison logic having at least one logic gate and / or at least one inverting logic gate.

The comparison logic is preferably formed from at least one AND gate, an OR gate and an XOR gate, the inputs of the AND gate and the OR gate with the switching signal line outputs and the two inputs of the XOR gate with the outputs of the AND Gate and the OR gate are connected. Such a construction allows an error signal to be signaled whenever the signal lines of one type of control led to the inputs of the comparison logic have different and thus disturbed signals.

In a further preferred embodiment, a test module is provided which is connected to the pixel array and / or the comparison module such that test signals are present in a test mode at the input of the comparison logic. It is thus advantageously possible to check the functionality of the comparison logic and to further increase the security of the monitoring.

A signal manipulator is preferably arranged at the input or output of the pixel array, via which the test module can introduce signals in the signal line path. Different test signals that stimulate certain signals at the output of the comparison logic can be introduced into the system to be monitored in a simple manner via the signal manipulator.

A method for operating the above-mentioned semiconductor component is also advantageously provided, in which a switching signal for global control of the pixel array is first generated, followed by detection and comparison of the switching signals of a control function on a plurality of switching signal lines on an output side of the pixel array, and then a Generate an error signal and initiate an error response if the detected and compared switching signals are unequal.

In a further embodiment of the method with a test module, it is provided that test signals are applied to at least one input of a logic gate in a test mode, the test signals being generated in such a way that at the output certain signals are to be expected from the logic gate. If the signal at the output deviates from the expected signal, an incorrect comparison logic is signaled.

The invention is explained in more detail below on the basis of exemplary embodiments with reference to the drawings.

• 1 eine aus dem Stand der Technik bekannte globale Ansteuerung eines Pixels in einem Pixelarray,
• 2 eine erfindungsgemäße Überwachung einer globalen Ansteuerung,
• 3 eine mögliche Verschaltung einer Vergleichslogik,
• 4 eine Vergleichslogik mit Testeingängen,
• 5 eine Anordnung mit einem Testmodul und ein Signalmanipulator,
• 6 eine Multiplexeranordnung als Signalmanipulator am Signalausgang des Pixelarrays,
• 7 eine Multiplexeranordnung am Signaleingang des Pixelarrays,
• 8 eine Vergleichslogik mit einem Gesamtfehler- und Diagnoseausgang,
• 9 eine Multiplexeranordnung mit einer gemeinsamen Busleitung.

They show schematically:

• 1 a global control of a pixel in a pixel array known from the prior art,
• 2 monitoring of a global control according to the invention,
• 3 a possible interconnection of a comparison logic,
• 4 a comparison logic with test inputs,
• 5 an arrangement with a test module and a signal manipulator,
• 6 a multiplexer arrangement as a signal manipulator at the signal output of the pixel array,
• 7 a multiplexer arrangement at the signal input of the pixel array,
• 8th a comparison logic with an overall error and diagnostic output,
• 9 a multiplexer arrangement with a common bus line.

In the following description of the preferred embodiments, the same reference symbols designate the same or comparable components.

1 shows schematically a single pixel 201.1 of a pixel array 200 , as it is basically for example from the DE 10 2009 028 352 A1 is known. The pixel 201.1 of the pixel array 200 has a photosensitive area 260 to generate charge carriers, a charge storage device 270 and an output circuit 280 on. These components are schematic as a photodiode 260 , as a capacitor 270 and as an output amplifier 280 shown. The output amplifier 280 can also be designed as a switch in a simple embodiment.

The photodiode 260 is via a reset switch 210s connectable with a potential so that a reproducible initial state can be established before a measurement. In a known manner, the reset switch is used during an exposure 210s opened and the photodiode 260 via a hold switch 211s with the capacitor 270 connected. After a desired integration time has elapsed, the hold switch is activated 211s opened so that on the capacitor 270 collected charges through the output circuit 280 can be called up by an evaluation unit. In the example shown, the pixel or the associated amplification circuit is used to read out the charge 280 via a line 230.1 and a column line 235.1 addressed. This addressing takes place, for example, via corresponding shift registers.

For controlling the reset and hold switches 210s . 211s are typically separate signal lines for each row of the pixel array 210.1 . 211.1 intended. The signal lines 210.1 . 211.1 are routed to a common entry point according to their switch assignment, so that the respective switching function can be controlled globally, that is to say for all pixels simultaneously, via a signal driver. In order to monitor the global control, the signals driven into the pixel array are provided on an output side 220.1 . 221.1 of the pixel array 200 for each signal line 210.1 . 211.1 to be tapped separately.

2 shows a device according to the invention with a plurality of parallel reset signal lines 210.1 - 210.4 , A signal generator 50 generates switching signals, for example, as a function of a predetermined program, with which, as described above, switches 210s . 211s in the pixel array 200 can be controlled globally. In the case shown, there is a reset switching signal 210 on four switching signal lines 210.1 - 210.4 of the pixel array 200 distributed. In order to provide sufficient current for the switching process, each switching signal line is 210.1 - 210.4 a signal driver 100 prefixed.

Within the pixel array 200 are the signal lines 210.1 - 210.4 as below 1 described in every pixel 201.1 - 201.20 with their assigned reset switch 210s connected. According to the invention, the switching signal lines are now provided 210.1 - 210.4 with switching signal line outputs 220.1 - 220.4 to provide and every exit 220.1 - 220.4 with a comparison logic 300 connect to.

The comparison logic 300 is preferably constructed such that an error is always registered or an error signal is generated when the signals at the outputs of the switching signal lines 220.1 - 220.4 have different signals.

In one possible embodiment, the switching signal driver could 100 for global control of the reset switch 210s For example, provide a voltage of 5 volts with sufficient current. This 5 In fault-free operation, volts are essentially also at the outputs 220 the respective switching signal line 210 can be tapped and are from the comparison logic 300 recognized as switch-on signal or as "Logical 1". In one A fault, for example in the event of a signal line break, appears at the output during a global switching process 220 the faulty signal line does not have a corresponding switching signal and thus corresponds to a "logical 0". The comparison logic 300 is preferably designed such that in the case of unequal logic states at the input of the comparison logic 300 an error signal is generated. No error signal is generated if either all inputs have a switch-on signal ( 1 ) or a switch-off signal ( 0 ) exhibit.

3 shows a possible embodiment for monitoring the global control of the pixel array 200 with a hold or reset signal. The reset and hold signals 210 . 211 are in the example shown from the left in the pixel array 200 driven and on several signal lines 210.1 - .4 ; 211.1 - .4 distributed and through the pixel array 200 looped through. At the right exit of the pixel array 200 become the outputs 220.1 - .4 . 221.1 - .4 of the signal lines 210 . 211 to different logic gates of the comparison logic 300 guided.

The exits 220.1 - 220.4 the reset signal lines 210.1 - 210.4 are on a first 301 and the exits 221.1 - 221-4 of the hold signal lines 211 to a second logic gate group 302 led so that a separate error signal can be generated for the respective global control.

In the first logic gate group 301 and in a corresponding manner for the second logic gate group 302 are the exits 220 . 221 of the signal lines 210 . 211 each in parallel on an AND gate 310 . 311 and in parallel on an OR gate 320 . 321 guided. The logic outputs of the AND and OR gates 310 . 311 ; 320 . 321 are in turn with an input of an XOR gate 330 . 331 connected. Such a logical combination ensures that it is always at the output of the XOR gate 330 . 331 a signal is present when the signal line outputs 220 . 221 have different switching signals or logic values.

4 shows a variant of the arrangement according to 3 where the AND gate 310 ' . 311 ' as well as the OR gates 320 ' . 321 ' have an additional input to which additional signals can be applied. A test signal can be applied to this input, for example in a test mode, which as a result provokes an error signal at the output.

In a further preferred variant, it can be provided that the additional inputs each directly with the driving reset or hold signal of the switching signal driver 100 connected is. This has the advantage that not only the consistency of the output signals of the signal lines 220.1 - .4, 221.1 - .4 among themselves, but also the consistency of the output signals with the driving input signal 210 . 211 can be compared.

5 shows a variant in addition to the comparison logic 300 a test module 500 and a signal manipulator 400 are provided. Without intervention by the test module 500 will, as already in 2 described, the global switching signal (hold, reset) using a switching signal driver 100 over several signal lines 210.1 - 210.4 into the pixel array 200 line by line and the signal line outputs 220.1 - 220.4 using the comparison logic 300 monitored for consistency in order to generate an error signal in the event of an error.

To check the functionality of the comparison logic 300 it is now provided according to the invention, between the output of the signal lines 220 . 221 and the comparison logic 300 a signal manipulator 400 to arrange. The test module acts in a test mode 500 via the signal manipulator 400 the inputs of the comparison logic 300 with predetermined test signals, and simultaneously monitors whether expected signals are present at an output of the comparison logic. Deviates the output signal of the comparison logic 300 from an expected value, error signals can be transmitted to a further control unit, for example as an error reaction. It is also conceivable via the test module 500 generate further test signals to localize the exact cause of the error.

6 shows a possible embodiment of a monitoring according to the invention with a signal manipulator 400 , The signal manipulator 400 is here from several multiplexers 410.1 - 410.4 . 411.1 - 411.4 built, with each signal output 220 . 221 a dedicated multiplexer is assigned. The single multiplexer 410 . 411 switches according to that on a test selection line 430 . 431 and a test bus line 420 . 421 signals present either on the signal outputs or on the test bus line 410 . 411 around. Via the test bus line 410 . 411 can use the multiplexers 410 . 411 subsequent inputs of the comparison logic 300 different logic signals for diagnosis and / or error analysis are made available. It is conceivable here to switch each multiplexer individually to the test bus, while the other multiplexers still have their assigned signal line outputs 210 . 211 are connected. It is also possible to remove all multiplexers from the signal line outputs 210 . 211 disconnect and connect to the test bus.

7 shows a variant in which the signal manipulator 400 is arranged on the input side of the signal lines. Here the signal manipulator switches 400 from the global switching signals in test mode to the test signals. By monitoring the output signals 300 In this arrangement, both the functionality of the pixel array 200 as well as that of the comparison logic 300 be checked.

8th shows a variant of the comparison logic 300 where the reset error and the hold error on a common OR gate 350 so that if an error occurs in the hold 211 or reset signal lines 210 a common error is issued. In addition, the outputs are the respective OR gates 320 . 321 on an XOR gate 360 guided. The exit 365 this gate 360 serves as a diagnostic output in such a way that there is no signal at the diagnostic output only if both Hold and Reset are not switched or both are switched through simultaneously. Based on the signal at the diagnostic output and at the error output, conclusions can be drawn about the exact cause of the error.

9 shows a variant of the structure according to 7 , in which the signals of the common test bus can optionally be connected to the multiplexers. In normal operation, the test bus is not switched to a signal.

Of course, the procedure according to the invention is not limited to the exemplary embodiments shown. In particular, the signal line can be routed not only in rows, but also in columns. It is also conceivable that the signal lines drive groups of pixels and an output line for this group of pixels is led to the outside. Likewise, the invention is not limited to the fact that the signal lines are led to the outside at the opposite end of the pixel array. The outputs of the signal lines can optionally also be routed to the outside on other sides of the pixel array and in particular can be fed back over one pixel line and over a subsequent pixel line, so that the input and output of the signal line lie on one side.

The comparison logic can also be set up with other gate structures, in particular it is also conceivable to set up the comparison logic as a programmable module and to carry out the error monitoring by means of program code.

• Alle Pixel einer Zeile oder Spalte des Pixelarrays 200 werden für eine globale Ansteuerung durch einen Treiber 100 gesteuert. Ein Kurzschluss innerhalb des Pixelarrays zu einer Versorgungsspannung wirkt sich auf alle Pixel der Zeile bzw. der entsprechenden Spalte aus. Eine Unterbrechung des Signals wirkt sich vor allem auf alle Pixel der Zeile bzw. Spalte aus, die vom Treiber aus gesehen der Unterbrechung nachfolgen. Erfindungsgemäß ist es vorgesehen, das Signal nicht nur von einer Seite in das Pixelarray 200 einzutreiben, sondern die Signalleitungen 210, 211 an der gegenüberliegenden Seite des Pixelarrays 200 herauszuführen, sodass alle eventuell vorhandenen Fehler auf der Signalleitung 210.1 - .4, 211.1 - .4 insbesondere Unterbrechung, auf der Ausgangsseite 220, 221 detektierbar sind.

Basically, the main idea can be summarized as follows:

• All pixels of a row or column of the pixel array 200 are used for global control by a driver 100 controlled. A short circuit within the pixel array to a supply voltage affects all pixels of the row or the corresponding column. An interruption in the signal affects above all all pixels in the row or column that follow the interruption from the driver's point of view. According to the invention, it is provided that the signal not only from one side into the pixel array 200 drive in, but the signal lines 210 . 211 on the opposite side of the pixel array 200 lead out, so that any possible errors on the signal line 210.1 - .4 . 211.1 - .4 especially interruption, on the exit side 220 . 221 are detectable.

An OR and a parallel AND operation of all similar digital signal outputs on the opposite side or output side can be used to check whether all signals carry the same information.

The logical links of all signal line outputs can be implemented as a tree, wired-OR / -AND link or accordingly. The AND link checks whether all signals are set. The OR link checks whether at least one signal is set. The system is only integral if both checks deliver the same result, otherwise an error can be assumed. The comparison of whether the two signals are the same can preferably be carried out using an XOR gate.

To check the comparison logic 300 , can be between the signal outputs 220 . 221 of the pixel array 200 and the comparison logic 300 signal manipulators 400 be arranged, which, as an alternative to the signals to be monitored, impress a test pattern or the like for simulating errors. Furthermore, test signals can also be integrated in the tree or structure of the logic gates in order to modify signals there in order to simulate errors. This procedure advantageously enables the comparison logic to function 300 to be checked in detail by further signal processing.

Additional logic gates can be provided for each additional global control signal.

Claims (5)

Semiconductor component with a pixel array (200) which, for global control of the pixels (201.1 -.20) of the pixel array (200), switching signal lines (210.1 - 210.4, 211.1 - 211.4) for the control of reset and hold switches (210s, 211s) These switching signal lines (210.1-210.4, 211.1-211.4), which are assigned to a specific global control function (210, 211), on an output side (220.1-220.4, 221.1-221.4) of the pixel array (200) with comparison logic (300 ) are connected, the comparison logic (300) being designed such that an error signal is generated if the outputs of the switching signal lines have different switching signals, and the comparison logic (300) consists of at least one AND gate (310, 311), an OR gate (320, 321) and an XOR gate (330, 331) is formed, the at least one AND gate (310, 311) and the at least one OR gate (320, 321) having an additional input which is in a test mode with a Test signal can be applied. Semiconductor device after Claim 1 , in which the inputs of the AND gate (310, 311) and the OR gate (320, 321) with the switching signal line outputs (220.1 - 220.4, 221.1 - 221.4) and the two inputs of the XOR gate (330, 331) with the outputs of the AND gate (310, 311) and the OR gate (320, 321) are connected. Semiconductor component according to one of the preceding claims, with a test module (500) which is connected to the pixel array (200) and / or the comparison module (300) such that test signals are present in a test mode at the input of the comparison logic (300). Semiconductor device after Claim 3 , in which a signal manipulator (400) is arranged at the input or at the output of the pixel array (200), via which the test module (500) can introduce signals into the signal line path. Method for operating a semiconductor component according to one of the preceding claims, comprising the steps: - Generation of a switching signal for global control of the pixel array - Detection and comparison of the switching signals of a control function (210, 220) on several switching signal lines (210.1 - 210.4, 211.1 - 211.4) on an output side (220.1 - 220.4, 221.1 - 221.4) of the pixel array (200), Generating an error signal and initiating an error reaction if the detected and compared switching signals are unequal and in which test signals are applied to at least one input of a logic gate in a test mode, the test signals are generated in such a way that certain signals are to be expected at the output of the logic gate, - If the signal at the output deviates from the expected signal, an incorrect comparison logic is signaled.

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