DE102011084473A1 - Method for symmetrizing memory cells of a memory device and memory system for carrying out the method - Google Patents

Abstract

The invention relates to a method for balancing memory cells (102a, 102b, 102c, 102n) of a memory device (102), which is set up for storing electrical and / or chemical energy, in particular for storing energy for a drive of a motor vehicle, wherein - charge states (214a, 214b, 214c, 214n) of the memory cells (102a, 102b, 102c, 102n) are determined and selected from the memory cells (102a, 102b, 102c, 102n) to be balanced cells and via discharge resistors (106a, 106b, 106c, 106n, 107a, 107b, 107c, 107n) of a heat-emitting element (103) are at least partially discharged, wherein the cells to be balanced are selected and / or so with the discharge resistors (106a, 106b, 106c, 106n, 107a, 107b, 107c, 107n ) are electrically connected so that a temperature of the heat-emitting element (103) does not exceed a maximum temperature (505). The invention further relates to a storage system (101) for carrying out the method.

Description

Motor vehicles, which are fully or partially electrically powered, are steadily increasing in importance. This is due to people's desire for mobility, the need to reduce CO ₂ emissions, and the limited supply of oil. Such vehicles have at least one electrostatic or electrochemical energy store, which is set up to supply a starter, a drive or the electrical system of the vehicle with electrical energy. Typically, such energy storage devices are designed in vehicles as batteries or as double-layer capacitors and comprise a plurality of memory cells, which are usually switchable in series. In operation, these memory cells are repeatedly charged and discharged.

In the production of such energy storage usually fluctuations occur, which have the consequence that the individual memory cells of the energy storage differ in their charge capacity in the charging and / or discharging. In the course of the operation of the energy storage such fluctuations of the properties of the memory cells even increase. As a result of unequal charge states of the memory cells, charging of a constant current can lead to overloading of individual cells. Accordingly, when discharging the memory cells, there is the danger that individual memory cells will become exhausted. Both can lead to damage to the memory cells, to shorten their life and / or to reduce their charge capacity.

In order to prevent such damage, the charge states of the storage cells of the energy store are regularly matched to one another. Corresponding methods are called symmetrization methods or balancing methods. Widely used in this context is the so-called passive balancing. In this method, the states of charge of the storage cells of higher state of charge are equalized to the state of charge of the storage cell with the lowest state of charge by discharging them via discharge resistors. At the discharge resistors, the excess energy stored in the higher state-of-charge storage cells is at least partially released in the form of heat energy. This generation of heat can lead to damage to the energy storage device or individual components of a storage system comprising the energy storage device.

The present invention is therefore based on the object to propose a method for balancing memory cells of a storage device for storing electrostatic and / or electrochemical energy, which allows as effective as possible damage to a storage system, which can be caused by an amount of heat generated during balancing prevent. It is another object of the present invention to develop a memory system suitable for carrying out this method.

This object is achieved by a method according to claim 1 and by a memory system for carrying out this method. Specific embodiments of the invention are described in the independent claims.

• – Ladezustände der Speicherzellen ermittelt werden und
• – aus den Speicherzellen zu symmetrierende Zellen ausgewählt und über Entladewiderstände eines Wärmeabgabeelements wenigstens teilweise entladen werden,

wobei die zu symmetrierenden Zellen derart ausgewählt und/oder derart mit den Entladewiderständen elektrisch verschaltet werden, dass eine Temperatur des Wärmeabgabeelements eine Maximaltemperatur nicht überschreitet.It is proposed, therefore, a method for symmetrizing memory cells of a memory device, which is adapted to store electrical and / or chemical energy, in particular for storing energy for a drive of a motor vehicle, wherein

• - Charging states of the memory cells are determined and
• Cells selected from the memory cells are selected and at least partially discharged via discharge resistors of a heat-emitting element,

wherein the cells to be balanced are selected and / or electrically connected to the discharge resistors such that a temperature of the heat-emitting element does not exceed a maximum temperature.

The fact that the cells to be balanced are selected and / or electrically connected to the discharge resistors so that a temperature of the heat-emitting element does not exceed a maximum temperature, in particular as a result of the at least partial discharge, will cause damage to a storage system caused by a quantity of heat generated during balancing at least the storage device and the heat-emitting element comprises effectively prevented. In particular, damage to the heat-dissipating element or damage to components of the storage system arranged in or on the heat-dissipating element is avoided.

The memory cells can be designed, for example, as cells of a lead-acid battery, as double-layer capacitors, as nickel-metal hydride, nickel-zinc, lithium-air, zinc-air or lithium-ion cells. Typically, the memory cells are connected in series. Usually, at the memory cells in the fully charged state, a cell voltage of about 4V is applied. The state of charge of a single memory cell or the memory device as a whole is measured in each case in percent and refers to the maximum charge capacity of the respective memory cell or Storage device. The state of charge is also referred to as SOC (State of Charge). Depending on the type of memory cell, there may be a characteristic relationship between the SOC of the memory cell and the open circuit voltage (OCV or Open Circuit Voltage) applied to the respective memory cell. Based on a course of a so-called SOC-OCV curve, the state of charge of the respective cell can then be determined by measuring the rest voltage applied to the cell. Consequently, the determination of the charge states of the memory cells is the same as the determination of the respective resting voltages applied to the memory cells.

The term "balancing" should preferably designate the balancing in the context of the so-called passive-balancing method. In the method described herein, a desired state of charge of the memory cells is preferably determined, which is usually set equal to the state of charge of the memory cell with the smallest state of charge. As part of the Symmetrierungsverfahrens then the charge states of the memory cells to be adjusted by the at least partially discharging the memory cells via the discharge resistors to the desired state of charge.

The heat-dissipating element is preferably different from the storage device. In particular, the heat-emitting element may be spaced from the storage device. For example, a shortest distance between the storage device and the heat-dissipating element is at least 1 cm, at least 5 cm, at least 10 cm, at least 20 cm, or at least 50 cm. The heat-emitting element may be made of metal. For example, the heat-emitting element may be formed as a printed circuit board (PCB).

The discharge resistors may be arranged in, on or on the heat-emitting element. In particular, the discharge resistors are each electrically connectable at least to a subset of the memory cells. The interconnection can comprise both the electrical interconnection of the discharge resistors with the memory cells and the interconnection of the discharge resistors with one another. Typically, each of the discharge resistors may be connected in parallel with at least one of the memory cells, with an ohmic resistance of the discharge resistors usually ranging between 10Ω and 100Ω, respectively. However, the ohmic resistance of the discharge resistors can also assume any other value. The interconnection of the discharge resistors with the memory cells may preferably be performed by means of electrical switches acting as mechanical switches or e.g. may be formed as transistors. Thus, there are preferably a large number of possibilities for interconnecting the discharge resistors with the memory cells.

In particular, it may be provided that the ohmic resistance of a discharge resistor connected in parallel with a given memory cell or a discharge arrangement connected in parallel with the given memory cell can be varied. For example, it may be provided that a plurality of discharge resistors are independently switchable in parallel to a given memory cell. Thus, a discharging current flowing from the memory cell when discharging this memory cell and a quantity of heat and / or power dissipated to the heat-dissipating member when discharging this memory cell are controllable and / or controllable. Typically, a maximum value of the discharge current for a given memory cell is at most 1 A, preferably at most 500 mA, most preferably at most 200 mA.

In a specific embodiment, an initial temperature of the heat-emitting element is detected before the at least partial discharge of the cells to be symmetrized. Thus, it is possible to determine how many degrees the temperature of the heat-emitting element can be increased until the maximum temperature is reached. Usually, the detection of the initial temperature is carried out by means of at least one temperature sensor which is arranged in, on or on the heat-emitting element. Preferably, these are a plurality of temperature sensors, which are regularly distributed in, on or on the heat-emitting element. In this way, a spatial temperature distribution of the heat-emitting element can be detected at a given time. The at least one temperature sensor may e.g. be designed as a temperature-dependent electrical resistance.

In a further specific embodiment, the selection of the cells to be balanced and / or the interconnection of the cells to be balanced with the discharge resistors before discharge is determined again until a time course of the calculated depending on the particular selection and / or the particular interconnection Temperature of the heat-emitting element does not exceed the maximum temperature within a Symmetrierzeitdauer. The unloading is then carried out with the last determined selection and / or interconnection.

The selection and the interconnection, which are determined before unloading and on the basis of which the calculation of the time profile of the temperature of the heat-emitting element is made, should also be called virtual selection and virtual interconnection. By this word choice is intended to Expression come that with the first only virtual selection and / or virtual interconnection nor any physical change in the interconnection, z. B. by flipping the electrical switch, goes along. The actual unloading is then carried out with that actual, ie physical selection and / or interconnection which corresponds to the last determined virtual selection and / or the last determined virtual interconnection and for which the calculated temporal course of the temperature of the heat delivery element predicts that the temperature of the Heat emission element does not exceed the maximum temperature within the Symmetrierzeitdauer. Preferably, the virtual selection and / or the virtual interconnection are changed with the redetermining each time. Instead of calculating the time profile of the temperature of the heat-emitting element, it is also possible to read out the corresponding time profile from a database. If the time course is calculated, it can then be stored in this database.

With this particular embodiment, it is possible to control and limit the increase in the temperature of the heat-emitting element. Overheating of the heat-emitting element and damage caused thereby can thus be effectively prevented in this way.

In a further specific embodiment, the balancing period is calculated as a function of the states of charge of at least the cells to be balanced and / or depending on the interconnection of the cells to be balanced with the discharge resistors and / or dependent on a desired state of charge. By way of example, the balancing period is that period of time which elapses until all the cells to be balanced have assumed the desired state of charge as a result of the at least partial discharge. In this case, the balancing period is thus equal to the maximum discharge time of the cells to be balanced. Alternatively, it may be provided that the balancing period is predetermined, e.g. as a predetermined by a hardware and / or software period of time. Conveniently, the Symmetrierzeitdauer can also be set equal to the smaller of these two values, namely the maximum discharge time and the time specified by the software or hardware period. By calculating the calculated time profile of the temperature of the heat-emitting element only for the balancing period, the calculation can be shortened and / or a physical memory for storing the time profile can be limited.

• – die virtuelle Auswahl der zu symmetrierenden Zellen und/oder die virtuelle Verschaltung der zu symmetrierenden Zellen mit den Entladewiderständen vor dem Entladen erneut bestimmt werden/wird oder
• – die zu symmetrierenden Zellen entladen werden.

In a further specific embodiment, depending on the calculated time profile of the temperature of the heat-emitting element, a heating time period is determined, which is typically given by a start of discharging and by a heating time at which the calculated time curve is the maximum temperature or a maximum temperature of the calculated time profile the temperature of the heat-emitting element reaches or exceeds, depending on the particular Heizzeitdauer

• - the virtual selection of the cells to be balanced and / or the virtual interconnection of the cells to be balanced with the discharge resistors is again determined before discharging or
• - the cells to be balanced are discharged.

The first alternative, namely the re-determination of the virtual selection and / or the virtual interconnection, is preferably selected when the determined heating time duration is smaller than the balancing time period. In this first case, a harmful overheating of the heat-emitting element is to be expected even before the maximum balancing period has elapsed. The second alternative, namely the discharge of the cells to be balanced, preferably for the Symmetrierzeitdauer, is preferably selected when the particular heating time is greater than the Symmetrierzeitdauer. Namely, in this second case, a harmful overheating of the heat-emitting element within the Symmetrierzeitdauer is not to be expected. In this embodiment, a harmful overheating of the heat-emitting element is thus effectively prevented.

• – das Berechnen des zeitlichen Verlaufs der Temperatur des Wärmeabgabeelements und/oder
• – das erneute Bestimmen und Verändern der virtuellen Auswahl und/oder der virtuellen Verschaltung abhängig von
• – elektrischen Eigenschaften wenigstens der jeweiligen virtuellen Auswahl der zu symmetrierenden Zellen und/oder
• – elektrischen und/oder geometrischen und/oder thermischen Eigenschaften der Entladewiderstände und/oder
• – thermischen und/oder geometrischen Eigenschaften des Wärmeabgabeelements.

In another specific embodiment

• - Calculating the time course of the temperature of the heat-emitting element and / or
• - The re-determining and changing the virtual selection and / or the virtual interconnection depending on
• Electrical properties of at least the respective virtual selection of the cells to be balanced and / or
• - electrical and / or geometric and / or thermal properties of the discharge resistors and / or
• - Thermal and / or geometric properties of the heat-emitting element.

In this case, the electrical properties of the respective virtual selection of the cells to be balanced can have an electrical voltage applied to these cells and / or a charge state and / or a charge capacity and / or a desired charge state and / or a calculated power loss delivered via the discharge resistors during discharge include. The electrical properties of the discharge resistors turn may each comprise an ohmic resistance and / or a temperature dependence of the ohmic resistance and / or a discharge current flowing during discharge via the discharge resistors. The geometric properties of the discharge resistors and / or of the heat-emitting element may include a geometric shape and / or an arrangement of the discharge resistors relative to the heat-dissipating element. Finally, the thermal properties of the discharge resistors and / or of the heat-emitting element may include a thermal conductivity and / or a heat capacity and / or a temperature and / or a spatial temperature distribution.

By taking into account these parameters when calculating the time course of the temperature of the heat-emitting element, this time profile can be predicted with great accuracy. A possible overheating of the heat-emitting element with the associated damage can be detected in this way. By considering these parameters when redetermining and changing the virtual selection and / or the virtual interconnection, an optimal selection and / or an optimal interconnection can be found as efficiently as possible. Computing and storage capacities can thus be effectively reduced.

In a further specific embodiment, the selection and / or the interconnection or the virtual selection and / or the virtual interconnection are respectively re-determined and changed before discharging such that a calculated power loss output via the discharge resistors to the heat-dissipating element is reduced as a result of the change , For example, the power loss can be reduced by reducing the number of cells to be balanced. It is also conceivable that the interconnection is changed in such a way that the ohmic resistances of the discharge resistors are increased. Also, such memory cells can be selected as cells to be balanced, to which a lower voltage is applied. Preferably, the calculated power loss is reduced by a predetermined value, e.g. By reducing the power loss, an amount of heat emitted to the heat-dissipating element via the discharge resistors is reduced, thereby preventing overheating of the heat-dissipating element.

In a further specific embodiment, in a first step all memory cells of the memory device are selected as the cells to be balanced. Preferably, only the memory cell with the lowest state of charge is not selected as the cell to be balanced since its state of charge usually already defines the desired state of charge and does not have to be changed any more. In this embodiment, the fastest possible symmetrization of the memory cells is ensured.

Also proposed is a storage system for carrying out the method described above, comprising a storage device for storing electrical and / or chemical energy, in particular for storing energy for a drive of a motor vehicle, and a heat-emitting element, a measuring device and a control and computing unit.

In this case, the memory device has a plurality of memory cells, which are preferably connected in series or switchable. The heat-dissipating element comprises a plurality of electrical resistances, which are electrically connectable to the memory cells and / or to one another and via which the memory cells are at least partially electrically dischargeable, and at least one thermal sensor for detecting a temperature of the heat-dissipating element. The measuring device is designed to detect states of charge of the memory cells and / or to detect electrical voltages applied to the memory cells. Finally, the control and arithmetic unit can be electrically and / or radio-connected to the heat-emitting element and the measuring device and to select memory cells to be symmetrized from the memory cells and / or to interconnect with the resistors in such a way that the temperature of the heat-dissipating element does not exceed a maximum temperature exceeds, in particular due to the at least partial discharge of the cells to be balanced.

Embodiments of the claimed method and the claimed memory system are illustrated in the drawings and will be explained in more detail with reference to the following description. Show it

1 a memory system comprising a memory device having a plurality of memory cells, a measuring device, a heat-dissipating element having a plurality of discharge resistors and a control and computing unit,

2 schematically out some of the memory cells 1 each with different states of charge,

3 the storage system off 1 with a first virtual connection of the discharge resistors and the memory cells,

4 the storage system off 1 with another virtual interconnection of the discharge resistors and the memory cells,

5 a temperature-time diagram with a plurality of calculated time profiles of a temperature of the heat-emitting element 1 and

6 schematically steps of a method for balancing memory cells, shown in a flow chart.

1 shows a storage system 101 with a storage device 102 , a heat dissipation element 103 , a measuring device 104 and with a control and processing unit 105 , The storage device 102 includes a plurality of memory cells 102 to 102n , which are formed in the present example as lithium-ion cells and connected in series. By between the memory cells 102c and 102n shown dashed line is to be indicated that between these memory cells in each case a plurality of further memory cells of the same type is arranged, the representation of which has been omitted here, however. The memory cells 102 to 102n each have a charging capacity of 15 Ah (amp hours). In the fully charged state, one each between the two poles of each of the memory cells 102 to 102n applied voltage in about 4 V. In the storage device 102 it is an energy storage for supplying an electrical drive of a motor vehicle with electrical energy.

The measuring device 104 includes a variety of voltage measuring devices 111 to 111n , The voltage measuring devices 111 to 111n are set up, between the poles of the memory cells 102 to 102n to detect applied electrical voltages. For example, with the voltmeter 111 between the poles of the memory cell 102 applied electrical voltage measurable. With the voltmeter 111b can the at the memory cell 102b applied electrical voltage can be determined etc.

On the heat delivery element 103 , which is formed as a metallic printed circuit board (PCB), is a variety of discharge resistors 106a to 106n and 107a to 107n arranged. Furthermore, located on the heat-emitting element 103 temperature sensors 110a to 110n , the spatially evenly over the heat-emitting element 103 are distributed and which are each temperature-dependent electrical resistances. In the embodiment shown here are the discharge resistors 106a to 106n and 107a to 107n each formed identically, wherein an ohmic resistance of the discharge resistors 106a to 106n and 107a to 107n each 60 Ω.

About electrical switches 108a to 108n and 109a to 109n are the discharge resistors 106a to 106n and 107a to 107n independently of each other with the memory cells 102 to 102n electrically interconnected. In particular, each of the discharge resistors 106a to 106n and 107a to 107n independent of the other discharge resistors to at least one of the memory cells 102 to 102n be connected in parallel so that the memory cells 102 to 102n independently of each other at least over a subset of the discharge resistors 106a to 106n and 107a to 107n are dischargeable. For example, the memory cell 102 via the discharge resistors 106a and or 107a dischargeable, the memory cell 102b is about the discharge resistors 106b and or 107b dischargeable, etc. When discharging the memory cells 102 to 102n In each case discharge currents flow via the discharge resistors 106a to 106n and / or via the discharge resistors 107a to 107n from the memory cells and are at least partially irreversibly converted into heat energy to the heat-emitting element 103 is discharged and this heated. Because of the memory cells 102 to 102n can each be selectively discharged via only one or two of the discharge resistors, one of the memory cells 102 to 102n to the heat-emitting element 103 delivered amount of heat and / or power loss are each controlled and limited. In embodiments that differ slightly from those presented herein, the amount of heat and / or power dissipated by a given memory cell may be much more finely tunable and / or controllable, e.g. B. by the use of sliding resistors whose value is continuously variable.

The control and computing unit 105 , which is designed here as a programmable microcontroller, is connected 112 with the measuring device 104 and about a connection 113 with the heat-dissipating element 103 connected or connectable. Here are the links 112 and 113 each formed as electrical connections. In a slightly modified embodiment, it may be in the compounds 112 and 113 z. B. be radio communications. About the connections 112 and 113 can the voltage measuring devices 111 to 111n and the temperature sensors 110a to 110n be read out and / or controlled. Likewise, the control and processing unit 105 set up the electrical switch 108a to 108n and 109a to 109n about the connection 113 independently of each other. The control and computing unit 105 So can the electrical switch 108a to 108n and 109a to 109n independently of each other optionally in the open or in the closed switch position bring.

In the present embodiment, the storage device 102 and the heat-emitting element 103 executed as separate components and spatially separated. A smallest spatial distance 120 between the storage device 102 and the heat-emitting element 103 is 30 cm. This is a transfer of heat from the heat-emitting element 103 on the storage device 102 prevented or reduced in a simple manner.

The following is a by means of the storage system 101 out 1 feasible method for symmetrizing the memory cells 102 to 102n the storage device 102 to be discribed.

In a first step of the method are by means of the voltage measuring devices 111 to 111n charge states 214a to 214n the memory cells 102 to 102n determined schematically in 2 are shown. Here and below, recurrent features are each provided with identical reference numerals. The charge states 214a to 214n the memory cells 102 to 102n can by means of a in the control and processing unit 105 stored SOC-OCV curve representing the cell type of memory cells 102 to 102n is characteristic, off at the memory cells 102 to 102n derived resting voltages are derived. The charge states 214a to 214n are given as a percentage and refer in each case to the loading capacities 216a to 216n the corresponding memory cell. 2 is removable, that the state of charge 214c the memory cell 102c is lower than the charge states of the remaining memory cells. The state of charge 214c should also be lower than charge states 214d to 214n-1 from memory cells not shown here 102 to 102n-1 , By means of the control and arithmetic unit 105 will be a comparison of the states of charge 214a to 214n carried out, the state of charge 214c as nominal charge state 215 is identified in 2 is shown in the form of a dashed line.

It is therefore the task of the symmetrization method to determine those of the memory cells 102 to 102n the storage device 102 whose state of charge is greater than the desired state of charge 215 , about the discharge resistors 106a to 106n and or 107a to 107n or via at least a subset of the discharge resistors 106a to 106n and or 107a to 107n at least partially discharged until their state of charge each as well as possible with the desired state of charge 215 matches. It should unload the memory cells 102 to 102n be made such that a temperature of the heat-emitting element 103 a maximum temperature 505 (please refer 5 ) as a result of unloading. This should damage the heat dissipation element 103 or damage from in, on or on the heat-dissipating element 103 arranged components can be prevented.

In the next step, first the temperature of the heat-emitting element 103 with the help of temperature sensors 110a to 110n certainly. In this way, a spatial temperature distribution of the heat-emitting element 103 determined. Then be by the control and processing unit 105 from the memory cells 102 to 102n selected in a first virtual selection to be balanced cells, their charge states as the first to the desired state of charge 215 to be aligned. In the present example, with the exception of the memory cell 102c whose state of charge 214c the nominal state of charge 215 defines, with the first virtual selection, all other memory cells first 102 . 102b such as 102d to 102n selected as cells to be symmetrized. The term "virtual" in this context is intended to indicate that "virtually" selected cells are initially not actually symmetrized. Rather, only calculations and / or simulations are initially performed for the first virtual selection of the cells to be balanced.

In addition, with the help of the control and processing unit 105 for the first virtual selection of memory cells to be symmetrized, a discharge process is simulated. For this purpose, first a first virtual interconnection 301 the discharge resistors 106a to 106n and 107a to 107n with the memory cells 102 to 102n selected (see 3 ). An interconnection, and with it the first virtual interconnection 301 , corresponds in each case exactly one configuration of the electrical switch 108a to 108n and 109a to 109n , The configuration is determined by that for each of the electrical switches 108a to 108n and 109a to 109n is determined whether the respective switch is in the open or closed switch position. The term "virtual interconnection" is intended to mean that the corresponding interconnection initially not by actual driving the electrical switch 108a to 108n and 109a to 109n through the control and computing unit 105a is realized. Rather, the first virtual interconnection serves 301 in this step merely as a basis for the control and computation unit 105 performed simulation or calculation of the discharge and a time course of the temperature heat dissipation element 103 as a result of this unloading process.

At the first virtual interconnection 301 are with the exception of the electrical switch 108c and 109c all electrical switches in the closed switch position. The first virtual interconnection 301 is thus selected such that the total resistances over which the cells to be balanced are to be discharged in each case assume the smallest possible value. So is in 3 for example, the total resistance of the discharge resistors 106a and 107a , each parallel to the memory cell 102 are switched, a total of 30 Ω. For example, would the electric switch 109a brought from the closed switch position in the open switch position, so deceive the corresponding total resistance of the discharge resistors 106a and 107a over which the discharge of the memory cell 102 would be done 60 Ω.

For the in 3 shown first virtual interconnection 301 calculates the control and arithmetic unit 105 a first virtual power dissipation, via the discharge resistors 106a to 106n and 107a to 107n to the heat-emitting element 103 if the partial discharge of the memory cells 102 to 102n with an actual interconnection would be performed, that of the first virtual interconnection 301 equivalent. The first virtual power loss is given by the sum of each of the individual according to the first virtual selection to be symmetrized cells to the heat dissipation element 103 delivered individual first virtual power losses. The individual first virtual power losses are in turn given by the voltage applied to the individual cells to be symmetrized in each case and previously determined electrical voltages, and by the total resistance of those discharging resistors via which the discharge of the respective cells to be balanced is to take place. If adjacent memory cells are discharged, discharge currents flowing between these adjacent memory cells or flowing between the discharge resistors respectively associated with the adjacent memory cells may be neglected. For example, in 3 Discharge currents coming from one of the discharge resistors 106a and 107a formed discharge on one of the discharge resistors 106b and 107b formed further discharge arrangement flow, disregarded when calculating the first virtual power loss.

In addition, the control and computation unit calculates 105 for the first virtual selection of the cells to be balanced in each case first virtual discharge periods, which would each require a discharge to the desired state of charge. The first virtual discharge periods are dependent on the state of charge of the respective memory cell before discharging, from the desired state of charge 215 as well as from the first virtual interconnection.

After that, the control and computation unit compares 105 the first virtual discharge periods thus calculated with one of the control and computation unit 105 predetermined hardware time. In the present example, the calculated first virtual discharge periods of the cells to be balanced according to the first virtual selection should each be several hours. In each case, they are much larger than the hardware time duration, which should be 2000 seconds here. Then selects the control and processing unit 105 the hardware time of 2000 seconds as balancing time 504 (please refer 5 ) out. In the following, all of the control and processing unit 105 carried out simulations and / or calculations of the discharge process or the time course of the temperature of the heat-emitting element 103 performed only for a time interval, which by the Symmetrierzeitdauer 504 is given or only slightly longer than the Symmetrierzeitdauer 504 ,

Starting from the in 3 shown first virtual selection of the cells to be balanced and the first virtual interconnection 301 calculates the control and arithmetic unit 105 now a first time course 506a (please refer 5 ) the temperature of the heat-emitting element 103 , Input variables for this calculation are those of the discharge resistors 106a to 106n and 107a to 107n to the heat-emitting element 103 transmitted first virtual power loss, a spatial arrangement of the discharge resistors 106a to 106n and 107a to 107n on the heat-dissipating element 103 , a geometric shape of the heat-emitting element 103 and a thermal conductivity of the heat-emitting element 103 ,

For example, the control and computation unit calculates 105 the first time course 506a the temperature of the heat-emitting element 103 by solving the heat conduction equation for the heat delivery element 103 with the help of finite element methods. In this case, it can also be provided that a decrease in the discharge currents flowing from the first virtual selection of the cells to be balanced in the course of the discharge process and an associated decrease in the first virtual power loss are taken into account. Another input to the calculation is the initial temperature of the heat delivery element 103 or the spatial initial temperature distribution of the heat-emitting element 103 It can also be provided that the control and computing unit 105 does not perform the calculation itself, but the first time course 506a eg read from a database. In such a database, different temporal temperature profiles can be stored as a function of different values of the input parameters. These input parameters include, for example, those to the heat-emitting element 103 delivered virtual power loss, the initial temperature of Heat dissipation element 103 , the respective virtual selection of the cells to be balanced and / or the respectively selected virtual interconnection.

5 shows a temperature-time diagram 501 with different time courses 506a to 506f the temperature of the heat-emitting element 103 , On the X axis 502 the time is plotted, whereby the time t = 0 corresponds to a beginning of the unloading process. On the Y axis 503 is the temperature change of the heat-emitting element 103 applied. This temperature difference relates in each case to the largest temperature of the heat-emitting element calculated for a given time 103 and to the highest temperature of the heat-emitting element 103 at the start time, ie before the start of the unloading process. The symmetry duration given by the hardware time 504 is 2000 seconds. Also highlighted by a dashed line is the maximum temperature 505 , It is a temperature value that the heat dissipation element 103 should not overwrite to damage the heat dissipation element 103 or damage from on the heat-dissipating element 103 to avoid arranged components.

After the control and computing unit 105 the first time course 506a calculated, determines the control and processing unit 105 a first heating time 507a in which the first time course 506a the maximum temperature 505 reached. In the present case is the first heating time 507a at about 350 s. In a next process step, the control and computing unit compares 105 one by the first heating time 507a given first heating period 508a with the balancing period 504 , in this case, the first heating period 508a of 350 s less than the Symmetrierzeitdauer 504 from 2000s. Would the discharge of the cells to be balanced thus with the first virtual interconnection 301 according to 3 performed, the heat-emitting element would 103 the maximum temperature 505 for the first heating time 507a exceed. Therefore, the actual discharge of the cells to be balanced is not performed with an interconnection, that of the first virtual interconnection 301 according to 3 equivalent.

Instead, the control and computing unit determines 105 a second virtual selection of the cells to be balanced and / or a second virtual interconnection 401 (please refer 4 ) of the cells to be balanced with the discharge resistors 106a to 106n and 107a to 107n , In this case, the virtual selection of the cells to be balanced and / or the virtual interconnection of the cells to be balanced with the discharge resistors 106a to 106n and 107a to 107n modified such that the according to the second virtual selection and / or the second virtual interconnection 401 via the discharge resistors 106a to 106n and 107a to 107n to the heat-emitting element 103 delivered second virtual power loss is less than the first virtual power loss. Here, the first virtual power loss is 20 W, the second virtual power loss, however, only 19 W.

This can be done, for example, by reducing a number of the cells to be balanced. For example, the memory cell 201b according to the first virtual interconnection 301 in 3 selected as memory cell to be balanced, but not according to the second virtual interconnection 401 in 4 , Compare to the switch positions of the electrical switch 108b and 109b in the 3 and 4 , However, the reduction in the virtual power loss can also be realized in that, for example, the ohmic resistance over which a given memory cell is to be discharged is greater according to the second virtual interconnection than according to the first virtual interconnection. For example, the memory cell 102 according to the first virtual interconnection 301 in 3 discharged via an ohmic resistance of 30 Ω, according to the second virtual interconnection 401 in 4 however, over an ohmic resistance of 60 Ω. Compare to the switch positions of the electrical switch 109a in the 3 and 4 ,

In the example shown here, the transition from the first to the second virtual selection of the cells to be balanced or from the first virtual interconnection takes place 301 to the second virtual interconnection 401 the initially determined initial temperature distribution of the heat-emitting element 103 considered. For example, at the second virtual selection 401 such memory cells are no longer selected, their discharge a portion of the heat-emitting element 103 would heat even further with a particularly high temperature. Usually, the heat-dissipating element heats up 103 when partially discharging the memory cells in a central region of the heat-emitting element 103 especially fast. When changing the virtual selection of the cells to be balanced, therefore, typically those memory cells are initially selected no more than cells to be balanced, to which discharge resistors in the central region of the heat-emitting element are assigned for discharging. In the change of the virtual selection and / or the virtual interconnection, therefore, the arrangement of the discharge resistors 106a to 106n and 107a to 107n on the heat-dissipating element 103 considered.

After the control and computing unit 105 the virtual selection and / or the virtual interconnection has changed is for the second virtual Selection and / or the second virtual interconnection 401 calculates a second virtual power dissipation when discharging to the heat dissipation element 103 would be delivered. Then, for the second virtual selection and / or for the second virtual interconnection 401 a second time course 506b (please refer 5 ) the temperature of the heat-emitting element 103 calculated. It can be clearly seen that the temperature increase of the heat-emitting element 103 according to the second time course 506b less than in the case of the first time course 506a , Thereupon also becomes for the second virtual interconnection 401 or for the second time course 506b a second heating time 507b determines to which the second time course 506b the maximum temperature 505 reached. Since the second virtual power loss (19 W) is less than the first virtual power loss (20 W), the temperature of the heat-dissipating member increases 103 slower. This is accompanied by the fact that by the second heating time 507b given second heating period 508b greater than the first heating time 507a given first heating period 508a , As already in connection with the first time course 506a described, so is the second heating time 508b with the balancing period 504 compared. As is the second heating time 508b is less than the Symmetrierzeitdauer 504 , the actual unloading is not done with a selection and / or interconnection, that of the second virtual selection and / or the second virtual interconnection 401 equivalent.

Instead, the control and evaluation unit determines 105 a third virtual selection of the cells to be balanced and / or a third virtual connection of the discharge resistors 106a to 106n and 107a to 107n with the memory cells 102 to 102n wherein a third virtual power dissipation is less than the second virtual power dissipation. As before, a third time course 506c the temperature of the heat-emitting element 103 calculated. The corresponding third heating period 508c is again greater than the second heating time 508b ,

This process is continued until the calculated heating time duration is greater than the balancing time period 504 , In 5 are more temporal courses 506d and 506d with corresponding heating times 507d and 507e and heating time periods 508d and 508e shown. For a sixth time course 506f is the sixth heating time period 508f finally greater than the Symmetrierzeitdauer 504 , Therefore, the control and computing unit controls 105 the electrical switches 108a to 108n and 109a to 109n now such that an actual selection of the cells to be balanced and / or an actual connection of the discharge resistors 106a to 106n and 107a to 107n with the memory cells 102 to 102n the last determined sixth virtual selection and / or sixth virtual interconnection corresponds (not shown here). A corresponding sixth virtual power loss should be 15 W. The discharging of the thus selected cells to be balanced is started with the actual driving of the electric switches. The cells to be balanced become for the Symmetrierzeitdauer 504 discharged.

With the aid of the method described above, the temperature of the heat-dissipating element is prevented 103 the maximum temperature 505 within the balancing period 504 crosses out. Damage to the heat-dissipating element 103 as a result of overheating it is successfully avoided. After expiry of the balancing period 504 For example, the process just described may be redone until the state of charge 214a to 214n all memory cells 102 to 102n to the nominal state of charge 215 are aligned.

In 6 is the symmetrization method described here in the form of a flow chart again shown schematically. In a first process step 601 becomes a first virtual selection of cells to be balanced and / or a first virtual interconnection 301 the memory cells 102 to 102n with the discharge resistors 106a to 106n and 107a to 107n determined, wherein for the first virtual selection respectively first virtual discharge periods are calculated. In a second process step 602 a first virtual power dissipation is determined. In a third process step 603 becomes a first time course of a temperature of the heat-emitting element 103 calculated. In addition, depending on the first time course, a first heating time and a first heating time determined by the latter are calculated. In a fourth process step 604 becomes the first heating time period with the balancing period 504 compared. If the first heating time is less than the Symmetrierzeitdauer 504 , becomes a procedural step 605 passed.

In the process step 605 a new virtual selection and / or a new virtual interconnection are determined, whereby a virtual power loss calculated for the new virtual selection and / or for the new virtual interconnection is reduced

is, for. B. by 1 W. In the next step 606 For the new virtual selection and / or for the new virtual interconnection, a new time course of the temperature of the heat delivery element is 103 calculated. In addition, a new heating time and a new heating time are determined. Subsequently, again becomes the process step 604 passed. The process steps 604 . 605 and 606 are repeated until the currently calculated heating time duration is greater than the balancing time period 504 ,

If this is the case, then becomes the process step 607 passed. In the process step 607 an actual selection of cells to be balanced is made or an actual connection of the memory cells takes place 102 to 102n with the discharge resistors 106a to 106n and 107a to 107n by appropriate activation of the electrical switch 108a to 108n and 109a to 109n realized. The actual selection or the actual interconnection correspond to the last determined virtual selection or the last determined virtual interconnection. The appropriate selection of the cells to be balanced is then for the Symmetrierzeitdauer 504 at least partially unloading. The process can be repeated until the states of charge 214a to 214n all memory cells 102 to 102n to the nominal state of charge 215 are aligned.

Claims (10)

Method for symmetrizing memory cells ( 102 . 102b . 102c . 102n ) a storage device ( 102 ), which is adapted to store electrical and / or chemical energy, in particular for storing energy for a drive of a motor vehicle, wherein - charge states ( 214a . 214b . 214c . 214n ) of the memory cells ( 102 . 102b . 102c . 102n ) and - from the memory cells ( 102 . 102b . 102c . 102n ) cells to be balanced and via discharge resistors ( 106a . 106b . 106c . 106n . 107a . 107b . 107c . 107n ) of a heat-emitting element ( 103 ) are at least partially discharged, characterized in that the cells to be symmetrized are selected in such a way and / or with the discharge resistors ( 106a . 106b . 106c . 106n . 107a . 107b . 107c . 107n ) are electrically connected so that a temperature of the heat-emitting element ( 103 ) a maximum temperature ( 505 ) does not exceed. Method according to one of the preceding claims, characterized in that before discharging an initial temperature of the heat-emitting element ( 103 ) is detected. Method according to one of the preceding claims, characterized in that the selection of the cells to be balanced and / or the interconnection of the cells to be balanced with the discharge resistors ( 106a . 106b . 106c . 106n . 107a . 107b . 107c . 107n ) is determined again before discharging until a time course calculated as a function of the respectively determined selection and / or a function of the respectively determined interconnection ( 506a . 506b . 506c . 506d . 506e . 506f ) the temperature of the heat-emitting element ( 103 ) the maximum temperature ( 505 ) within a balancing period ( 504 ) and that unloading is then carried out with the last selection and / or interconnection. Method according to Claim 3, characterized in that the balancing period ( 504 ) - depending on the charge states of at least the cells to be balanced and / or depending on the interconnection of the cells to be balanced with the discharge resistors ( 106a . 106b . 106c . 106n . 107a . 107b . 107c . 107n ) is calculated and / or - given. Method according to Claim 3, characterized in that, depending on the calculated time course ( 506a . 506b . 506c . 506d . 506e . 506f ) the temperature of the heat-emitting element ( 103 ) a heating time period ( 508a . 508b . 508c . 508d . 508e . 508f ) is determined, depending on the determined heating time period - the selection and / or the interconnection are again determined before unloading, or - the cells to be balanced are discharged. A method according to claim 3, characterized in that - calculating the time course ( 506a . 506b . 506c . 506d . 506e . 506f ) the temperature of the heat-emitting element and / or - the redetermining and changing the selection and / or the interconnection depending on - electrical properties of at least the respective selection of the cells to be balanced and / or - electrical and / or geometric and / or thermal properties of the discharge resistors ( 106a . 106b . 106c . 106n . 107a . 107b . 107c . 107n ) and / or - thermal and / or geometric properties of the heat-emitting element ( 103 ) is made. A method according to claim 6, characterized in that - the electrical properties of the respective selection of the cells to be balanced in each case an applied voltage to these cells and / or a state of charge ( 214a . 214b . 214c . 214n ) and / or a loading capacity ( 216a . 216b . 216c . 216n ) and / or a desired state of charge ( 215 ) and / or during discharge via the discharge resistors ( 106a . 106b . 106c . 106n . 107a . 107b . 107c . 107n ) include the calculated power loss - and / or that the electrical properties of the discharge resistors ( 106a . 106b . 106c . 106n . 107a . 107b . 107c . 107n ) in each case an ohmic resistance and / or a temperature dependence of the ohmic resistance and / or an unloading via the discharge resistors ( 106a . 106b . 106c . 106n . 107a . 107b . 107c . 107n ) comprise flowing discharge current - and / or that the geometric properties of the discharge resistors ( 106a . 106b . 106c . 106n . 107a . 107b . 107c . 107n ) and / or the heat-emitting element ( 103 ) a geometric shape and / or an arrangement of the discharge resistors ( 106a . 106b . 106c . 106n . 107a . 107b . 107c . 107n ) relative to the heat dissipation element ( 103 ) and / or that the thermal properties of the discharge resistors ( 106a . 106b . 106c . 106n . 107a . 107b . 107c . 107n ) and / or the heat-emitting element ( 103 ) comprise a thermal conductivity and / or a heat capacity and / or a temperature. A method according to claim 3, characterized in that the selection and / or the interconnection before each discharge again such determined and changed / is that one of the discharge resistors ( 106a . 106b . 106c . 106n . 107a . 107b . 107c . 107n ) to the heat-dissipating element ( 103 ) is reduced as a result of the change. Method according to one of the preceding claims, characterized in that in a first step all memory cells ( 102 . 102b . 102c . 102n ) of the storage device ( 102 ) are selected as the cells to be symmetrized. Storage system ( 101 ) for carrying out the method according to one of the preceding claims, comprising - a memory device ( 102 ) for storing electrical and / or chemical energy, in particular for storing energy for a drive of a motor vehicle, - a heat-emitting element ( 103 ), - a measuring device ( 104 ) and - a control and processing unit ( 105 ), wherein - the memory device ( 102 ) a plurality of memory cells ( 102 . 102b . 102c . 102n ), - the heat-dissipating element ( 103 ) a plurality of discharge resistors ( 106a . 106b . 106c . 106n . 107a . 107b . 107c . 107n ), which are connected to the memory cells ( 102 . 102b . 102c . 102n ) and / or electrically interconnectable with each other and via which the memory cells ( 102 . 102b . 102c . 102n ) are at least partially electrically dischargeable, and at least one thermal sensor ( 110a . 110b . 110c . 110n ) for detecting a temperature of the heat-emitting element ( 103 ), - the measuring device ( 104 ) for detecting states of charge ( 214a . 214b . 214c . 214n ) of the memory cells ( 102 . 102b . 102c . 102n ) and / or for detecting at the memory cells ( 102 . 102b . 102c . 102n ) is attached to the applied electrical voltages and wherein - the control and computing unit ( 105 ) with the heat-dissipating element ( 103 ) and the measuring device ( 104 ) is electrically and / or wirelessly connectable and program-technically arranged, from the memory cells ( 102 . 102b . 102c . 102n ) to select cells to be balanced and / or with the discharge resistors ( 106a . 106b . 106c . 106n . 107a . 107b . 107c . 107n ) such that a temperature of the heat-emitting element ( 103 ) a maximum temperature ( 505 ) does not exceed.

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