DE102011004895A1 - Electronic circuit arrangement for converting analog input signal into digital output signal in automotive industry, has charge subtraction device removing predetermined charge amount from capacitor in response to output signal - Google Patents

Abstract

The arrangement has a sample and hold circuit (110) whose input side is connected with an input terminal (102) that delivers an analog input signal (Uanalog) to be converted. An analog-to digital converter (120) converts a signal level that exists at an output (112) of the sample-and-hold circuit into a digital output signal (Udigital). A charge subtraction device removes a predetermined charge amount from a sample and hold capacitor (Csh) in response to an output signal of a comparator (130) so that the signal level is smaller than a reference signal level (Uref). An independent claim is also included for a method for converting an analog input signal into a digital output signal.

Description

The invention relates to the technical field of converting analog electrical signals into digital signals. In particular, the present invention relates to an electronic circuit arrangement having a sample-and-hold circuit and an analog-to-digital converter for converting an analog input signal into a digital output signal. The present invention further relates to a method of converting an analog input signal into a digital output signal by means of such an electronic circuit arrangement.

An analog-to-digital converter (ADC) uses different methods to convert analog input signals into digital data or a data stream, which can then be digitally processed or stored. In the age of progressive digitization, a wide variety of technical fields, such as u. a. In automotive engineering a variety of ADWs are used for a wide variety of applications.

The resolution of an ADC depends on both the measuring range and the number of available bits. The maximum voltage to be measured defines the area to be measured. To get the smallest resolution, the measurement range is divided by the number of bits. At a measuring range of z. B. 3 volts and a resolution of 12-bit thus results in a resolution of 3 V: 4096 = 732.42 μV per bit. Since the range of measurement of an analog-to-digital conversion to be detected can not typically be restricted, increasing the resolution of an analog-to-digital conversion will only increase the number of bits used.

From the US 5,748,129 For example, a circuit for analog-to-digital conversion of an analog input voltage is known which still uses an analog reference voltage for conversion in addition to the input voltage. The analog reference voltage has a voltage level which is determined as a function of the level of the input voltage by means of an analog level detector circuit and a proportional circuit connected downstream of the analog level detector circuit. The known analog-to-digital conversion circuit has a so-called parallel comparator type analog-to-digital converter (PK-ADC). The PK-ADC converts the level of the input voltage supplied to the PK-ADC via a first input of the PK-ADC with respect to the level of the analog reference voltage supplied to the PK-ADC via a second input of the PK-ADC , into a digital output value. The parallel comparator type analog-to-digital converter is conventionally composed of (1) a set of comparators which compare the analog input voltage signal with different fixed voltage values, (2) a corresponding set of D-type flip-flops representing the digital ones And outputs (3) an encoder which converts the outputs of the D-type flip-flops to the final digital output code.

The invention has for its object to increase the resolution of an analog-to-digital conversion in a simple manner.

This object is solved by the subject matters of the independent claims. Advantageous embodiments of the present invention are described in the dependent claims.

According to a first aspect of the invention, an electronic circuit arrangement for converting an analog input signal into a digital output signal is described. The described electronic circuit arrangement comprises (a) an input terminal for supplying the analog input signal to be converted, (b) a sample-and-hold circuit which is connected on the input side to the input terminal and which has a switch and a sample-and-hold capacitor, c) an analog-to-digital converter, (c1) which is connected on the input side to an output of the sample-and-hold circuit and (c2) which is adapted to a present at the output of the sample-and-hold circuit signal level in the digital (D) an output terminal for outputting the converted digital output signal, (e) a comparator connected to the output of the sample-and-hold circuit and arranged such as at the output of the sample-and-hold circuit compare applied signal level with a reference signal level, and (f) a charge subtractor, which with an output g is connected to the comparison device and which is arranged to remove a predetermined amount of charge from the sample-and-hold capacitor in response to an output signal of the comparison device, so that the voltage applied to the output of the sample-and-hold circuit signal level becomes smaller than the reference signal level.

The described electronic circuit arrangement is based on the recognition that, by means of a targeted charge subtraction from the sample-and-hold capacitor, the analog signal level which is output by the sample-and-hold circuit is transformed into a range of signal levels, which from the analogue to Digital converter can be processed without an override of the analog-to-digital converter. In this way, an input signal to be converted can also be used be converted into the digital output signal when the signal level of the input signal to be converted is significantly larger than the actual measuring range of the analog-to-digital converter used.

In the case of the aforementioned charge subtraction, a precisely defined charge quantity is preferably removed from the sample-and-hold capacitor. By knowing this amount of charge accurately, the output of the analog-to-digital converter can then be adjusted so that the digital output does not match the signal level actually being processed by the analog-to-digital converter (= the output of the sample-hold Circuit applied signal level) corresponds. Since, given a knowledge of the capacitance of the sample-and-hold capacitor, each defined charge withdrawal corresponds to a certain voltage difference, the primary digital output signal of the analog-to-digital converter can be converted into the digital output by a simple addition with a digital value corresponding to the certain voltage difference digital output of the entire circuit can be transformed.

The circuit described has the advantage that analog-to-digital converters can be used which have a measuring range which is significantly smaller compared to the expected signal level of the analog input signal to be converted. At a given digital resolution (eg 8 bits) of the analog-to-digital converter, the resolution is then automatically increased in comparison to a conventional analog-to-digital converter whose measuring range is adapted to the signal level to be expected because the predetermined digital resolution (eg 8 bits) relates to the measuring range of the described analog-to-digital converter, which measuring range is possibly much smaller than the expected signal level of the analog input signal to be converted. By a suitable charge subtraction, the amount of charge must be known exactly as described, thus almost any increase in the resolution of the circuit arrangement can be achieved compared to a conventional analog-to-digital converter, without the number of bits described and for the inventive circuit arrangement used analog-to-digital converter must be increased.

A further advantage of the described electronic circuit arrangement can be seen in the fact that the circuit technology required for the realization of the charge subtraction is already contained at least partially (eg to 50%) in many known sample-and-hold circuits.

In this document, the term "connected" is to be understood in particular as "electrically connected". An electrical connection can be immediate, d. H. only with a piece of electrical conductor (in particular a conductor track), or indirectly via at least one further electronic component (eg a resistor, a capacitor and / or a coil). Possibly. For example, active components or assemblies (eg, an amplifier) may also be used to electrically interconnect various components of the described electronic circuitry.

The described (analog) signal levels may be voltage levels and / or current levels. Preferably, the described signal levels are voltage levels, which are processed in a known manner in the comparison device, which has, for example, a comparator, and / or the analog-to-digital converter used.

According to an embodiment of the invention, the electronic circuit arrangement further comprises a reference signal generator for providing the reference signal level. Depending on the type of analog signals used in the described electronic circuitry, the reference signal generator may be a constant voltage source or a constant current source.

According to another embodiment of the invention, the reference signal generator is implemented in the analog-to-digital converter. This has the advantage that the expenditure on equipment for realizing the described electronic circuit arrangement can be kept small. This is especially true when an analog-to-digital converter is used, which uses a signal whose internal level is identical to the reference signal level anyway as an internal reference signal.

According to a further exemplary embodiment of the invention, the charge subtraction device has a subtraction capacitor. The use of a capacitor, which is referred to in this document as a subtraction capacitor, has the advantage that in a particularly simple manner, a precisely defined amount of charge can be dissipated by the sample-and-hold capacitor.

According to a further embodiment of the invention, the charge subtraction device further comprises a control logic and a plurality of switching elements. In this case, the control logic is connected on the input side to an output of the comparison device and the switching elements are controllable by the control logic such that the Subtraction capacitor at least for a certain period of time with the sample-and-hold capacitor is connectable.

The switching elements may, for example, be transistors which are suitably connected to the control logic and connect the subtraction capacitor to the sample-and-hold capacitor so that a defined charge transfer or charge drain from the sample-and-hold capacitor to the subtraction capacitor takes place.

According to a further embodiment of the invention, the charge subtraction device is designed such that the subtraction capacitor and the sample-and-hold capacitor can be connected to one another in the form of a parallel connection. This has the advantage that the charge removal described above can be realized in a particularly simple manner without having to obtain a reduced accuracy with regard to the precise amount of the removed charge. Since, in accordance with the general principles of electrostatics, the capacitances add up when two capacitors are connected in parallel, the charge removal quantity can not only be precisely defined, but also calculated in a simple manner.

According to a further exemplary embodiment of the invention, the charge subtraction device furthermore has a plurality of further switching elements, which can be controlled by the control logic such that the subtraction capacitor can be connected to two reference potentials for at least a certain period of time. In particular, one terminal of the subtraction capacitor can be connected to a first reference potential and the other terminal of the subtraction capacitor can be connected to a second reference potential.

The use of the further switching element in conjunction with the two reference potentials has the advantage that the amount of charge which is drawn off at a connection of the two capacitors of the sample-and-hold capacitor, is particularly well defined. In this way, the accuracy of the electronic circuitry with respect to the overall analog to digital conversion can be increased.

According to a further embodiment of the invention. a first reference potential is identical to the reference signal level and / or the second reference potential is a ground potential. This has the advantage that reference potentials are used, which are present anyway in the analog-to-digital converter used, so that advantageously no additional expenditure on equipment for generating the reference potentials is required.

According to a further exemplary embodiment of the invention, the switching elements and the further switching elements can be controlled by the control logic in such a way that the subtraction capacitor can be alternately connected to the sample-and-hold capacitor and to the two reference potentials. This has the advantage that multiple removal of a defined amount of charge is possible. The successive removal of a defined charge quantity in each case can be continued until the signal level applied to the output of the sample-and-hold circuit assumes a value which lies within the measuring range of the analog-to-digital converter used.

According to a further exemplary embodiment of the invention, the switching elements and the further switching elements are arranged in such a way and the control logic is set up such that the subtraction capacitor with alternating polarity can be connected to the sample-and-hold capacitor and / or to the two reference potentials.

By selectively reversing the subtraction capacitor with respect to the sample-and-hold capacitor and / or the two reference potentials, the amount of charge taken from the sample-and-hold capacitor during a switching cycle can be increased. In this context, the term "switching cycle" is to be understood as a time period within which the subtraction capacitor is connected once to the sample-and-hold capacitor and once to the two reference potentials.

According to another aspect of the invention, a method of converting an analog input signal to a digital output signal by means of an electronic circuit arrangement comprising a sample and hold circuit comprising a switch and a sample-and-hold capacitor and an analog-to-digital converter is described wherein the analog-to-digital converter is connected to an output of the sample-and-hold circuit. The described method comprises (a) supplying the analog input signal to be converted to an input terminal of the electronic circuitry connected to an input of the sample and hold circuit, (b) comparing a signal level applied to the output of the sample and hold circuit (c) removing a predetermined amount of charge from the sample-and-hold capacitor in response to an output signal of the comparison means by means of a charge subtractor connected to a reference signal level by means of a comparator connected to the output of the sample-and-hold circuit; Output of the comparator is connected so that the voltage applied to the output of the sample-and-hold circuit Signal level becomes smaller than the reference signal level, (d) converting the signal level applied to the output of the sample-and-hold circuit to the digital output signal, and (e) outputting the converted digital output signal at an output terminal of the electronic circuitry.

The described method is also based on the recognition that, by a targeted charge removal from the sample-and-hold capacitor, the analog signal level which is output by the sample-and-hold circuit is transformed into a range of signal levels, which from the analogue to Digital converter can be easily processed. In this way, an input signal to be converted can still be converted into the digital output signal even if the signal level of the input signal to be converted is significantly greater than the actual measuring range of the analog-to-digital converter used.

By deliberately choosing an analog-to-digital converter with a reduced measuring range compared to the expected signal level of the input signal, the absolute resolution of the described analog-to-digital conversion can be compared with conventional analog-to-digital conversion , in which the measuring range of the analog-to-digital converter is adapted to the expected signal level of the input signal, be increased significantly. Namely, the resolution of the analog-to-digital converter merely "disperses" to a window of signal levels at the output of the sample-and-hold circuit which is reduced by the charge extraction (s).

It should be noted that embodiments of the invention have been described with reference to different subject matters. In particular, some embodiments of the invention are described with apparatus claims and other embodiments of the invention with a method claim. However, it will be readily apparent to those skilled in the art upon reading this application that, unless explicitly stated otherwise, in addition to a combination of features belonging to a type of subject matter, any combination of features that may result in different types of features is also possible Subject matters belong.

Further advantages and features of the present invention will become apparent from the following exemplary description of a presently preferred embodiment.

The 1a and 1b show according to an embodiment of the invention, an electronic circuit arrangement for converting an analog input signal into a digital output signal.

It should be noted that the embodiments described below represent only a limited selection of possible embodiments of the invention. In particular, it is possible to suitably combine the features of individual embodiments with one another, so that a multiplicity of different embodiments are to be regarded as obviously disclosed to the person skilled in the art with the embodiment variants explicitly illustrated here.

In the 1a and 1b an electronic circuit arrangement according to a preferred embodiment of the invention is shown in detail. 1a shows the general structure of the circuit arrangement, 1b shows in detail the construction of a charge subtraction device 150 , which is used for the electronic circuit arrangement.

The two parts of the electronic circuit arrangement are connected to each other via the connection points A, B and C, which in both 1a and 1b are indicated.

How out 1 As can be seen, the circuit arrangement has an analog input terminal 102 on which the analog input signal U to be converted _is applied _analogously and which is the input of a sample-and-hold circuit 110 represents. The sample-and-hold circuit 110 has a switch S _SH and a sample-and-hold capacitor C _SH . One terminal of the sample-and-hold capacitor C _SH is connected to a ground potential GND.

According to the embodiment shown here, the switch S _SH by means of an electronic switching element such. B. realized a transistor. Since sample-and-hold circuits are known to those skilled in the art, the function of the sample and hold circuit is discussed 110 not discussed here.

An exit 112 the sample-and-hold circuit 110 is on the one hand with the input of an analog-to-digital converter 120 and on the other hand with a comparison device 130 connected. According to the embodiment shown here, the comparison device 130 realized with a constructed as an operational amplifier comparator.

The analog-to-digital converter 120 has a digital output port 182 on.

As further out 1a can be seen, by means of the comparator 130 the one at the exit 112 the sample-and-hold circuit 110 applied signal level compared to a reference potential U _ref , which of a reference signal generator 135 provided. As long as the at the output 112 applied voltage is greater than the reference potential U _ref , according to the embodiment shown here, a positive signal from the comparator 130 output. Is that at the exit 112 applied voltage less than the reference potential U _ref , is from the comparator 130 a negative signal is output. The output of the comparator 130 is via terminal C, which is the output of the comparator 130 represents to the in 1b illustrated charge subtraction device 150 output. In particular, the output of the comparator 130 to a control logic 155 the charge subtraction device 150 output.

According to the embodiment shown here, the reference signal generator 135 a part of the analog-to-digital converter 120 and the reference potential is a reference potential which also applies to the analog-to-digital conversion in the analog-to-digital converter 120 is used. This is to realize the reference signal generator 135 no additional equipment required.

How out 1b can be seen, the charge subtractor 150 next to the control logic 155 another Subtraktionskondensator C _S on, which connects via a system of a plurality of switching elements to Subtraktionskondensator C _S alternately to the sample-hold capacitor C _SH and two reference potentials. According to the exemplary embodiment illustrated here, a first of the two reference potentials is the reference signal level U _ref . The second of the two reference potentials is the ground potential GND.

According to the embodiment shown here, the system consisting of several switching elements has a total of four switching elements 162a . 162b . 162c and 162d and two other switching elements 164a and 164b on. The switching elements 162a . 162b . 162c . 162d . 164a and 164b are dashed lines shown control lines 155a and 155b from the control logic 155 controllable.

In the mutual connection of the subtraction capacitor C _S with the sample-and-hold capacitor C _SH (in the form of a parallel connection of the two capacitors C _S and C _SH ) and the two reference potentials U _ref and GND during a switching cycle in each case a certain amount of charge from the sample Holding capacitor C _SH taken. In this case, a switching cycle is defined by that time period within which the subtraction capacitor C _{S is connected} once to the sample-and-hold capacitor C _SH and once to the two reference potentials U _ref and GND. The mutual connection of the subtraction capacitor C _S with the sample-and-hold capacitor C _SH and the two reference potentials U _ref and GND is continued until, due to the successive charge removal, the output voltage of the sample-and-hold circuit 110 has dropped so far that it is less than or equal to the measurement range of the analog-to-digital converter 120 is (then according to the embodiment shown here, the output of the comparator 130 negative). Then by the analog-to-digital converter 120 in a known manner an analog-to-digital conversion performed, which at the output terminal 182 the corresponding digital output signal U yields _digital .

It should be noted that preferably the digital output signal U _{digital is} not the primary output signal of the analog-to-digital converter 120 is. Rather, the digital output signal U is preferably a _digitally modified output signal into which the voltage differences associated with the respective charge withdrawals are included. The digital output signal U _digital then does not correspond to the output voltage of the sample-and-hold circuit, which is reduced by successive charge withdrawals 110 but actually at the input port 102 applied analog input voltage U _analog .

According to the embodiment shown here, the subtraction capacitor C _S can be used using a total of four switching elements 162a -D be connected to the sample and hold capacitor C _SH . Depending on the activation of the individual switching elements 162a -D the subtraction capacitor C _S with in principle two different polarities via the two terminals A and B with the sample-and-hold capacitor C _{SH are} connected. This can be done by the control logic 155 a deliberate reversal of the subtraction capacitor C _{S are made} in relation to the sample-and-hold capacitor C _SH , whereby the charge subtraction can be made in relatively large portions and still with high accuracy.

In summary, it remains to be stated: In order to be able to carry out an accurate and reproducible analog-to-digital conversion, a known reference voltage of high accuracy is always required in the case of the circuit arrangement described here. This reference voltage can also be significantly smaller than the maximum voltage U _{to be} measured _analogously . If the reference voltage z. B. 1/2 times as large as the maximum voltage to be measured U _analog , it is sufficient, the analog-to-digital converter 120 instead of, for example, only 3 volts to 1.5 volts interpreted. If the voltage to be measured is then less than 1.5 volts, then without a charge subtraction with the analog-to-digital converter 120 converted in a known manner.

Is the voltage to be measured, however, _analog U is greater than 1.5 volts, then the existing reference voltage U _ref in the form of a Ladungssubtraktion from the output 112 the sample-and-hold circuit 110 subtracted voltage. Thus, the circuit described is capable of resolving the analog-to-digital conversion compared to the standard resolution of the analog-to-digital converter 120 to double. For a 12-bit analog-to-digital converter 130 then results instead of a resolution of 3.0 volts: 4096 = 732.42 μVolt per bit, a double resolution of 1.5 volts: 4096 = 366 μVolt per bit. A μV stands for 10 ^-6 volts.

As detailed above, the subtraction can be advantageously performed in the sample and hold circuit 110 done, z. B. by adding two scanned across the capacitances C _SH and C _S values (1x measured value, 1x reference value). If the reference voltage z. B. to 0.5 V, then can be subtracted by appropriate multiple charge subtraction, a voltage of 1.5 volts or 2.0 volts. This improves resolution down to 0.5 volts: 4096 = 122 μV per bit.

LIST OF REFERENCE NUMBERS

102

Input connection (analog)

110

Sample and hold circuit

112

Output of sample-and-hold circuit

120

Analog to digital converter

130

Comparing means / comparator

135

Reference signal generator

150

Ladungssubtraktionseinrichtung

155

control logic

155a

control line

155b

control line

162a-d

switching element

164a, b

another switching element

182

Output connection (digital)

S _SH

switch

C _SH

Sample and hold capacitor

C _S

Subtraktionskondensator

U _ref

Reference signal level / reference potential

GND

Dimensions

U _analog

input

U _digital

output

A

first terminal sample-and-hold capacitor

B

second terminal sample-and-hold capacitor

C

Output of the comparator / comparator

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 5748129 [0004]

Claims (11)

Electronic circuit arrangement for converting an analog input signal (U _analog ) into a digital output signal (U _digital ), the electronic circuit arrangement having an input connection ( 102 ) for supplying the analog input signal to be converted (U _analog ), a sample and hold circuit ( 110 ), which on the input side with the input terminal ( 102 ) and which comprises a switch (S _SH ) and a sample-and-hold capacitor (C _SH ), an analog-to-digital converter ( 120 ), which on the input side with an output ( 112 ) the sample and hold circuit ( 110 ) and which is set up, one at the output ( 112 ) the sample and hold circuit ( 110 ) to convert applied signal levels into the digital output signal (U _digital ), an output terminal ( 182 ) for outputting the converted digital output signal (U _digital ), a comparison device ( 130 ), which with the output ( 112 ) the sample and hold circuit ( 110 ) and which is arranged in such a way that at the output ( 112 ) the sample and hold circuit ( 110 ) to compare applied signal levels with a reference signal level (U _ref ), and a charge subtractor ( 150 ) connected to an output (C) of the comparator ( 130 ) and which is set up as a function of an output signal of the comparison device ( 130 ) to remove a predetermined amount of charge from the sample and hold capacitor (C _SH ), so that the at the output of the sample-and-hold circuit (C _SH ) 110 ) applied signal level is smaller than the reference signal level (U _ref ). Electronic circuit arrangement according to the preceding claim, further comprising a reference signal generator ( 135 ) for providing the reference signal level (U _ref ). Electronic circuit arrangement according to the preceding claim, wherein the reference signal generator ( 135 ) in the analog-to-digital converter ( 120 ) is implemented. Electronic circuit arrangement according to one of the preceding claims, wherein the charge subtraction device ( 150 ) has a subtraction capacitor (C _S ). Electronic circuit arrangement according to the preceding claim, the charge subtraction device ( 150 ) further comprising a control logic ( 155 ) and several switching elements ( 162a . 162b . 162c . 162d ), The control logic ( 155 ) on the input side with an output (C) of the comparison device ( 130 ) and - wherein the switching elements ( 162a . 162b . 162c . 162d ) of the control logic ( 155 ) are controllable, that the subtraction capacitor (C _S ) at least for a certain period of time with the sample-and-hold capacitor (C _SH ) is connectable. Electronic circuit arrangement according to the preceding claim, wherein the charge subtraction device ( 150 ) is formed such that the subtraction capacitor (C _S ) and the sample-and-hold capacitor (C _SH ) are connectable to each other in the form of a parallel connection. Electronic circuit arrangement according to one of the preceding claims 5 to 6, the charge subtraction device ( 150 ) further comprising a plurality of further switching elements ( 164a . 164b ), which depends on the control logic ( 155 ) are controllable such that the subtraction capacitor (C _S ) at least for a certain period of time with two reference potentials (U _ref , GND) is connectable. Electronic circuit arrangement according to the preceding claim, wherein a first reference potential with the reference signal level (U _ref ) is identical and / or the second reference potential is a ground potential (GND). Electronic circuit arrangement according to one of the preceding claims 7 to 8, wherein the switching elements ( 162a . 162b . 162c . 162d ) and the other switching elements ( 164a . 164b ) from the control logic ( 155 ) are controllable such that the subtraction capacitor (C _S ) alternately with the sample-and-hold capacitor (C _SH ) and with the two reference potentials (U _ref , GND) is connectable. Electronic circuit arrangement according to one of the preceding claims 7 to 9, wherein the switching elements ( 162a . 162b . 162c . 162d ) and the other switching elements ( 164a . 164b ) are arranged and the control logic ( 155 ) is arranged such that the subtraction capacitor (C _S ) with alternating polarity with the sample-and-hold capacitor (C _SH ) and / or with the two reference potentials (U _ref , GND) is connectable. Method for converting an analogue input signal (U _analogue ) into a digital output signal (U _digital ) by means of an electronic circuit arrangement comprising a sample-and-hold circuit ( 110 ) with a switch (S _SH ) and a sample-and-hold capacitor (C _SH ) and an analog-to-digital converter ( 120 ), wherein the analog-to-digital converter ( 120 ) with an output ( 112 ) the sample and hold circuit ( 110 ), the method comprising supplying the analog input signal (U _analog ) to be converted to an input terminal ( 102 ) of the electronic Circuit arrangement connected to an input of the sample-and-hold circuit ( 110 ), comparing one at the output ( 112 ) the sample and hold circuit ( 110 ) applied signal level with a reference signal level (U _ref ) by means of a comparison device ( 130 ) connected to the output of the sample and hold circuit ( 110 ), removing a predetermined amount of charge from the sample-and-hold capacitor (C _SH ) in response to an output signal of the comparison device ( 130 ) by means of a charge subtraction device ( 150 ) connected to an output (C) of the comparator ( 130 ), so that the at the output ( 112 ) the sample and hold circuit ( 110 ) is less than the reference signal level (U _ref ), converting the at the output ( 112 ) the sample and hold circuit ( 110 ) present signal level in the digital output signal (U _digital ), and outputting the converted digital output signal (U _digital ) at an output terminal ( 182 ) of the electronic circuitry.

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