DE102009061167B3 - Semiconductor body with a connection cell - Google Patents

Abstract

Semiconductor body having a first terminal (VDD) for supplying an upper supply potential and having a first and a second terminal cell (IO1, IO2) spaced apart from each other, further comprising a dissipation structure (PCL) connected between the first and second terminal cells (PCL). IO1, IO2) is constructed in a p-doped substrate (PSUB) having the dissipation structure (PCL) - a first and a second p-channel field effect transistor structure (PMOS3, PMOS4) arranged in respective n-doped wells (NW61, NW62 ) are constructed substantially parallel to the first and second terminal cell (IO1, IO2); and a diode structure (TRG) arranged with a p-doped region in a further n-doped well (NW63) in a cross section of the semiconductor body spatially between the n-doped wells (NW61, NW62) of the first and the second p-channel Field-effect transistor structure (PMOS3, PMOS4) is constructed, wherein the diode structure (TRG) is arranged to control the first and the second p-channel field effect transistor structure (PMOS3, PMOS4) as a discharge in an electrostatic discharge in the semiconductor body.

Description

The invention relates to a semiconductor body having at least one terminal cell, which in particular has a pad as input contact and / or output contact.

Terminal cells are used in semiconductor integrated circuits to make contact from the integrated circuit to the outside. In particular, such contacts serve to supply supply voltages or reference voltages. Furthermore, the integrated circuit via the contacts control signals, data signals or other arbitrary signals can be supplied or tapped from her.

In the operation of the integrated circuit, error situations may occur, for example when overvoltages are applied to the contacts or due to electrostatic discharges. In order that such overvoltages do not lead to damage or destruction of the integrated circuit, protective elements are often used, via which the resulting currents can be dissipated. In many cases, field effect transistor structures are used for this purpose. Due to the structure of the field effect transistor structures, however, parasitic bipolar structures result in conjunction with the substrate of the semiconductor body of the integrated circuit, over which significant current flows occur in the event of a fault. In particular, current flows are generated in the substrate, which lead to a permanently low-impedance state of the parasitic bipolar structures under appropriate voltage conditions. This can in many cases lead to the destruction of the semiconductor body with the integrated circuit. Such a condition is also called a latch-up effect.

In order to limit the consequences of such a latch-up effect, it is proposed in conventional circuits to detect a current in the substrate and, in the event of detection, to separate the circuit via dedicated switches from corresponding terminals or contacts. However, since a fault current has already been generated in the substrate in this case, destruction of the semiconductor circuit can under certain circumstances not be prevented, in particular since significantly many charge carriers are already in motion in the substrate. Furthermore, a function of the circuit is limited or completely interrupted by the separation of the contact from the circuit.

document US 2006/0223258 A1 is concerned with a manufacturing method for a semiconductor body with complementary metal oxide semiconductor transistors and a bipolar transistor. A protection arrangement comprises a supply terminal, a connection cell with a connection area, a trigger element and an ESD protection element with two bipolar transistors. With ESD the term electrostatic discharge, English: electrostatic discharge abbreviated. A series circuit of diodes of the trigger element is coupled to a bipolar transistor of the ESD protection element.

document EP 0660410 A2 describes multi-slot I / O structures. In this case, a semiconductor body comprises a cell having a connection surface which is separated from an edge of the semiconductor body via an ESD circuit. According to a further embodiment, two adjacent signal cells are separated by an ESD circuit from the edge of the semiconductor body.

It is therefore desirable to provide a semiconductor body with a terminal cell that is better protected against damage due to overvoltages.

Such a semiconductor body is given by the subject of independent claim 1. Further developments and special embodiments are the subject of the dependent claims.

In one embodiment of a semiconductor body having a connection cell, the latter has a connection area, a first connection for supplying an upper supply potential and a second connection for supplying a lower supply potential. In this case, the upper supply potential is in particular higher than the lower supply potential. The connection cell furthermore has a p-channel field-effect transistor structure constructed in the semiconductor body, which has a p-doped first sensor region at a distance from its drain region. Furthermore, an n-channel field-effect transistor structure is constructed in the semiconductor body, which has an n-doped second sensor region at a distance from its drain region.

Here, in the p-channel field effect transistor structure, the drain region is electrically connected to the pad, a source region is electrically connected to the first terminal, and the first sensor region is connected to the second terminal via a first resistor element and directly to a gate. Connection of the n-channel field effect transistor structure electrically connected. Furthermore, in the n-channel field effect transistor structure, the drain region is electrically connected to the pad, a source region is electrically connected to the second terminal, and the second sensor region is connected via a second resistor element to the first terminal and directly to a gate terminal of the p Channel field effect transistor structure electrically connected.

In the case of a positive overvoltage at the pad, a current flow from the drain region of the p-channel field effect transistor structure is not guided into the substrate of the semiconductor body, but flies over the first sensor region and the first resistance element to the second connection. This results in a voltage drop across the first resistive element, which opens the gate of the n-channel field effect transistor structure. As a result, the overvoltage can flow away from the pad via the drain and source of the n-channel field effect transistor structure to the second terminal. A current flow into the substrate of the semiconductor body is thus effectively prevented.

Similarly, if there is a negative overvoltage on the pad, or a voltage much lower than the lower supply potential on the second pad, the pad will respond. In this case, a current flow is generated from the drain region of the n-channel field-effect transistor structure to the second sensor region, and thus a discharge of charge carriers into the substrate is prevented. From the second sensor region, the current flows via the second resistance element to the first connection, the current value being negative in this assumed current direction. The voltage drop across the second resistive element drives the gate of the p-channel field effect transistor structure so that a fault current can drain across the drain region and the source region of the p-channel field effect transistor structure to the first port, again with a negative current value. Also in this case, an outflow of charge carriers into the substrate, which could destroy the semiconductor body, is prevented.

Preferably, the first sensor region and the drain region of the p-channel field effect transistor structure with an intermediate region form a PNP bipolar structure, for example in the form of a lateral bipolar transistor. For example, the intermediate region is an n-doped well in which the drain region and the first sensor region are formed.

Further preferably, the second sensor region and the drain region of the n-channel field effect transistor structure with an intermediate region form an NPN bipolar structure, again in the form of a lateral bipolar transistor, for example.

With the bipolar structures deliberately formed by the sensor regions, the influence or the significance of other occurring parasitic bipolar structures is reduced. In particular, the sensor regions are arranged in the semiconductor body in such a way that charge carriers which are set in motion by overvoltages are preferably drawn to the sensor regions and not into the substrate.

In an embodiment, the semiconductor body comprises a p-doped substrate in which the p-channel field effect transistor structure and the n-channel field effect transistor structure are constructed. For example, the p-channel field effect transistor structure is constructed in a first n-doped well within the substrate, wherein the associated drain region and the associated source region are each constructed as p-doped regions within the first n-doped well and the first n-doped well is electrically connected to the first terminal.

In an embodiment based thereon, the first sensor region is constructed within the substrate, wherein the first sensor region is more p-doped than the substrate.

However, in an alternative and preferred embodiment, the first sensor region is constructed within the first n-doped well. By way of example, the drain region, the n-doped well and the p-doped sensor region form a lateral PNP bipolar transistor.

In a further embodiment, the first sensor region is arranged parallel to the drain region of the p-channel field-effect transistor structure. Alternatively, the first sensor region is arranged at least partially in arcuate fashion around the drain region and the source region of the p-channel field-effect transistor structure. In both cases, the first sensor region serves as a collecting region for charge carriers emanating from the drain region of the p-channel field-effect transistor structure or, according to another consideration of the current direction, as a primary charge carrier supplier.

In one embodiment, the n-channel field effect transistor structure is constructed in a second n-doped well within the substrate. In this case, the drain region of the n-channel field-effect transistor structure is constructed as an n-doped region within the second n-doped well and is more heavily doped than the second n-doped well. The source region of the n-channel field-effect transistor structure is constructed in a p-doped well within the second n-doped well. In this case, the p-doped well is electrically connected to the second connection. In this embodiment, the second sensor region is arranged at a distance from the second n-doped well. Accordingly, for example, the second sensor region, the substrate region located between the second sensor region and the second n-doped well, and the second n-doped well form a lateral NPN transistor over which, in the event of a fault, a current flows which is used to trigger the p-channel transistor. Field effect transistor leads. By the lateral arrangement of the second sensor and the second n-doped well, a charge carrier flow in the substrate is limited to the intermediate substrate region, so that here too a significant current flow into the p-doped substrate is prevented.

By way of example, the second sensor region is arranged spaced parallel to the second n-doped well. Alternatively, the second sensor region is arranged at least partially in an arcuate manner around the second n-doped well. As previously stated for the first sensor region, the second sensor region in the described embodiments also serves as a charge carrier supplier during a current flow via the lateral NPN bipolar transistor.

In the event of a fault, ie in the case of a positive or negative overvoltage, the respective current flowing across the sensor regions or the lateral bipolar transistors is low. Namely, the largest portion of each resulting fault current is derived via the respectively activated field effect transistor structure, which is preferably designed for carrying large currents. A latch-up effect is thus prevented or eliminated by deriving the respective latch-up current through the field-effect transistor structures.

If a plurality of terminal cells of the type described are provided in a semiconductor body, they can readily be placed close to one another without necessarily providing non-conductive protective areas between the terminal cells. This is possible because in the described structures of the terminal cells no significant current flow in the substrate is produced, which could adversely affect adjacent terminal cells.

The function of the connection cell is also guaranteed in the event of an overload, that is to say in the case of a positive or negative overvoltage, because a connection to the first and second connection for supplying the supply potentials is not interrupted. A signal state at the pad is thus not changed by the protection arrangement with the sensor areas.

In some embodiments of semiconductor bodies, it is provided that, in addition to terminal cells, also discharge elements for electrostatic discharges, English: electrostatic discharge, ESD, are provided. Such a diverting element usually has a trigger element such as a diode, which triggers an actual diverting element in the ESD case in order to be able to safely divert the overvoltage as a result of the ESD event. If such a diode is particularly sensitive to current flows, there is always the danger that unwanted tripping of the ESD dissipation element occurs.

In particular if such a diverting element with a diode is arranged next to a terminal cell, charge carriers which pass from the terminal cell into the substrate can generate a current flow in the diode, which leads to undesired tripping. This can be particularly critical if the diode is arranged directly next to the connection cell in the semiconductor body.

Accordingly, the previously described principle to prevent unwanted charge carriers in the substrate or to intercept in time, be used to prevent unwanted current in a trigger diode of a diverter.

For example, a semiconductor body has a first terminal cell and a second terminal cell, which is constructed at a distance from the first terminal cell. Furthermore, the semiconductor body comprises a dissipation structure, which is constructed between the first and the second terminal cell in the substrate. In this case, the dissipation structure has a first and a second p-channel field-effect transistor structure, which are constructed in respective n-doped wells, and a diode structure, which has a p-doped region in another n-doped well, between the n-doped wells the first and second p-channel field effect transistor structure is constructed. In this case, the diode structure is set up to control the first and second p-channel field-effect transistor structures as diverting elements in the case of an electrostatic discharge in the semiconductor body.

With the proposed structure, on the one hand, the path for charge carriers, which possibly reach from the terminal cell into the substrate, is increased to the diode structure in comparison to conventional arrangements. Thus, low charge carrier concentrations do not even reach the diode structure as a carrier element, whereby a first protection is ensured.

In addition, the respective n-doped wells of the first and second p-channel field effect transistor structures are preferably connected to the first terminal for supplying the upper supply potential or alternatively to a terminal for another, higher potential. Thus, charge carriers that enter the substrate from the adjacent connection cells are preferably accommodated in the respective n-doped wells, so that they can not get to the diode structure located between the p-channel field effect transistor structures. Consequently, a sensitive trigger structure with diode is also undesirable Triggers protected by charge carriers in the substrate.

In one embodiment, the further n-doped well of the diode structure is electrically connected to the first terminal via a third resistance element and directly to gate terminals of the first and second p-channel field effect transistor structures. This ensures tripping by the diode structure in the ESD case.

The described arrangement of connection cells and diverted structure located therebetween can be formed with conventional connection cells. However, in an advantageous embodiment, one or both adjacent connection cells are designed in accordance with the connection cell described above having first and second sensor regions. Thus, even for particularly sensitive cases, sufficient protection against unintentional triggering of the dissipation structure due to charge carriers in the substrate can be prevented.

The invention will be described below with reference to several embodiments with the aid of the figures. Like reference numerals refer to similar elements or structures in the figures.

Show it:

1 A first embodiment of a semiconductor body with a connection cell as an electrical block diagram and as an arrangement overview in the semiconductor body,

2 a further embodiment of a semiconductor body with a connection cell in the lateral cross-section,

3 FIG. 2 shows a further exemplary embodiment of a semiconductor body with a connection cell in a schematic plan view, FIG.

4 Yet another embodiment of a semiconductor body with a connection cell in a schematic plan view,

5 an embodiment of a semiconductor body with two terminal cells and intervening Ableitstruktur, and

6 a further embodiment of a semiconductor body with two terminal cells and a discharge structure in the lateral cross section and as an electrical block diagram.

1 shows an embodiment of a semiconductor body with terminal cell, wherein in the right half of a plan view of the semiconductor body and in the left half a block diagram of the terminal cell are shown. The semiconductor body comprises a p-channel field effect transistor structure PMOS, in which a p-doped first sensor region PSEN is embedded. The semiconductor body further comprises an n-channel field effect transistor structure NMOS to which an n-doped second sensor region NSEN is arranged at a distance. Furthermore, a pad PAD is provided in the semiconductor body or on the semiconductor body.

It can be seen from the block diagram on the left side that the pad PAD is directly electrically connected to respective drain terminals DP, DN of the p-channel structure PMOS and the n-channel structure NMOS. A source terminal SP of the p-channel structure PMOS is connected directly to a first terminal VDD, via which an upper supply potential can be fed. The bulk port BP of the p-channel structure PMOS is connected to the source terminal SP.

In the p-channel structure PMOS, a lateral PNP bipolar transistor LPNP is formed whose emitter terminal electrically corresponds to the drain terminal DP and whose collector terminal corresponds to the first sensor area PSEN. The base of the bipolar transistor LPNP is formed by a base region of the p-channel structure, for example an n-doped well, which is electrically connected to the first terminal VDD.

Similarly, in the n-channel structure NMOS, the source terminal SN is connected to a second terminal VSS for supplying a lower supply potential, wherein a bulk terminal BN of the n-channel structure NMOS also to the source terminal SN and The second connection VSS is connected. In this case, the upper supply potential is higher in voltage than the lower supply potential.

In the n-channel structure NMOS, a lateral NPN bipolar transistor LNPN is formed, inter alia, by the second sensor region NSEN, whose collector terminal corresponds to the second sensor region NSEN and whose emitter terminal corresponds to the drain terminal DN of the n-channel structure NMOS. The base terminal of the bipolar transistor LNPN is formed by a base region of the n-channel structure NMOS and electrically connected to the second terminal VSS.

The first sensor area PSEN or the collector of the transistor LPNP is connected via a first resistance element R1 to the second terminal VSS and directly to a gate terminal GN of the n-channel structure NMOS. Likewise, the second sensor region NSEN or the collector of the transistor LNPN via a second resistance element R2 with the first terminal VDD and directly with a gate terminal GP of the p-channel structure PMOS electrically connected.

In the case of a positive overvoltage, that is to say a voltage which is greater than the upper supply potential at the terminal VDD, a current flow via the collector and emitter is produced across the bipolar transistor LPNP which generates a voltage drop across the resistor element R1. This voltage drop causes a positive voltage ratio between the gate terminal GN and the source terminal SN, so that the n-channel structure NMOS becomes conductive. Thus, the pad PAD is shorted to the second terminal VSS, so that the overvoltage on the pad PAD can discharge via a current through the n-channel structure NMOS.

Accordingly, when the positive overvoltage occurs, a small current has developed across the lateral bipolar transistor LPNP, as well as a larger short-circuit current across the channel of the n-channel structure NMOS, which is designed for corresponding current loads.

In case of a negative overvoltage, i. H. a voltage which is lower than the lower supply potential, at the pad PAD, corresponding operations result with the respective complementary structures. In particular, a current flow which is fed by the first terminal VDD via the second resistance element R2 is generated via the second sensor region NSEN as collector and the drain region DN of the n-channel structure NMOS as emitter of the lateral bipolar transistor structure LNPN. Accordingly, by the voltage drop across the second resistance element R2, the potential at the gate terminal GP of the p-channel structure is pulled down, so that the channel of the p-channel structure becomes conductive. Consequently, a short-circuit current between the first terminal VDD and the pad PAD arises, which preferably discharges the negative overvoltage. Again, this results in a low current through the bipolar structure LNPN and a larger current through the field effect transistor PMOS. Because of the directed and controlled current flows, no charge carriers enter the substrate of the semiconductor body, which is thereby protected against damage or destruction.

In the block diagram in 1 For the sake of completeness, it is pointed out that the illustrated bipolar transistor structures LPNP and LNPN are not specially designed components, but rather arise as parasitic but desired structures only through correspondingly doped regions in the semiconductor body or the field-effect transistor structures.

2 shows a cross section in the side view of an embodiment of a connection cell in the semiconductor body. The terminal cell is constructed in a p-doped substrate PSUB. The p-channel structure PMOS is formed in an n-doped well NW1 within the substrate PSUB, wherein the well NW1 is electrically connected to the first terminal VDD. A source region SP is formed within the well NW1 by a heavily p-doped region, which is also electrically connected to the first terminal. A drain region DP of the p-channel structure PMOS is formed by a p-doped region PW1, which is electrically connected to the pad PAD.

A gate electrode GP is arranged above the channel region between the source region SP and the drain region DP. Furthermore, a further p-doped region PW3, which acts as a sensor region PSEN, is located at a distance from the drain region DP. The region PW1, the well NW1 and the region PW3 form a lateral PNP bipolar structure LPNP, in which the drain region DP of the p-channel structure PMOS acts as an emitter. The sensor region PSEN is the collector and the well NW1 forms the base of the bipolar structure LPNP.

For the n-channel field-effect transistor structure NMOS, a further n-doped well NW2 is provided in the substrate PSUB, in which a heavily n-doped region DN is provided as the drain region of the n-channel structure NMOS. This drain region DN is electrically connected to the pad PAD. Furthermore, a p-doped well PW2 is provided within the n-doped well NW2, which serves as a bulk region of the n-channel structure NMOS and which is electrically connected to the second terminal VSS. In this p-doped well PW2, another heavily n-doped region SN is introduced, which serves as a source region of the n-channel structure NMOS and is also electrically connected to the second terminal VSS. Above the channel between the drain region DN and the source region SN is provided a gate electrode GN, which is electrically connected to the sensor region PSEN. Spaced apart from the second n-doped well NW2, a third n-doped well NW3 is arranged in the substrate PSUB, which forms a second sensor region NSEN, which is electrically connected to the gate connection GP of the p-channel structure PMOS.

The well NW3, the substrate PSUB and the well NW2 form an NPN bipolar structure LNPN with the sensor region NSEN as collector, the substrate PSUB as base and the second well NW2 as emitter.

The remaining circuitry of the semiconductor body or of the connection cell with the resistance elements R1, R2 corresponds to that in FIG 1 illustrated and described arrangement. Accordingly, in the case of a positive overvoltage on the pad PAD, the lateral bipolar transistor LPNP is turned on, so that the resulting current flow via the resistance element R1 opens the n-channel structure NMOS, via which the overvoltage is conducted to the second terminal VSS. Likewise, in the case of a negative overvoltage, the lateral bipolar transistor LNPN is brought into conduction, so that the resulting current via the resistance element R2 opens the p-channel structure PMOS. As a result, the overvoltage is dissipated by a current flow between the first terminal VDD and the pad PAD.

Since the n-doped well NW1 and the bulk region BP form the basis for the bipolar structure LPNP, there is no charge carrier flow into the substrate PSUB. An undesirable current flow in the substrate PSUB can thus be effectively prevented.

Similarly, in the case of the negative overvoltage, the charge carrier flow takes place in the n-channel structure NMOS or in the lateral bipolar transistor LNPN. Charge carriers from the drain region DN or the second n-doped well NW2 move primarily on the surface of the semiconductor body PSUB to the second sensor region NSEN. Thus, although a charge carrier flux at the surface takes place in the substrate, the charge carrier distribution in the case of overvoltage decreases towards deeper regions of the substrate PSUB. In other words, a significant current flow in the substrate PSUB is also prevented by the second sensor region NSEN.

In an alternative embodiment, the first sensor area PSEN can also be arranged in the substrate PSUB, analogous to the arrangement of the second sensor area NSEN. In this case, the sensor region PSEN is designed as a p-doped well, in which the p-doping is stronger than that of the substrate PSUB.

3 shows a plan view of a possible embodiment of the semiconductor body with terminal cell. The n-doped wells NW1, NW2 are in this case designed as elongated trays, in which the respective remaining regions SP, DP, PSEN or DN, BN, SN are introduced. The first sensor region PSEN is hereby arranged at a parallel distance from the p-doped well PW1 or the drain region DP. Similarly, the second sensor region NSEN is arranged in the substrate PSUB parallel to the second well NW2. Thus, in each case charge carriers in the full width of the respective drain region DP, DN can be picked up by the sensor regions PSEN, NSEN in order to prevent flow into the substrate PSUB.

An alternative embodiment of the semiconductor body with connection cell is shown in FIG 4 shown. In this exemplary embodiment, the first sensor region PSEN curves around the source region SP and the drain region DP of the p-channel structure PMOS, the sensor region PSEN circulating within the well NW1 acting as the bulk region BP. In an analogous manner, the third n-doped well NW3 circumscribes the second n-doped well NW2 of the n-channel structure NMOS as the second sensor region NSEN.

With the illustrated circumferential structure of the sensor regions PSEN, NSEN, charge carriers emanating from the field-effect transistor structures PMOS, NMOS can be tapped or removed in an improved manner. As a result, charge carrier currents in the substrate PSUB are prevented even more effectively.

At the in 4 In the embodiment shown, the sensor areas PSEN, NSEN completely surround the respective field-effect transistor structures PMOS, NMOS. In a modification thereof, however, embodiments which comprise a combination of the embodiments of FIG 3 and 4 represent. In other words, the sensor regions PSEN, NSEN can also circulate the respective structures only in the opened arc, whereby preferably the respective drain region DP, DN of the structures PMOS, NMOS is included, since of these the highest charge carrier concentration to be accommodated is to be expected.

5 shows a further embodiment of a semiconductor body with two connection cells IO1, IO2 with an underlying Ableitstruktur PCL. The connection cells IO1, IO2 each have a p-channel field effect transistor structure PMOS1, PMOS2, an n-channel field effect transistor structure NMOS1, NMOS2 and pads PAD1, PAD2. The connection cells can basically have any desired structure, but they preferably have a structure according to one of the previously described embodiments.

The dissipation structure PCL has two halves of a preferably symmetrically divided p-channel field-effect transistor, between which a diode structure TRG is arranged. The indication ½PMOS in the illustrated p-channel field-effect transistor structures PMOS3, PMOS3 indicates that the structures PMOS3, PMOS4 used here are dimensioned approximately half as large in comparison to a conventional p-channel field-effect transistor leakage structure.

6 shows an exemplary cross section of such a structure 5 , In this case, for the first connection cell IO1 in the substrate PSUB, an n-doped well NW64, for the second connection cell IO2 an n-doped well NW65, for the p-channel field effect transistor structures PMOS3, PMOS4 n-doped wells NW61, NW62 and for the diode structure an n-doped well NW63 provided. Other semiconductor regions, in particular for the connection cells IO1, IO2 and the field effect transistor structures PMOS3, PMOS4 are not shown for reasons of clarity. It is only indicated that the n-doped wells NW61, NW62 are electrically connected to the first terminal VDD.

The diode structure TRG has a heavily p-doped region in the n-doped well NW63, which forms a PN junction for the diode structure.

Below the cross-sectional view is in 6 a symbolic block diagram of the Ableitstruktur shown, in which the anode of the diode structure TRG is connected to the drain terminals of the p-channel structures PMOS3, PMOS4. The cathode of the diode structure TRG is connected directly to the gate terminals of the structures PMOS3, PMOS4 and to the first terminal VDD via a third resistance element R3. As already in cross section in 6 indicated, the bulk terminals and the source terminals of the structures PMOS3, PMOS4 are electrically connected to the first terminal VDD.

In the case of an electrostatic discharge, there is a flow of current through the diode element TRG, which aufsteuert the transistor structures PMOS3, PMOS4 by the voltage drop across the resistor element R3, so that they act as discharge elements for the electrostatic discharge. The tripping sensitivity of the dissipation structure PCL depends on the sensitivity of the diode structure TRG. In order to prevent the discharge structure from being triggered by the action of undesired charge carriers which do not originate from an electrostatic discharge, in the present exemplary embodiment the n-doped wells NW61, NW62 are arranged around the well NW63 of the diode structure TRG, so that charge carriers, the may possibly originate from the connection cells IO1, IO2 or their wells NW64, NW65, be intercepted by the wells NW61, NW62 and do not reach the well NW63.

Thus, in the in the 5 and 6 arrangement shown the same principle applied as in the terminal cells from the 1 to 4 in that charge carriers which otherwise could cause uncontrolled undesired effects in the substrate are intercepted by corresponding doped and contact regions before the aforementioned undesired effects occur.

Compared to a conventional dissipation structure, in which the trigger region or diode region TRG is placed directly next to the connection cell, significantly improved sensitivities with respect to undesired triggering of the diverting elements can be achieved with the proposed embodiment. In addition, the splitting of the p-channel field effect transistor structure, which is usually constructed in one piece into the two structures PMOS3, PMOS4, requires no additional space in the integration on the semiconductor body.

LIST OF REFERENCE NUMBERS

• VDD, VSS

  connection

  PMOS, PMOS1, PMOS2

  p-channel field-effect transistor structure

  PMOS3, PMOS4

  p-channel field-effect transistor structure

  NMOS, NMOS1, NMOS2

  n-channel field effect transistor structure

  PAD

  terminal area

  PSUB

  substratum

  PSEN, NSEN

  sensor range

  GP, GN

  Gate terminal

  BP, BN

  Bulk sector

  SP, SN

  Source region

  DP, DN

  Drain region

  R1, R2, R3

  resistive element

  NW1, NW2, NW3

  n-doped tub

  NW61, NW62, NW63

  n-doped tub

  NW64, NW65

  n-doped tub

  PW1, PW2, PW3

  p-doped tub

  PCL

  Ableitstruktur

  TRG

  diode structure

  IO1, IO2

  connection cell

  LPNP, LNPN

  lateral bipolar structure

Claims (14)

Semiconductor body having a first terminal (VDD) for supplying an upper supply potential and having a first and a second terminal cell (IO1, IO2), which are spaced apart from each other, further comprising a dissipation structure (PCL), which between the first and the second terminal cell (PCL) IO1, IO2) is constructed in a p-doped substrate (PSUB) having the dissipation structure (PCL) - a first and a second p-channel field effect transistor structure (PMOS3, PMOS4) arranged in respective n-doped wells (NW61, NW62 ) are constructed substantially parallel to the first and second terminal cell (IO1, IO2); and a diode structure (TRG), which is provided with a p-doped region in a further n-doped well (NW63) in a cross section of the semiconductor body spatially between the n-doped wells (NW61, NW62) of the first and the second p-channel field-effect transistor structure (PMOS3, PMOS4), wherein the diode structure (TRG) is set up in an electrostatic discharge in the semiconductor body, the first and the second p-channel field effect transistor structure (PMOS3, PMOS4) aufzusteuern as discharge elements. Semiconductor body according to claim 1, wherein the first and the second terminal cell (IO1, IO2) are constructed such that the first and the second terminal cell (IO1, IO2) each comprise: - a pad (PAD); The first port (VDD); - A second connection (VSS) for supplying a lower supply potential; A p-channel field effect transistor structure (PMOS) constructed in the semiconductor body and having a p-doped first sensor region (PW3, PSEN) at a distance from its drain region (DP); and An n-channel field-effect transistor structure (NMOS) constructed in the semiconductor body and having an n-doped second sensor region (NW3, NSEN) at a distance from its drain region (DN); in which - In the p-channel field effect transistor structure (PMOS), the drain region (DP) is electrically connected to the pad (PAD), a source region (SP) is electrically connected to the first terminal (VDD), and the first sensor region (PW3, PSEN) is electrically connected via a first resistance element (R1) to the second terminal (VSS) and directly to a gate terminal (GN) of the n-channel field effect transistor structure (NMOS); In the n-channel field effect transistor structure (NMOS) the drain region (DN) is electrically connected to the pad (PAD), a source region (SN) is electrically connected to the second connection (VSS), and the second sensor region (NW3, NSEN) via a second resistance element (R2) to the first terminal (VDD) and directly to a gate terminal (GP) of the p-channel field effect transistor structure (PMOS) is electrically connected, and - The semiconductor body comprises the p-doped substrate (PSUB), in which the p-channel field effect transistor structure (PMOS) and the n-channel field effect transistor structure (NMOS) are constructed. The semiconductor body according to claim 2, wherein the first sensor region (PW3, PSEN) and the drain region (DP) of the p-channel field effect transistor structure (PMOS) with a region therebetween form a pnp bipolar structure. Semiconductor body according to claim 2 or 3, wherein the second sensor region (NW3, NSEN) and the drain region (DN) of the n-channel field effect transistor structure (NMOS) with an intermediate region form an npn bipolar structure. Semiconductor body according to one of claims 2 to 4, wherein the p-channel field effect transistor structure (PMOS) in a first n-doped well (NW1) is constructed within the substrate (PSUB), wherein the associated drain region (DP) and the associated source region (SP) are each constructed as p-doped regions within the first n-doped well (NW1) and the first n-doped well (NW1) is electrically connected to the first terminal (VDD). Semiconductor body according to claim 5, wherein the first sensor region (PW3) is constructed within the substrate (PSUB), wherein the first sensor region (PW3) is more p-doped than the substrate (PSUB). Semiconductor body according to Claim 5, in which the first sensor region (PW3, PSEN) is constructed inside the first n-doped well (NW1). Semiconductor body according to one of Claims 5 to 7, in which the first sensor region (PSEN) is arranged parallel to the drain region (DP) of the p-channel field-effect transistor structure (PMOS). Semiconductor body according to one of claims 5 to 7, wherein the first sensor region (PSEN) at least partially arcuately circumferentially around the drain region (DP) and the source region (SP) of the p-channel field effect transistor structure (PMOS) is arranged. Semiconductor body according to one of claims 2 to 9, wherein the n-channel field effect transistor structure (NMOS) is constructed in a second n-doped well (NW2) within the substrate (PSUB), wherein The drain region (DN) of the n-channel field effect transistor structure (NMOS) is constructed as an n-doped region within the second n-doped well (NW2) and is more heavily n-doped than the second n-doped well (NW2); The source region (SN) of the n-channel field effect transistor structure (NMOS) is constructed in a p-doped well (PW2) within the second n-doped well (NW2); - The p-doped well (PW2) is electrically connected to the second terminal (VSS); and - The second sensor region (NW3, NSEN) spaced from the second n-doped well (NW2) is arranged. Semiconductor body according to Claim 10, in which the second sensor region (NW3, NSEN) is arranged parallel to the second n-doped well (NW2). Semiconductor body according to claim 10, wherein the second sensor region (NSEN) at least partially arcuately arranged circumferentially around the second n-doped well (NW2). Semiconductor body according to one of claims 1 to 12, wherein the further n-doped well (NW63) via a third resistance element (R3) to the first terminal (VDD) and directly to gate terminals of the first and the second p-channel field effect transistor structure (PMOS3, PMOS4) is electrically connected. A semiconductor body according to any one of claims 1 to 13, wherein the respective n-doped wells (NW61, NW62) of the first and second p-channel field effect transistor structures (PMOS3, PMOS4) are electrically connected to the first terminal (VDD).

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