DE102009046081B4 - Eutectic bonding of thin chips on a carrier substrate - Google Patents

Abstract

A method of manufacturing a semiconductor device (166) comprising the steps of:
a) a semiconductor chip (110) is produced on an output substrate (112), the semiconductor chip (110) being connected to the output substrate (112) in at least one support point (116), the semiconductor chip (110) being one of the output substrate (112) has remote front side (130) and a rear side (132) facing the starting substrate (112),
b) in at least one via step, at least one via filler material (142) is applied to the semiconductor chip (110), at least a partial area (140) of the rear side (132) being coated with the via filler material (142),
c) the semiconductor chip (110) is separated from the starting substrate (112), and
d) the semiconductor chip (110) is applied to at least one carrier substrate (150), the partial area (140) of the rear side (132) of the semiconductor chip (110) coated with the via filler material (142) having at least one bond pad (152) by means of a eutectic bonding process is connected on the carrier substrate (150).

Description

State of the art

So-called chip film processes for producing thin chips are known from the prior art. These chip film processes are, for example, in M. Zimmermann et al., “A Seamless Ultra-Thin Chip Fabrication and Assembly Technology”, Tech. Dig. IEDM, pp. 1010-1012, 2006. In chip film technology, special etching processes are used to create depressions on an initial substrate, in particular a carrier wafer made of conventional silicon, which are also referred to as “cavities”. These are made by manufacturing porous silicon and then removing porous silicon (APSM process). Silicon suitable for circuits is then applied to these cavities using an epitaxial process. This applied layer later forms the ultra-thin microchip. The desired circuit structure is then processed on this surface using conventional methods. Then, using a process known as “pick, crack and place” technology, the chip can be sucked in with a vacuum pipette (pick), broken off from the starting substrate (crack) and then placed on any other carrier substrate (place).

Processes for producing electrical contacts on or through a wafer or chip are also known from the prior art. For example, narrow holes with almost vertical walls can be produced in a wafer, insulated and then completely or partially filled with a conductive material, for example metal or silicon. Furthermore, eutectic bonding processes at the wafer level and for so-called “chip-to-wafer processes” are known from microsystem technology. In the field of applications, approaches for integrating sensor chips and evaluation ICs in a chip assembly are known.

From scripture DE 10 2008 001 738 A1 a method is known in which a membrane with micromechanical functionality is produced for the production of chips in a surface layer of a semiconductor substrate. The chip is then detached from the substrate assembly and soldered onto a carrier for further processing. A similar procedure is from Scripture DE 10 2008 040 521 A1 known.

Disclosure of the invention

Based on the known prior art, the present invention provides a method for producing semiconductor components which is able to improve a connection between semiconductor chips, in particular thin semiconductor chips, with carrier substrates. The proposed method is particularly suitable for producing sensor elements on the basis of semiconductor components, as will emerge in more detail from the following description.

The proposed method for producing a semiconductor element comprises the steps described below, which are preferably carried out in the order shown. In addition to the process steps mentioned, further process steps can be provided, and individual or several process steps can be carried out in parallel and / or repeatedly.

In a first method step, a semiconductor chip is produced on an initial substrate. The semiconductor chip is connected to the starting substrate in at least one support point and has a front side facing away from the starting substrate and a rear side facing the starting substrate. The semiconductor chip can in particular be designed as a thin chip, that is to say as a chip which has a thickness of less than 100 μm, preferably less than 50 μm and particularly preferably less than 20 μm. The semiconductor chip can in particular be produced on the basis of silicon. In particular, the above-described chip film method can be used for the production of the semiconductor chip, so that, for example, silicon can be used as the starting substrate, which has one or more cavities which are completely or partially filled with porous semiconductor material, in particular porous silicon. The semiconductor chip can then, for example, be built up epitaxially on the porous semiconductor material, and the porous material is preferably removed in the APSM process. As was also explained above, the semiconductor chip can be structured using conventional semiconductor processes and can be given at least one functionality.

In a second method step, which is also referred to below as a via step, at least one via filler material is applied to the semiconductor chip. In this case, at least a partial area of the rear side is coated with the via filler material. At the same time, as will be explained in more detail below, during the via step, at least one wall of at least one via, i.e. an opening in the semiconductor chip, for example a narrow opening perpendicular to the surface of the semiconductor chip, and at least one side wall of the semiconductor chip can be coated with the via filling material . A through-hole filling material is to be understood as meaning a material that has at least semiconducting properties has, so a semiconductor material or a conductor material. This via filling material can therefore serve as a carrier for the electrical current. In particular, as will be explained in more detail below, the via filler material can be a material that can be deposited from a liquid phase and / or a gas phase.

In a third method step, the semiconductor chip is separated from the starting substrate. During this separation, the support points are severed, for example by a mechanical and / or a chemical process. For example, the above-described “pick, crack and place” process can be used for this separation so that, for example, the semiconductor chip can be sucked in, rotated or tilted with a vacuum pipette and thus broken off from the starting substrate and finally made available for further use. However, other techniques are also possible in principle.

In a fourth method step, the semiconductor chip is applied to at least one carrier substrate, the partial area of the rear side of the semiconductor chip coated with the via filler material being connected to at least one bond pad by means of a eutectic bonding process on the carrier substrate. A bond pad is to be understood here as a conductive structure on the surface of the carrier substrate which can form a conductive connection with the at least one partial area. The at least one bond pad can, for example, have a rectangular shape, a frame shape, a circular shape or any other arbitrary shape, which can completely or partially follow the partial area of the rear side of the semiconductor chip that is coated with the via filler material, or which can also basically follow a different one May have structure.

This basic form of the proposed manufacturing method can advantageously be further developed in various ways. Thus, as shown above, additional method steps can be provided. It is also particularly preferred if, in the fourth method step, a eutectic bonding method is used to connect the partial area of the rear side of the semiconductor chip coated with the via filler material to the at least one bond pad. A eutectic bonding process is understood to mean a special connection process based on the formation of a connection using a eutectic alloy. A eutectic alloy is a mixture of conductor or semiconductor materials, for example silicon and gold or germanium and aluminum, in which the components of the mixture are in such a relationship that the melting temperature of the alloy is below the melting temperature of the individual elements lies.

The via filling material can in particular comprise at least one semiconductor material. In this case, germanium or silicon is particularly suitable. Correspondingly, the bond pad can comprise a material which can preferably form a eutectic alloy with the via filler material. For example, the bond pad can comprise aluminum which, in particular, can form a eutectic alloy with germanium as the via filler material. As an alternative or in addition, the bond pad can also comprise gold, for example, while the via filler material comprises silicon. Another possible material combination would be gold-germanium. In general, it is preferred if the bond pad comprises a metallic material, while the via filling material comprises a semiconductor material, wherein the metallic material and the semiconductor material can form a eutectic alloy.

In the via step, as already explained above, in addition to the coating of at least a partial area of the rear side of the semiconductor chip, further areas of the semiconductor chip can be coated. For example, vias can be provided, that is to say openings in the semiconductor chip which, for example, connect the front side to the rear side or connect at least one layer level of the semiconductor chip to at least one other layer level. These openings can, for example, have a round or polygonal cross section, with at least one wall of this via being able to be coated in the via step. Alternatively or additionally, at least one side wall of the semiconductor chip can be coated with the via filling material in the via step. A side wall is to be understood here as a surface of the semiconductor chip that differs from the front side and the rear side, preferably a surface which is essentially perpendicular to the front side and to the rear side, the front side and the rear side preferably being aligned parallel to one another. For example, in the above-described chip film method, this side wall can be produced in a so-called trenching step, in which the area and the outer edges of the semiconductor chip are defined. In this trenching process, mechanical or chemical separation processes can be used, for example DRIE (Deep Reactive Ion Etching).

In a further preferred embodiment of the method, at least one frame is produced on the rear side in the via step. In particular, it can be act as a closed framework. This frame can, for example, be applied to the side edges of the rear side of the semiconductor chip and, for example, follow these side edges. The frame can preferably have a width which is less than 100 μm, preferably less than 50 μm, in particular 10 μm or less or even only 1 μm. After the semiconductor chip has been applied to the carrier substrate, an interspace is created within the frame, in particular a hermetically sealed interspace. This gap is delimited by the rear side of the semiconductor chip, a front side of the carrier substrate facing the semiconductor chip, and the frame. In addition, further structures can be provided for the purpose of delimitation. The closed space can, for example, as will be explained in more detail below, be used as a reference vacuum of a pressure sensor. A hermetically sealed interspace is understood to mean an interspace in which an exchange of gas from the interspace with the surroundings of the semiconductor component takes place much more slowly, preferably on a time scale of several months or even several years, in particular much more slowly than normal times of use of the semiconductor component.

In the via step, in particular an isotropic deposition method can be used, preferably a conformal deposition method, i.e. a deposition method in which the deposited material at least partially follows the outer contours of the semiconductor chip or other components by means of contact filler material. In particular, liquid phase deposition processes and / or gas phase deposition processes are suitable here, for example CVD processes (Chemical Vapor Deposition), for example LPCVD processes (low pressure CVD).

As already shown above, the semiconductor chip can in particular be configured in such a way that it comprises one or more functional elements of the semiconductor component. In particular, the semiconductor chip can comprise at least one of the following elements: an integrated circuit; a sensor structure; a micromechanical structure. These functional elements can be arranged wholly or partially on the semiconductor chip and can be produced by means of conventional methods, as are known to the person skilled in the art from semiconductor technology.

Further possible developments of the invention relate to the implementation of the via step. For example, at least one insulating material can in particular be applied to the semiconductor chip before the via step. This insulating material can be, for example, an organic or an inorganic material. The use of dielectric layers, for example silicon oxide layers, is particularly preferred. As an alternative or in addition to the use of such an insulating material, which is intended to at least partially prevent electrical contact between the via filling material and certain functional elements of the semiconductor chip, other processes can also be used. For example, CMOS processes can be used in which the semiconductor chip is used at least in some areas with an insulation doping, for example in order to avoid short circuits. Again, as an alternative or in addition, the via filling material can be at least partially removed again from the semiconductor chip after the via step. For example, conventional semiconductor processes of a wet-chemical or dry-chemical nature can be used for this removal, for example wet-chemical or dry etching processes. In this regard, reference can be made to known etching processes. So-called lift-off processes are also fundamentally conceivable, i.e. processes in which areas of the semiconductor chip that are not to be coated with the via filling material are previously coated with a layer which is removed again from the semiconductor chip after the via step.

Further possible developments of the invention relate to the configuration of the semiconductor chip. As shown above, the semiconductor chip can in particular be produced using a chip film method. Accordingly, it is particularly preferred if the semiconductor chip comprises a monocrystalline semiconductor membrane, in particular a monocrystalline silicon membrane. However, other semiconductor materials are also possible in principle. In addition to monocrystalline material, preferably silicon, the support point can also comprise a porous material, preferably porous silicon.

In addition to the proposed method in one or more of the configurations described above, a semiconductor component is also proposed which can be produced by a method in accordance with one or more of the embodiment variants described. In particular, the semiconductor component can be selected from the following semiconductor components: a pressure sensor; an inertial sensor; an acceleration sensor; a switch. In general, the semiconductor component can therefore be designed entirely or partially, in particular as a sensor element, and / or comprise such a sensor element.

The proposed invention can therefore be used to produce semiconductor components which can in particular comprise thin chips and which can have vias. In addition to the electrical feed-through, the vias can simultaneously take on the task of creating a hermetically sealed and space-saving mechanical connection between the semiconductor chips, in particular thin chips, and basically any carrier substrates, for example printed circuit boards, lead frames or carrier substrates with complex mechanical and / or electrical design, for example To enable carrier chips such as ASICs (Application Specific Integrated Circuit). In this case, the via filling material can simultaneously serve as a material component for eutectic bonding of the semiconductor chip to the carrier substrate. Thin chips with ICs and / or sensor structures with vias can be produced on a monocrystalline silicon membrane with support points, for example by means of the chip film method described above. The via filler material, for example germanium, can then also be deposited in the same deposition process on the underside of the membrane, that is to say the rear side of the semiconductor chip, in an area adjoining the via. The thin chips can be placed on metal bond pads, for example aluminum, of a carrier substrate, and a eutectic bond can be produced between the via filling material and the bond pad.

By means of the proposed method, in particular different types of micromechanical sensors can be implemented, in particular on a carrier IC chip as the carrier substrate. The semiconductor chip, whereby several semiconductor chips can also be provided, in particular as a thin chip, as a membrane for pressure sensors, as a finger structure for inertial sensors, as a switch, as a second counter electrode for z-acceleration sensors or in some other way as part of a sensor element.

With the proposed method and the proposed semi-conductor elements, it is particularly advantageous that the optional eutectic bond can be designed to be stable and hermetically sealed even with a small connection width. Small bond frame widths or through contacts can be implemented, in particular widths of less than 10 μm. With the proposed method, semiconductor chips, in particular thin chips, can also be bonded stress-free, so that a low reject rate and a long service life of the semiconductor components can be achieved. Furthermore, an integration of a sensor element and an IC can be realized with the smallest possible space requirement. Several semiconductor chips, for example several thin chips, and thus preferably several functions can be integrated one above the other and / or next to one another on a carrier substrate, for example a carrier chip.

In the proposed method, conventional method techniques can be used and modified according to the invention. Overall, the process can be implemented very simply and basically using conventional process techniques. For example, the at least one through contact can be produced at the same time as a separation trench, which is already produced today with the chip film method described above. Furthermore, functional elements can be produced on the semiconductor chip and / or the carrier substrate using standard techniques as they are already used today, so that the proposed method can be implemented very cost-effectively overall.

Figure list

Exemplary embodiments of the invention are shown in the figures and explained in more detail in the description below.

• 1A bis 1H Verfahrensschritte eines Ausführungsbeispiels eines Verfahrens zur Herstellung eines Halbleiterbauelements;
• 2 ein Ausführungsbeispiel eines Drucksensors;
• 3 ein Ausführungsbeispiel eines Inertialsensors;
• 4 ein Ausführungsbeispiel eines z-Beschleunigungssensors; und
• 5 eine Verfahrensvariante mit einem CMOS-Prozess.

Show it:

• 1A until 1H Method steps of an exemplary embodiment of a method for producing a semiconductor component;
• 2 an embodiment of a pressure sensor;
• 3 an embodiment of an inertial sensor;
• 4th an embodiment of a z acceleration sensor; and
• 5 a process variant with a CMOS process.

Embodiments

In the 1A until 1H Method steps of an exemplary embodiment of a production method according to the invention for producing a semiconductor component are shown schematically.

In 1A a first method step is shown by way of example in which a semiconductor chip 110 on a starting substrate 112 is produced. This generation takes place here, for example, in a chip film process. The semiconductor chip 110 is designed as an epitaxial membrane, for example as a silicon membrane, which is located above a cavern 114 between the starting substrate 112 and the semiconductor chip 110 is trained. The semiconductor chip 110 , for example a silicon membrane, is supported by support points 116 held, which can be designed for example in the form of crystalline and / or porous silicon. Inside the semiconductor chip 110 one or more functional elements can be created by conventional methods 118 , for example functional layers 120 , integrated or on the surface of the semiconductor chip 110 be secluded. In this way, the semiconductor chip 110 for example comprise a layer stack.

Furthermore, the semiconductor chip comprises 110 , for example a layer stack of the semiconductor chip 110 , preferably at least one electrical contact 122 , for example a bond pad, which is preferably made of an insulating layer 124 , for example an oxide, is surrounded.

By means of what is known as a trench method, in the exemplary embodiment shown, as in FIG 1B shown trenches 126 made, for example, saw trenches. Furthermore, one or more through contacts are optional 128 produced, which in this embodiment as simple openings in the semiconductor chip 110 are designed. These vias 128 can for example be one of the starting substrate 112 groundbreaking front 130 of the semiconductor chip 110 with one of the starting substrate 112 assignable back 132 of the semiconductor chip 110 associate.

Finally, a dielectric layer is formed by means of a preferably conformal deposition process 134 on the semiconductor chip 110 upset. For example, this dielectric layer can in turn comprise an oxide layer, preferably silicon oxide. As a deposition method, known deposition methods come into consideration, for example, in particular TEOS ozone methods, SACVD layers, low temperature oxide methods or similar methods. This process also uses side walls 136 of the semiconductor chip 110 in the area of the trenches 126 and / or side walls 138 the vias 128 with the dielectric layer 134 coated. Furthermore, partial areas are also used in this exemplary embodiment 140 on the back side 132 in the area of the trenches 126 and / or the vias 128 with the dielectric layer 134 coated.

The dielectric layer is then created with a strongly anisotropic, directed oxide etching 134 on the front side 130 , i.e. the chip surface of the semiconductor chip 110 , thinned and the electrical contact 122 , for example the bond pad, opened without the side wall protection in the area of the side walls 136 , 138 is significantly thinned. One result of this process step is in 1C shown. Alternatively, the oxide etching and opening of the electrical contacts 122 can also be carried out with other techniques, for example with a spray paint technique. Various other techniques are known to those skilled in the semiconductor fabrication arts.

In an in 1D A through-hole filling material is then used 142 applied, preferably in a conformal deposition process. For example, this via filler material 142 Include germanium. For example, an LPCVD process can be used, that is to say a low-pressure CVD process. Due to the conformal deposition, the layer of via filler material follows 142 the contour of the semiconductor chip 110 so that next to the front 130 also the side walls 136 of the semiconductor chip 110 and optionally the side walls 138 the vias 128 are coated, as well as sub-areas 140 on the back side 132 of the semiconductor chip 110 .

In 1E is the in 1D with the letter A designated and framed by dashed lines part of the semiconductor chip 110 shown, which has a via 128 includes. This illustration illustrates the benefits of conformal deposition of the via filler material 142 visible. The sub-areas 140 , within which also the back 132 of the semiconductor chip 110 with through-hole filling material 142 is coated, are preferably not larger than the partial areas in which the back 132 with the dielectric layer 134 is coated (see for example 1B above).

In 1E typical dimensions are shown. So point the openings of the vias 128 typically a diameter D1 of less than 2 µm. The membrane of the semiconductor chips 110 typically has a thickness d ₂ of approximately 10 to 20 μm. These openings can be covered with an approximately 1 µm thick layer of the via filler material 142 , for example a germanium layer, are closed. In the cavern 114 , which preferably has a depth d ₃ of more than 3 μm, is at the rear 132 of the semiconductor chip 110 and through-hole filling material at the bottom of the cavern 142 deposited, for example less than 1 µm. As a result, a gap remains 144 between semiconductor chip 110 and cavern floor exist, with which the thickening of the semiconductor chips 110 remains possible. Preferably the via filler material 142 thus applied with a thickness d ₄ which is less than half the height d _{3 of} the cavern 114 amounts to.

In 1F an optional process step is shown in which the via filler material 142 is at least partially removed again, in particular from the front 132 of the semiconductor chip 110 . On the side walls 136 and 138 can the coating with the via filler material 142 are retained, as well as in the sub-areas 140 . At the same time, a structuring of the through-hole filling material can be achieved 142 be done, for example, to on the front 130 optional conductor tracks 146 and / or other structures, which are also wholly or partially part of the functional elements 118 can be to generate. In the example shown in 1F can thus, for example, the electrical contact 122 via the conductor track shown 146 and the via 128 from the back 132 be electrically contacted. For structuring the via filler material 142 In principle, techniques known from semiconductor manufacture can be used. For example, spray paints, standard lithography or standard etching processes can be used. Such processes are known in principle to the person skilled in the art.

Then the semiconductor chip 110 , as in 1G shown, from the starting substrate 112 be separated. The support points are 116 severed. This separation process, which is also referred to as “picking” or “pecking”, can be carried out, for example, by means of a vacuum pipette 148 as in 1G shown. However, other methods are also possible in principle, for example mechanical gripping methods. For cutting through the support points 116 can, for example, be a torsion about an axis perpendicular to the surface of the semiconductor chip 110 take place and / or another type of tilting. However, other separation techniques are also possible in principle.

In another, in 1H The illustrated process step is then the semiconductor chip 110 on a carrier substrate 150 upset. This carrier substrate 150 can for example comprise a printed circuit board and / or a lead frame and / or another type of carrier substrate 150 . The carrier substrate 150 comprises at least one bond bath 152 on its surface to be assembled 154 . Under bond pads 152 In this context, any electrical structures are to be understood, which can also include, for example, conductor tracks, frames, connection contacts or the like. In the in 1H illustrated embodiment include those on the back 132 of the semiconductor chip 110 with through-hole filling material 142 provided sub-areas 140 for example a frame 156 , which the edges of the semiconductor chip 110 preferably completely enclosing, such as via pads 158 , which with the via filler material 142 inside the vias 128 and about this, for example, with conductor tracks 146 on the front side 130 of the semiconductor chip 110 stay in contact. These correspond to the bond pads 142 Bondpad frame 160 or bond pad contacts 162 . These can also be functionally mixed, for example the coating with through-hole filling material 142 on the side walls 136 can take over electrical tasks.

The in 1H The assembly step shown is therefore the via filler material 142 on the back side 132 of the semiconductor chip 110 on the bond pads 152 of the carrier substrate 150 put on. Subsequently, semiconductor chip 110 and carrier substrate 150 preferably eutectically bonded to one another. For example, the bond pads 152 Include aluminum with the via filler material 142 of the semiconductor chip 110 , for example germanium, can form a eutectic alloy. For the bonding step, for example, a heat treatment step can be carried out in order to remove the eutectic alloy at least in a boundary region between the bond pads 152 and the via filler material 142 to build.

Eutectic bond connections with a connection width of preferably 1 μm are hermetically sealed, at least in theory. This allows between the semiconductor 110 and the carrier substrate 150 a hermetically sealed space 164 which can be advantageous for many applications. The possible small bond width also enables thin chips with germanium vias to be populated or bonded to save space on other carrier chips or other wafers. Accordingly, the carrier substrate 150 themselves have one or more functionalities and are fundamentally much more complex than in 1H shown. For example, this enables the generation of microelectromechanical components (MEMS). Important examples of semiconductor components 166 that can be generated in this way are micromechanical or microelectrical sensor elements, which are also referred to below with reference numbers 168 are designated. However, other applications are also possible in principle.

In the 2 until 4th are various examples of such semiconductor components 166 with sensor elements 168 shown and / or semiconductor elements 166 which sensor elements 168 include. In principle, these represent modifications of the in 1H semiconductor component shown 166 represent, so that for large parts of these exemplary embodiments on the description of these 1H as well as the process in the 1A until 1H can be referenced.

In 2 is an example of a pressure sensor 170 shown. With such pressure sensors 170 makes it possible to create a hermetically sealed space 164 particularly advantageous noticeable, since this gap 164 for example as a reference vacuum 172 can be used and / or can be filled with a gas of a predetermined or known pressure. Due to the fact that eutectic connections in particular are characterized by high hermiticity with a low conductor track density, a reference pressure between the carrier substrate can be used 150 , for example a carrier chip, and the semiconductor chip 110 , for example a thin chip. For this purpose, the carrier substrate 150 be designed, for example, as an integrated circuit and / or comprise such an integrated circuit, for example an ASIC. The carrier substrate 150 can for example be or comprise a semiconductor carrier substrate and / or a carrier substrate made of another material, for example made of a ceramic material or a glass. Other materials are also possible in principle, for example plastic materials. The semiconductor chip 110 itself can be used in particular as a pressure sensitive membrane 174 works. This pressure sensitive membrane 174 can also include resistors and / or other electrical components, for example resistors for piezoresistive readout. Alternatively or additionally, this pressure-sensitive membrane 174 also function entirely or partially as a movable electrode of a capacitor and / or comprise such a movable electrode, with on the carrier substrate 150 for example, as in 2 shown, a lower fixed electrode 176 can be provided. Alternatively, on a carrier substrate 150 , for example a pre-structured carrier substrate 150 , optionally with a cavity, a semiconductor chip 110 be bonded in the form of a thin-chip IC that doubles as a membrane 174 can serve. For functional principles of micromechanical pressure sensors, which can also be implemented within the scope of the present invention, for example, Robert Bosch GmbH: Sensors in motor vehicles, edition 2007 , Pages 128 until 130 to get expelled.

In 3 is another example of a semiconductor device 166 in the form of a sensor element 168 shown, which in this example is used as an inertial sensor 178 is designed. Inertial sensors are sensor elements 168 , which are used to measure acceleration forces and rotational forces, for example to measure linear acceleration forces. An inertial sensor 178 usually comprises at least 2, preferably 3 or more acceleration sensors 180 for different spatial directions or coordinates. In the example shown, the semiconductor chip corresponds to 110 again in large parts according to the embodiment 1H so that again reference can be made to the above description. In this case, however, it was inside the semiconductor chip 110 a micromechanical structure 182 in the form of a finger structure 184 generated. This finger structure 184 can, for example, be used at the same time as the in 1B illustrated making the trenches 126 , so the trench, are generated. These finger structures 184 , whereby also several such finger structures 184 , for example, can be provided for different spatial directions, thus in turn form a MEMS, which can be capacitively read out and / or driven, for example. For the structure and operation of such inertial sensors 178 can for example on Robert Bosch GmbH: Sensors in Motor Vehicles, 2007 edition , Pages 144 until 146 to get expelled. In principle, however, other structures and modes of operation are also possible again. The semiconductor chip 110 can for example with the eutectic bonding technique on a carrier substrate 150 be bonded with an ASIC and / or in the form of an ASIC. Capping can then optionally take place.

In 4th is another example of a semiconductor device 166 and sensor element 168 a so-called z-acceleration sensor 186 is shown. In this case, the carrier substrate comprises 150 a micromechanical structure 182 , which as a movable electrode 188 functions and in the representation in 4th is framed by dashed lines. Furthermore, the carrier substrate comprises 150 a lower fixed electrode 190 . The bonded semiconductor chip 110 , for example the thin chip, can be used in whole or in part as an upper fixed electrode 192 function and / or such an upper fixed electrode 192 include. Alternatively or additionally, the semiconductor chip 110 also simply as a cap for the movable electrode 188 be exploited. During operation of the z-acceleration sensor 168, a z-movement of the movable electrode 188 , which thus functions as a z-electrode, in a z-direction, that is, a connection direction between the carrier substrate 150 and the semiconductor chip 110 be evaluated, for example differentially. Robert Bosch GmbH: Sensors in Motor Vehicles, Edition 2007 , Pages 144 until 146 to get expelled. However, other measurement principles and / or controls are also possible in principle.

The ones in the 1A until 1H The process steps shown are only possible exemplary embodiments for implementing the method according to the invention. Numerous modifications in the design and in the procedure are possible within the scope of the present invention. So, as in 5 is shown, for example on the application of the insulating layer 124 can also be waived in whole or in part. A structure is shown which essentially corresponds to the illustration in FIG 1F corresponds, so that in large parts reference can be made to the description of this illustration. In contrast to the 1F however, a CMOS process is used. Such processes are known in principle to the person skilled in the art from semiconductor technology. In this case, isolation trenches or other types of isolation doping can be created through deep doping profiles 194 into the semiconductor chip 110 or areas of the semiconductor chip 110 be introduced. In this way, for example, without an insulating layer 124 and / or without dielectric layers 134 Via filler materials 142 on the semiconductor chip 110 applied and / or in the semiconductor chip 110 can be introduced without short-circuits with other components, for example functional elements 118 of the semiconductor chip 110 to risk. In this way, a short circuit in the bonding and circuit area can be avoided. In this case a dielectric layer is deposited 134 and / or an insulating layer 124 so not absolutely necessary.

The semiconductor components according to the invention 166 , in particular with the vias according to the invention, are of great importance for the further construction of thin chips, in particular chips that have been produced using the chip film method. With the proposed through-hole design, a simple and inexpensive technique is made possible.

Claims (8)

A method of manufacturing a semiconductor device (166) comprising the steps of: a) a semiconductor chip (110) is produced on an output substrate (112), the semiconductor chip (110) being connected to the output substrate (112) in at least one support point (116), the semiconductor chip (110) being one of the output substrate (112) has remote front side (130) and a rear side (132) facing the starting substrate (112), b) in at least one via step, at least one via filler material (142) is applied to the semiconductor chip (110), at least a partial area (140) of the rear side (132) being coated with the via filler material (142), c) the semiconductor chip (110) is separated from the starting substrate (112), and d) the semiconductor chip (110) is applied to at least one carrier substrate (150), the partial area (140) of the rear side (132) of the semiconductor chip (110) coated with the via filler material (142) having at least one bond pad (152) by means of a eutectic bonding process is connected on the carrier substrate (150). Procedure according to Claim 1 , wherein the via filling material (142) comprises at least one semiconductor material, in particular germanium. The method according to any one of the preceding claims, wherein the bond pad (152) comprises aluminum. Method according to one of the preceding claims, wherein in the via step at the same time at least one wall (138) of at least one via (128) and / or at least one side wall (136) of the semiconductor chip (110) are coated with the via filling material (142). Method according to one of the preceding claims, wherein in the via step on the rear side (132) at least one frame (156) is produced, in particular a closed frame (156), wherein after the application of the semiconductor chip (110) to the carrier substrate (150) within of the frame (156) a gap (164) is created, in particular a hermetically sealed gap (164). Method according to one of the preceding claims, wherein the semiconductor chip (110) comprises at least one of the following elements: an integrated circuit; a sensor structure; a micromechanical structure (182). Method according to one of the preceding claims, wherein a conformal deposition method is used in the via step, in particular a liquid phase deposition method and / or a CVD method. Method according to one of the preceding claims, wherein at least one insulating material (124, 134) is applied to the semiconductor chip (110) prior to the via step.

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