DE102009045693B4 - Micromechanical component for a Hall sensor device and method for producing a micromechanical component for a Hall sensor device - Google Patents

Abstract

A micromechanical device for a Hall sensor device comprising: - a semiconductor substrate (54); and - a Hall element formed on a semiconductor region (56) with power supply contacts (20a) and voltage contacts (22a) which are designed so that a current flow through the semiconductor region (56) can be applied by means of the power supply contacts (20a) and by means of the voltage contacts (22a ) a voltage information with respect to a voltage applied to the semiconductor region (56) Hall voltage can be tapped; wherein a cavity (52) is formed in the semiconductor substrate (54) and the semiconductor region (10, 56) is disposed at a peripheral region of the cavity (52), the semiconductor region (10, 56) passing over at least one of the cavities (52 ) at least partially spanning the holding element (58) is connected to the semiconductor substrate (54), and wherein the at least one holding element (58) at least one integrally with the semiconductor region (56) and the semiconductor substrate (54) formed holding web (58), characterized in that the at least one retaining web (58) comprises an area arranged above the cavern (52) and / or partially covering the cavern (52), which extends into a first partial area (58a) with a first central longitudinal axis (58c) and into a second partial area (58b) can be subdivided with a second center longitudinal axis (58d) which is inclined relative to the first central longitudinal axis (58c).

Description

The invention relates to a micromechanical component for a Hall sensor device. Furthermore, the invention relates to a production method for a micromechanical component for a Hall sensor device.

State of the art

Hall sensors for measuring magnetic fields, or for measuring a current intensity of a current flow via the induced magnetic field, are known from the prior art. The DE 199 43 128 A1 describes, for example, a Hall sensor arrangement with at least two Hall sensor elements. In this case, each of the at least two Hall sensor elements comprises an active semiconductor region and four contact electrodes arranged thereon. By means of two of the contact electrodes of a Hall sensor element, an operating current is passed through the associated active region. The two other contact electrodes of the Hall sensor element pick up the Hall voltage applied to the active semiconductor region. The use of at least two Hall sensor elements is intended to ensure that a voltage tap on a single active semiconductor region can distinguish between a Hall voltage induced by an external magnetic field and a non-hall-induced voltage.

From the Scriptures DE 44 42 852 A1 a Hall element is known, which is arranged on a carrier body over a cavity in a substrate. In this case, the carrier body is suspended by means of a membrane or a plurality of webs in the cavity. Above the membrane or the webs, an insulating layer is applied, via which a contacting of the Hall element takes place.

From the Scriptures DE 10 2006 059 091 A1 For example, a micro-optical reflective device is known which is applied to a circular membrane. To suspend the membrane spring elements can be provided in one embodiment, which absorb mechanical stresses.

From the Scriptures EP 0 342 274 B1 An arrangement for reducing piezo effects in a piezo-sensitive electrical component is known. For this purpose, the piezoelectric-electric component is accommodated in an insulated cell such that the cell is directed downwards and laterally in all directions through a gap 4 is surrounded. The space is partially open at the top by means of pressure equalization openings and partially closed by thin intermediate webs. The thin intermediate webs form a connection to the remaining semiconductor material.

Disclosure of the invention

The invention provides a micromechanical component for a Hall sensor device having the features of claim 1 and a manufacturing method for a micromechanical component for a Hall sensor device having the features of claim 8.

Due to the at least partial integration of the Hall element into a semiconductor region which is at least partially separated / decoupled from the semiconductor substrate (bulk material), a micromechanical stress suppression in the semiconductor region can be carried out in a simple manner to avoid the occurrence of non-magnetic field induced voltages (offset voltages). This can also be so designated that the semiconductor region is / is designed as an island which is at least partially separated / decoupled from the semiconductor substrate. The inventive (partial) separation / decoupling of the semiconductor region from the semiconductor substrate by means of the cavern makes the Hall element "free".

In the case of the micromechanical component, offset voltages which are due to asymmetries and / or a piezoelectric effect can be "micromechanically" filtered out. Even with a force acting on the micromechanical component and / or a temperature change thus hardly / no offset voltages occur in the semiconductor region. A pressure exerted on the semiconductor substrate via the structure and / or connection technology can not / hardly lead to an offset voltage in the semiconductor region. This ensures a micromechanical component for a Hall sensor device in which hardly or no offset voltages occur / arise in the semiconductor region with the Hall element due to the micromechanical stress decoupling. The present invention thus ensures avoidance / suppression of offset voltages in the semiconductor region with the Hall element.

This is advantageous over a compensation of offset voltages, since the use of at least one second Hall element for carrying out the compensation is not necessary. The micromechanical component for a Hall sensor device is thus comparatively simple and inexpensive to produce with comparatively small dimensions. This reduces the space requirement of the micromechanical component and thus increases the possible uses for the micromechanical component.

The micromechanical component can be implemented as a monolithically integrated component. At a Integration of the micromechanical component in a sensor device can be integrated in the sensor device in a simple manner, a power supply and / or an electrical evaluation circuit for the Hall voltage due to the small space requirement of the micromechanical device. In particular, the power supply and / or the electrical evaluation circuit can be integrated into the micromechanical component.

The micromechanical component can be easily mounted using a protective cap in a low-cost mold housing. Due to the at least partial decoupling of the semiconductor region with the Hall element from the semiconductor substrate, the use of an expensive protective housing for the micromechanical component is not necessary. At the same time, it is ensured that the micromechanical component can also be used in environments in which it is subjected to a comparatively high level of stress.

In addition, in the case of the micromechanical component, the known possibilities of electrical compensation of the offset voltages can also be used. By suppressing offset voltages, particularly in combination with a known compensation method, a particularly high accuracy, resolution or sensitivity can be achieved in determining a magnetic field strength or a current intensity by means of the micromechanical component.

The realizable high accuracy in the magnetic field measurement, or in the current measurement, a comparatively large dynamic range is guaranteed. The micromechanical component is therefore particularly suitable for the current measurement of small currents in an electrical conductor, such as an electric drive.

The sensitivity of a Hall sensor depends on the mobility of the charge carriers, the resolution limit and the measurement spreads due to offset voltages. By suppressing the occurrence of offset voltages in the semiconductor region, the sensitivity of the Hall sensor device can thus be increased.

The semiconductor substrate and / or the semiconductor region may comprise silicon, for example. It should be understood, however, that the micromechanical device and method of manufacture described herein are not limited to the use of silicon as the semiconductor material. The low Hall sensitivity of silicon and the expression of the piezoelectric effect in silicon can be compensated for by the present invention.

For the manufacturing method according to the invention, the known silicon semiconductor technologies can be used, which are used in particular in bipolar or CMOS manufacturing processes. This simplifies the production of the micromechanical component.

A sensor device with the micromechanical component can be used, for example, as a Hall sensor for measuring static magnetic fields. The sensor device can be used in particular for measuring the geomagnetic field (compass). In addition, the sensor device can be used as a rotational speed sensor or as a rotational angle sensor, for example in a motor vehicle. Furthermore, the sensor device with the micromechanical component can also be used as a sensor for current measurement.

Advantageous developments of the micromechanical component and the manufacturing method are described in the subclaims. The advantages of the features of the micromechanical component of the subclaims can also be realized by means of a corresponding manufacturing method.

The manufacturing method may in particular comprise at least one of the following method steps for forming a membrane which at least partially spans the cavity: forming a plurality of depressions on a first outer side of the semiconductor substrate near a cavity region; At least partial immersion of the semiconductor substrate in an electrically conductive etching solution; Electrically connecting one of the first outer opposing second outer side of the semiconductor substrate with a first voltage contact; Immersing a second voltage contact in the electrically conductive etching solution; Performing anodization, wherein the cavity region is etched porous; and performing a temperature treatment to form the cavern ( 52 ) in the cavity area and the membrane ( 50 ), which the cavern ( 52 ) at least partially spanned. Thus, the formation of the membrane which spans the cavern can be carried out in a simple manner.

Brief description of the drawings

Further features and advantages of the present invention will be explained below with reference to the figures. Show it:

1A and 1B a plan view and a cross section illustrating an embodiment of the micromechanical device;

2 a flowchart for illustrating a first embodiment of the manufacturing method; and

3A to 3E Cross sections through a semiconductor substrate for illustrating a second embodiment of the manufacturing method.

Embodiments of the invention

1A and 1B show a plan view and a cross section illustrating an embodiment of the micromechanical device. 1B shows a cross section along the line AA 'the 1A ,

The micromechanical component shown schematically has a semiconductor region 10 on, which by means of a cavern 12 from one the semiconductor area 10 at least partially surrounding semiconductor substrate 14 disconnected / decoupled. The semiconductor area 10 is at / in a peripheral area of the cavern 12 arranged. One can also do this as an arrangement of the semiconductor region 10 over the cavern 12 describe. The cavern 12 is preferably partially from the semiconductor region 10 covered.

For arrangement / positioning of the semiconductor region 10 over the cavern 12 the micromechanical component has an insulating layer as the holding element 16 on. The insulating layer 16 spans the cavern 12 at least partially, or the cavern 12 is from the insulating layer 16 partially covering. Over the insulating layer 16 is the semiconductor area 10 with the semiconductor substrate 14 connected. The semiconductor area 10 can, for example, via an at least partial covering of the semiconductor region 10 on the insulating layer 16 be attached. Alternatively, the insulating layer 16 also one of the caverns 12 facing surface of the semiconductor region 10 to contact. In both cases, a secure hold of the semiconductor region 10 over the cavern 12 by means of the insulating layer 16 guaranteed.

The semiconductor area 10 and / or the semiconductor substrate 14 comprise at least one semiconductor material. A suitable semiconductor material for the semiconductor sector 10 and / or the semiconductor substrate 14 is for example silicon. In this case, the semiconductor region 10 as monocrystalline silicon island over the cavern 12 be arranged. It should be noted, however, that the micromechanical component described here is not limited to the use of silicon as a semiconductor material. Instead of or in addition to silicon, the semiconductor region 10 and / or the semiconductor substrate 14 still comprise at least one further semiconductor material. In addition to the at least one semiconductor material, the semiconductor region 10 and / or the semiconductor substrate 14 also comprise at least one metal.

The cavern 12 may be formed so that one to the semiconductor region 10 aligned outer area 12a the cavern 12 forms a separation trench, which is an outer side 10a of the semiconductor region 10 at least partially framed. In addition, with a suitable design of the cavern 12 Ensuring that one of the outside 10a opposite inner side 10b of the semiconductor region 10 by means of the cavern 12 from the semiconductor substrate 14 is spaced. On the advantages of such a spacing / mechanical (partial) separation of the semiconductor region 10 from the semiconductor substrate 14 will be discussed in more detail below.

As an alternative or as a supplement to this, the cavern can 12 be formed so that one parallel to the outside 10a , the inside 10b or the maximum extension / area of the semiconductor substrate 14 aligned maximum internal cross section 12b the cavern 12 a scope 12c which is larger than a maximum extent aligned parallel thereto 10c of the semiconductor region 10 is. In particular, the surface area of the maximum inner cross section 12b by a factor of at least 4, preferably by a factor of at least 6, greater than the surface area of the outside 10a and / or the inside 10b be. Likewise, the scope 12c the maximum inner surface 12b by a factor of at least 2, in particular by a factor of at least 4, greater than the maximum extent 10c of the semiconductor region 10 be. This enhances the advantages of spacing / mechanical (part) isolation of the semiconductor region 10 from the semiconductor substrate 14 ,

The semiconductor area 10 can, for example, by means of the cavern 12 from the (residual) semiconductor substrate 14 be structured out. In the insulating layer 16 can etch openings 16a be formed, by means of which the cavern is etchable in a simple manner. You can see the etching holes 16a also called perforations. On an advantageous approach to form the cavern 12 is used in the description of 2 still received.

The etching holes 16a can be at least partially filled / covered with a material. Preferably, the etching openings 16a by means of a sealing layer 18 completely covered. The sealing layer 18 For example, it may be an oxide layer. In this way is an intrusion of particles into the cavern 12 over the etch holes 16a preventable. Hermetically sealing the etch holes 16a is not necessary. The sealing layer 18 can the arrangement of the semiconductor region 10 in a desired position above the cavern 12 additionally stabilize.

This in 1A and 1B shown micromechanical component can also be used as Pirani probe be designated (only resistance measurement without Hall contacts). The micromechanical component has an on the outside 10a of the semiconductor region 10 arranged Hall element with power supply contacts 20a and voltage contacts 22a on. For example, by means of the two power supply contacts 20a the lines 20 a current flow through the semiconductor region 10 applied. The voltage contacts 22a the lines 22 may be arranged / formed such that voltage information with respect to one at the semiconductor region 10 applied Hall voltage, which is inducible by the applied current flow and an external magnetic field, via the contacts 22a can be tapped. Preferably, the semiconductor region 10 a doping of a first conductivity type, wherein the first conductivity type of a second conductivity type of a doping of the semiconductor substrate 12 is opposite.

Preferably, the voltage contacts 22a the lines 22 diagonally opposite to the power supply contacts 20a the lines 20 arranged. The wires 20 and or 22 may be formed of a metal and / or a doped semiconductor material, such as polysilicon. Optionally, an integrated circuit can be attached to the micromechanical component 24 be formed, which is designed such that by means of the integrated circuit 24 the current flow through the semiconductor region 10 controllable and / or the voltage information with respect to the semiconductor region 10 applied Hall voltage can be determined. The wires 20 and or 22 can spread over a section of the cavern 12 from the integrated circuit 24 to the semiconductor region 10 extend. The wires 20 and 22 may be the arrangement of the semiconductor region 10 in the preferred position over the cavity 12 additionally stabilize. As an alternative to the integrated circuit 24 can also be arranged externally a suitably trained control, regulation and / or evaluation.

Due to the at least partial separation / decoupling of the semiconductor region 10 from the semiconductor substrate 14 is the transmission of mechanical stresses from the semiconductor substrate 14 in the semiconductor field 10 diminishable / unterbindbar. Such mechanical stresses can be applied, for example, to the semiconductor substrate 14 applied pressure, in particular by the construction technique, and / or a temperature change in the semiconductor substrate 14 to be triggered. By weakening / inhibiting the transmission of such mechanical stresses, the occurrence of a piezoelectric effect in which a volume change results in a voltage change is in the semiconductor region 10 reliably prevented. The at least partial separation / decoupling of the semiconductor region 10 from the semiconductor substrate 14 by means of the cavern 12 thus causes a mechanical stress compensation to avoid non-hall-induced interference voltages (offset voltages). In addition, in this way it is ensured that asymmetries do not lead to an occurrence of voltages in the semiconductor region 10 to lead.

This is the occurrence of non-hall-induced interference voltages in the semiconductor region 10 preventable. It can thus be ensured that no non-hall-induced interference voltages are erroneously detected as Hall voltage. An evaluation of the voltage information with respect to the semiconductor region 10 applied Hall voltage therefore leads to more reliable results / information.

Since the occurrence of non-hall-induced interference voltages in the semiconductor region 10 by means of the cavern 12 is reliably reducible / can be prevented, it is not necessary in the illustrated micromechanical component to perform a compensation of possible interference voltages by evaluating / comparing the tapped at the illustrated Hall element voltage information with a voltage determined at a further Hall element voltage information. This eliminates the need for an additional Hall element in the micromechanical component. This reduces the costs for the production of the micromechanical component. In addition, in this way the size of the micromechanical component, and thus the space required, can be reduced. A further advantage of the micromechanical component is that a complex evaluation method of at least two voltage information tapped off at at least two Hall elements is not necessary. The micromechanical component thus ensures the use of a cost-effective and little space consuming sensor and evaluation, which therefore easy as an integrated circuit 14 is executable.

2 shows a flowchart for illustrating a first embodiment of the manufacturing method.

In an optional method step S1, a semiconductor region of a substrate may be doped with a doping of a first conductivity type, which is preferred for use of the semiconductor region as a sensitive region of a Hall element. Preferably, a residual region of the substrate, which is referred to below as a semiconductor substrate, can be doped with a doping of an opposite second conductivity type.

In an optional method step S2, an integrated circuit separate from the Semiconductor region can be arranged on the semiconductor substrate. The integrated circuit can be designed, for example, as an evaluation circuit. By integrating the integrated circuit into the semiconductor substrate, the size of the subsequently formed micromechanical component for a Hall sensor device can be reduced. With regard to the design of the integrated circuit, reference is made to the description above.

In a method step S3, an insulating layer is formed which at least partially covers an upper side of the semiconductor substrate on which the semiconductor region is arranged. If the semiconductor substrate is made of silicon, the formation of the insulating layer can take place, for example, via an oxidation. However, the manufacturing method described here is not limited to the use of a silicon semiconductor substrate. Also, instead of silicon oxide, other insulating materials may be used to form the insulating layer.

In the method step S3, etching openings (perforations) are preferably formed in the insulating layer. Preferably, the etching openings have a diameter between 0.5 to 3 microns. The insulating layer can thus be used as an etching mask for the subsequent etching steps. This multifunctionality of the insulating layer simplifies the manufacturing method described below. Advantageously, the etching openings may be formed in the insulating layer so that they lie on at least one line framing the semiconductor region.

In a subsequent anisotropic etching process (method step S4), trenches are formed in the semiconductor substrate. The positions and dimensions of these trenches are predetermined by the etching openings in the insulating layer. Preferably, the trenches lie on at least one line framing the semiconductor region.

Optionally, the side walls of the trenches formed in method step S4 can be covered with an etching protection layer in a method step S5. The covering of the side walls with the etching protection layer preferably takes place in such a way that the bottom surfaces of the trenches remain uncovered by the etching protection layer.

In a subsequent method step S6, a cavern is formed in the semiconductor substrate, wherein the semiconductor region is arranged on / in a peripheral region of the cavern. This is preferably done so that the cavern is at least partially covered by the semiconductor region. The method step S6 for forming the cavern / arranging the semiconductor region above the cavern is an isotropic etching step in the method described here. In this case, the semiconductor region is connected to the semiconductor substrate via the insulating layer acting as a holding element, which partially covers the cavern. This can also be described in such a way that the semiconductor region is freed by means of the cavern in such a way that the semiconductor region formed as an island is only supported by the insulating layer above the cavern.

If the sidewalls of the trenches are covered with the etching protection layer in method step S5, an etching material which does not etch / hardly etch the sidewalls is preferably used for method step S6.

In an optional method step S7 following the isotropic etching step (method step S6), the etching openings in the insulating layer can be at least partially closed. The applied sealing layer may comprise, for example, an oxide which is deposited via a chemical vapor deposition method. In this way, the penetration of foreign particles into the cavern can be prevented.

In step S8, a Hall element is formed on the semiconductor region. In this case, the power supply contacts of the Hall element are designed such that during operation of the Hall element, a current flow through the semiconductor region is applied by means of the power supply contacts. Likewise, the voltage contacts of the Hall element are designed such that during operation of the Hall element voltage information is tapped with respect to a voltage applied to the semiconductor region Hall voltage means of the voltage contacts.

Before the power supply contacts and / or the voltage contacts are formed, contact openings may be etched through the insulating layer and / or the sealing layer, for example. Subsequently, a conductive material, for example a metal and / or a doped semi-material, for forming the power supply contacts and / or the voltage contacts of the Hall element are deposited. Via a subsequent structuring of the conductive material, various embodiments of the power supply contacts and the voltage contacts can be realized.

In an optional method step S9, the micromechanical component produced can be surrounded by a protective structure. The process steps carried out in this case are described in more detail below.

The micromechanical produced by means of the method steps S1 to S8 described Component ensures the advantages already described above. However, the feasibility of the manufacturing process is not limited to that in 2 limited time sequence shown. In an alternative embodiment of the production method, for example, the at least one Hall element can already be formed before the deposition of the insulating layer. The method step S7 is executed in this case before the method step S3.

By means of the manufacturing process described below, for example, based on the 1A and 1B reproduced micromechanical component for a Hall sensor device produced. It should be noted, however, that by means of the manufacturing method, a micromechanical component with at least two Hall elements can be produced. The at least two Hall elements can, for example, be aligned with one another at an angle of inclination not equal to zero, preferably by 90 °. Likewise, the at least two Hall elements can be arranged uniformly on a periphery of a circular Hall plate, wherein in the process step S8 additionally an electronic switch is formed such that the at least two Hall elements are circularly switchable.

3A to 3E show cross-sections through a semiconductor substrate for illustrating a second embodiment of the manufacturing method.

In the manufacturing process, a preferably monocrystalline membrane 50 formed, which is a cavity 52 in a semiconductor substrate 54 spans. Preferably, to form the membrane 50 a technique known as lattice technology. In the following, method steps for carrying out the grid technology for simultaneous formation of the membrane will be described 50 and the cavity 52 described:
In the grid technology, a plurality of recesses are formed on a first outside of the semiconductor substrate 54 near a cavity area, in which the later cavity 52 should be formed formed. This may be said to etch a grid of pits above the cavity area.

Subsequently, the semiconductor substrate 54 in an electrically conductive etching solution, such as hydrofluoric acid immersed. The semiconductor substrate 54 is electrically connected on one of the first outer side facing the second outer side with a first voltage contact. A second voltage contact is immersed in the electrically conductive etching solution at a close distance to the depressions in the first outer side.

In the subsequent anodization form within the semiconductor substrate 54 Field lines, which extend from the inner regions (peaks) of the recesses in the semiconductor substrate. In this way, the semiconductor substrate 54 be selectively etched porous in the cavity area, so that within the cavity area several adjacent porous areas arise. A subsequent temperature treatment causes the formation of the membrane 50 , which is the cavity that occurs in the previously porous areas 52 spans.

The method described in the above paragraphs for forming the membrane 50 For example, using a semiconductor substrate 54 made of silicon. A membrane formed in this way 50 may be referred to as the APSM ^™ membrane (Advanced Porous Silicon Membrane).

It should be noted that the manufacturing method described below is not based on the formation of the membrane 50 is limited by the grid technology. As an alternative to the membrane formed by the lattice technology 50 may also include an epitaxial layer over one in the semiconductor substrate 54 etched cavity 52 be used.

Optionally, an integrated circuit 24 in the semiconductor substrate 54 be formed. The membrane 50 and the integrated circuit 24 can at least partially with an insulating layer 16 be covered. In the insulating layer 16 can etch openings 16a for an etching step described in more detail below.

After that, be on an outside 50a the membrane 50 above the cavity 52 formed the components of a Hall element. In forming the Hall element become power supply contacts 20a and voltage contacts 22a educated. This is done, for example, by depositing a conductive material on the insulating layer 16 and structuring lines 20 and 22 from the conductive material. 3A shows the semiconductor substrate after forming the leads 20 and 22 ,

As in the 3B and 3C is shown below, a semiconductor region 56 the membrane 50 so on the semiconductor substrate 54 with the cavern 52 arranged that the cavern 52 partly from the semiconductor region 56 is covered and the semiconductor area 56 via at least one of the membrane 50 Outlined retaining bridge 58 with the semiconductor substrate 54 is connected. The at least one jetty 58 can be integral with the semiconductor region 56 and / or the semiconductor substrate 54 be formed. For example, at least one is at least through the membrane 50 through and the semiconductor region 56 at least partially framing separation trench 60 etched.

The location of the at least one separation trench 60 is over the etch holes 16a in the insulating layer 16 fixable.

The island-shaped semiconductor region 56 points after the etching of the separation trench 60 a suspension, which only areas of the insulating layer, the at least one of the membrane 50 Outlined retaining bridge 58 and the areas of the wires 20 and 22 includes.

If an elastic suspension of the island-shaped semiconductor region 56 is preferred, the holding webs 58 by a suitably structured shape as thin resilient retaining webs 58 be formed. Also the lines 20 and 22 can be made elastic. In addition, the number of retaining bars 58 equal to the number of lines spanning the cavern 20 and 22 be. Thus, the elasticity of a holding web 58 only by a single line running on it 20 or 22 impaired.

In particular, the lines can 20 and 22 and / or the at least one retaining bridge 58 be formed so that one above the cavern 52 arranged and / or the cavern 52 partially covering area of a pipe 20 or 22 or a jetty 58 into a first (outer) subarea 20b . 22b or 58a with a first central longitudinal axis 58c and into a second (inner) subarea 20c . 22c or 58b with one to the first center longitudinal axis 58c inclined aligned second central longitudinal axis 58d is divisible (see 3C ). Preferably, the second central longitudinal axis runs 58d perpendicular to the first central longitudinal axis 58c , By such a design at least one line 20 or 22 and / or the at least one retaining web 58 is a transmission of mechanical stresses from the semiconductor substrate 54 to the semiconductor region via the line 20 or 22 and / or over the at least one retaining bar 58 additionally preventable.

In an optional process step, which by means of 3D is shown, the holding webs 58 be removed. This is done, for example, via an over-etching step. In this way, the decoupling of the semiconductor region can be 56 increase. In this case, the island-shaped semiconductor region is 56 after removing the retaining webs 58 only over the insulating layer 16 and the wires 20 and 22 connected to the semiconductor substrate. The optional overetching can be carried out, for example, by a wet-chemical process step or by means of a CIF3 etching.

In a further optional method step, a sealing layer 62 be separated, by means of which the penetration of foreign particles into the cavern 52 is preventable (see 3E ). As an alternative or as a supplement to the sealing layer 62 can a protective cap 64 via a fastener 66 be attached to the micromechanical component such that the protective cap 64 the semiconductor region 56 spanned with the Hall element formed thereon. The fastener 66 may be, for example, seal glass or an adhesive. The protective cap 64 can be made of silicon or a low-cost plastic. Alternative can as a protective cap 64 Also, an insert over a mold step are applied. It should be noted that a hermetic sealing of the semiconductor region 56 with the Hall element formed thereon by means of the protective cap 64 is not necessary. For this reason, attaching the protective cap 64 be an easy-to-implement gluing.

For contacting the micromechanical component, one end of a bonding wire 68 with the integrated circuit 24 get connected. By means of an adhesive 70 can the micromechanical component on a leadframe 72 be stuck. A second end of the bond wire 68 can with the leadframe 72 get connected. In this way, there is an electrical contact between the leadframe 72 and the integrated circuit 24 easily realizable.

For an additional protective covering, the micromechanical component can be provided with a molding compound 74 to be poured over. The protective cap 64 holds the applied molding compound 74 from the semiconductor region 56 remote with the Hall element formed thereon. Due to the at least partial mechanical stress decoupling of the semiconductor region 56 from the semiconductor substrate 54 is the formation of a cost-effective Moldgehäuses means of molding compound 74 sufficient. Due to the micromechanical stress decoupling it is ensured even with such a cost-effective protective housing that no assembly stress reaches the semiconductor region with the Hall element.

When used for a sensor device, the micromechanical component formed by means of the production method ensures the advantages already described above. In a development, however, a micromechanical component with more than one Hall element can also be formed by means of the production method.

Claims (8)

Micromechanical component for a Hall sensor device with: A semiconductor substrate ( 54 ); and - one on a semiconductor region ( 56 ) formed Hall element with power supply contacts ( 20a ) and voltage contacts ( 22a ), which are designed such that by means of the power supply contacts ( 20a ) a current flow through the semiconductor region ( 56 ) can be applied and by means of the voltage contacts ( 22a ) a voltage information with respect to one of the semiconductor region ( 56 ) adjacent Hall voltage can be tapped; wherein in the semiconductor substrate ( 54 ) a cavern ( 52 ) is formed and the semiconductor region ( 10 . 56 ) at / in a peripheral area of the cavern ( 52 ), wherein the semiconductor region ( 10 . 56 ) over at least one cavern ( 52 ) at least partially spanning retaining element ( 58 ) with the semiconductor substrate ( 54 ), and wherein the at least one retaining element ( 58 ) at least one integral with the semiconductor region ( 56 ) and the semiconductor substrate ( 54 ) formed retaining bridge ( 58 ), characterized in that the at least one retaining web ( 58 ) one above the cavern ( 52 ) and / or the cavern ( 52 ) partially covering area, which in a first portion ( 58a ) with a first central longitudinal axis ( 58c ) and into a second subarea ( 58b ) with one to the first center longitudinal axis ( 58c ) inclined aligned second central longitudinal axis ( 58d ) is divisible. Micromechanical component according to claim 1, wherein the cavern ( 52 ) one to the semiconductor region ( 56 ) aligned outer area ( 12a ), which is one of the semiconductor substrate ( 54 ) directed outside ( 10a ) of the semiconductor region ( 56 ) at least partially framed. Micromechanical component according to claim 1 or 2, wherein one of the outside ( 10a ) inwardly directed ( 10b ) of the semiconductor region ( 56 ) by means of the cavern ( 52 ) of the semiconductor substrate ( 54 ) is spaced. Micromechanical component according to claim 1, wherein the second central longitudinal axis ( 58d ) perpendicular to the first central longitudinal axis ( 58c ) is aligned. Hall sensor device with a micromechanical component according to one of the preceding claims. Manufacturing method for a micromechanical component for a Hall sensor device comprising the steps: - forming a Hall element with power supply contacts ( 20a ) and voltage contacts ( 22a ) on a semiconductor region ( 56 ), whereby the power supply contacts ( 20a ) and the voltage contacts ( 22a ) are designed such that during operation of the Hall element by means of the power supply contacts ( 20a ) a current flow through the semiconductor region ( 56 ) and by means of the voltage contacts ( 22a ) a voltage information with respect to one of the semiconductor region ( 56 ) applied Hall voltage is tapped; Arranging the semiconductor region ( 56 ) on / in a peripheral region of a semiconductor substrate (in 54 ) cavern ( 52 ), wherein the semiconductor region ( 56 ) over at least one cavern ( 52 ) at least partially spanning retaining element ( 58 ) with the semiconductor substrate ( 54 ), wherein at least one retaining element ( 58 ) as a holding bridge ( 58 ) integral with the semiconductor region ( 56 ) and the semiconductor substrate ( 54 ) is formed, characterized in that the at least one retaining web ( 58 ) one above the cavern ( 52 ) and / or the cavern ( 52 ) partially covering area, which in a first portion ( 58a ) with a first central longitudinal axis ( 58c ) and into a second subarea ( 58b ) with one to the first center longitudinal axis ( 58c ) inclined aligned second central longitudinal axis ( 58d ) is divided. The manufacturing method according to claim 6, wherein for arranging the semiconductor region ( 10 ) on / in the peripheral area of the cavern ( 12 ) the cavern ( 12 ) is etched so that at least the semiconductor region ( 10 ) from the semiconductor substrate ( 14 ) is structured out (S4, S6). The manufacturing method according to claim 6, wherein for arranging the semiconductor region ( 56 ) on / in the peripheral area of the cavern ( 52 ) the semiconductor area ( 56 ) from a cavern ( 52 ) at least partially spanning membrane ( 50 ) is structured out.

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