DE102008046188B4 - A chip printed circuit board assembly and method of manufacturing a chip printed circuit board assembly - Google Patents

A chip printed circuit board assembly and method of manufacturing a chip printed circuit board assembly Download PDF

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Publication number
DE102008046188B4
DE102008046188B4 DE102008046188A DE102008046188A DE102008046188B4 DE 102008046188 B4 DE102008046188 B4 DE 102008046188B4 DE 102008046188 A DE102008046188 A DE 102008046188A DE 102008046188 A DE102008046188 A DE 102008046188A DE 102008046188 B4 DE102008046188 B4 DE 102008046188B4
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Prior art keywords
circuit board
chip
intermediate layer
passivation layer
semiconductor chip
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DE102008046188A
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German (de)
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DE102008046188A1 (en
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Holger Huebner
Gerd Jungmann
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Polaris Innovations Ltd
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Qimonda AG
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    • H05K2203/049—Wire bonding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

Chip-Leiterplatten-Anordnung, aufweisend:
– eine Leiterplatte (19) mit einer Kontaktfläche (18);
– einen Halbleiterchip (11) mit einem elektrischen Anschlusskontakt (12) und einer Passivierungsschicht (13), die neben dem Anschlusskontakt (12) angeordnet ist;
– eine Drahtbondverbindung (15) mit Bonddraht (16) auf dem Anschlusskontakt (12) des Halbleiterchips, wobei
– der Bonddraht (16) auf der Passivierungsschicht (13) des Halbleiterchips (11) endet, wobei
die Passivierungsschicht (13) zum Zeitpunkt des Drahtbondens eine haftfähige Oberfläche aufweist, und wobei
– die Kontaktfläche (18) der Leiterplatte (19) gegenüber dem Ende des Bonddrahtes (16) angeordnet ist und
– der Bonddraht (16) mit der Kontaktfläche (18) der Leiterplatte (19) über ein elektrisch leitfähiges Material (17) verbunden ist.Chip circuit board assembly comprising:
- A printed circuit board (19) having a contact surface (18);
- A semiconductor chip (11) having an electrical terminal contact (12) and a passivation layer (13), which is arranged adjacent to the terminal contact (12);
- A wire bond connection (15) with bonding wire (16) on the terminal contact (12) of the semiconductor chip, wherein
- The bonding wire (16) on the passivation layer (13) of the semiconductor chip (11) ends, wherein
the passivation layer (13) has an adhesive surface at the time of wire bonding, and wherein
- The contact surface (18) of the printed circuit board (19) opposite the end of the bonding wire (16) is arranged and
- The bonding wire (16) with the contact surface (18) of the printed circuit board (19) via an electrically conductive material (17) is connected.

Figure 00000001
Figure 00000001

Description

Die Erfindung betrifft eine Chip-Leiterplatten-Anordnung und ein Verfahren zum Herstellen einer Chip-Leiterplatten-Anordnung.The invention relates to a chip printed circuit board assembly and a method for producing a chip printed circuit board assembly.

Die Entwicklung von elektronischen Bauelementen und deren Verbindung mit einem übergeordneten System wie einer Leiterplatte ist geprägt von den Anforderungen an ständig wachsende, höhere Leistungsfähigkeit der elektronischen Bauelemente bei gleichzeitiger Erfordernis an weitere Miniaturisierung und Kostenersparnis.The development of electronic components and their connection to a higher-level system such as a printed circuit board is characterized by the requirements of ever-increasing, higher performance of the electronic components while requiring further miniaturization and cost savings.

Eine Möglichkeit dazu ist es, Chips ohne eigenes Gehäuse direkt auf einer Leiterplatte anzuordnen und direkt miteinander zu verbinden.One possibility for this is to arrange chips without their own housing directly on a printed circuit board and connect them directly to one another.

Das Problem hierbei ist der Ausgleich der Strukturbreiten zwischen den Anschlusskontakten des Chips und den Kontaktflächen der Leiterplatte.The problem here is the compensation of the structure widths between the terminal contacts of the chip and the contact surfaces of the circuit board.

Übliche Strukturbreiten der Anschlusskontakte von Chips liegen zwischen 60 und 120 μm mit fallender Tendenz bei Weiterentwicklung der Fertigungstechnologie. Hingegen liegen die kleinsten Strukturbreiten auf Leiterplatten, die mit vertretbarem Aufwand im Volumen gefertigt werden können bei 150–200 μm.Typical structure widths of the connection contacts of chips are between 60 and 120 μm with a decreasing trend with further development of the manufacturing technology. By contrast, the smallest structural widths on printed circuit boards, which can be manufactured with reasonable effort in volume at 150-200 microns.

Um den Unterschied zwischen den Strukturbreiten auszugleichen, wird im Stand der Technik auf dem Chip eine Umverdrahtungsebene hinzugefügt.To compensate for the difference between the feature widths, a redistribution layer is added on the chip in the prior art.

Diese erhöht die Kosten der Montage und kann außerdem weitere Nachteile, wie ein Durchbiegen des Chips bei Temperaturwechsel, zur Folge haben.This increases the cost of assembly and may also have other disadvantages, such as sagging of the chip as the temperature changes.

Die Erfindung stellt eine Chip-Leiterplatten-Anordnung und ein Verfahren zur Herstellung einer Chip-Leiterplatten-Anordnung bereit, die diesen Anforderungen gerecht werden.The invention provides a chip printed circuit board assembly and a method of manufacturing a chip printed circuit board assembly that meets these requirements.

In der Patentschrift US 6 211 461 B1 wird ein „chip size package” und Methoden zur Herstellung beschrieben, die eine Aussparung im oberen Teil eines Halbleiterchips aufweisen und wobei Anschlusskontakte in der unteren Mitte der Aussparung gebildet werden.In the patent US 6 211 461 B1 For example, a "chip size package" and methods of fabrication are described which have a recess in the upper part of a semiconductor chip and wherein connection contacts are formed in the lower center of the recess.

Dabei ist das untere Ende eines Metaldrahtes mit einem Anschlusskontakt verbunden und die Aussparung ist mit einer Epoxymasse gefüllt, wobei ein oberer Teil des Metalldrahtes einen Buckel bildet und die Epoxymasse überragt. Dieser Buckel und ist mit einer Lotkugel verbunden.In this case, the lower end of a metal wire is connected to a terminal contact and the recess is filled with an epoxy compound, wherein an upper part of the metal wire forms a projection and projects beyond the epoxy mass. This hump and is connected to a solder ball.

Die Patentschrift US 6 972 496 B2 beschreibt ein „chip-scaled package” und eine Methode zur Herstellung eines Halbleiterbausteins mit einem aufgesetzten Anschlusskontakt, wobei auf dem Halbleiterbaustein eine ersten Isolationsschicht aufgebracht ist und mit einem geöffneten Teil versehen ist, der den Anschlusskontakt offenlegt. Dabei bedeckt ein Ende eines Metalldrahts den geöffneten Teil und ist elektrisch mit dem Halbleiteranschlusskontakt verbunden. Eine zweiten Isolationsschicht ist über der ersten Isolationsschicht aufgebracht und bedeckt auch den offenen Teil der ersten Isolationsschicht legt aber das andere Endes des Metalldrahtes offen, wobei eine leitfähige Kugel am anderen Ende des bloßliegenden Metalldrahtes gebildet wird und ein Substrat auf dem der Halbleiterbaustein mittels der leitfähigen Kugel montiert wird.The patent US Pat. No. 6,972,496 B2 describes a "chip-scaled package" and a method for producing a semiconductor device with an attached terminal contact, wherein on the semiconductor device, a first insulating layer is applied and is provided with an open part, which exposes the terminal contact. In this case, one end of a metal wire covers the opened part and is electrically connected to the semiconductor terminal contact. A second insulating layer is deposited over the first insulating layer and also covers the open part of the first insulating layer but exposes the other end of the metal wire, forming a conductive ball at the other end of the bare metal wire and a substrate on top of the semiconductor device by means of the conductive ball is mounted.

Die erfindungsgemäße Lösung ist besonders vorteilhaft, da die Verbindung zwischen Halbleiterchip und Leiterplatte keine weitere Ebene (Umverdrahtung, Leadframe, Substrat) benötigt, sondern direkt erfolgt. Die Bonddrähte sind flexibel und gleichen Verschiebungen aus, die durch verschiedene thermische Ausdehnungskoeffizienten von Halbleiterchip und Leiterplatte auftreten, was die Zuverlässigkeit dieser Chip-Leiterplatten-Anordnung erhöht.The solution according to the invention is particularly advantageous since the connection between the semiconductor chip and the printed circuit board requires no further plane (rewiring, leadframe, substrate), but takes place directly. The bonding wires are flexible and compensate for shifts that occur due to different thermal expansion coefficients of the semiconductor chip and printed circuit board, which increases the reliability of this chip-printed circuit board assembly.

Nachfolgend werden Ausführungsbeispiele gemäß der Erfindung unter Bezugnahme auf die beigefügte Zeichnung näher erläutert.Hereinafter, embodiments according to the invention will be explained in more detail with reference to the accompanying drawings.

1 zeigt im Querschnitt die schematische Darstellung einer Ausführungsform der erfindungsgemäßen Chip-Leiterplatten-Anordnung; 1 shows in cross section the schematic representation of an embodiment of the chip circuit board assembly according to the invention;

2 zeigt in der Draufsicht eine schematische Darstellung einer Ausführungsform der Chip-Leiterplatten-Anordnung für Chips mit einfacher Anschlusskontakt-Reihe; 2 shows in plan view a schematic representation of an embodiment of the chip-printed circuit board arrangement for chips with simple terminal contact row;

3 zeigt in der Draufsicht eine schematische Darstellung einer Ausführungsform der Chip-Leiterplatten-Anordnung für Chips mit einer doppelten Anschlusskontakt-Reihe. 3 shows in plan view a schematic representation of an embodiment of the chip-printed circuit board arrangement for chips with a double terminal contact row.

1 zeigt den Aufbau einer Chip-Leiterplatten-Anordnung mit einem Halbleiterchip 11, der auf einer Seite elektrische Anschlusskontakte 12 aufweist. Die Anschlusskontakte 12 sind von einer Passivierungsschicht 13 umgeben, die den Halbleiterchip vor mechanischen und Umwelteinflüssen schützt. Auf dem Anschlusskontakt 12 ist ein Drahtbondanschluss 15 angebracht, von dem ein Bonddraht 16 wegführt. 1 shows the structure of a chip-printed circuit board assembly with a semiconductor chip 11 , on one side electrical connection contacts 12 having. The connection contacts 12 are of a passivation layer 13 surrounded, which protects the semiconductor chip from mechanical and environmental influences. On the connection contact 12 is a wire bond connection 15 attached, of which a bonding wire 16 leads away.

Auf der Passivierungsschicht 13 ist eine Zwischenschicht 14 angeordnet. Diese Schicht hat die Aufgabe, das Aufsetzen des Bondwerkzeuges zu dämpfen und das freie Ende des Bonddrahtes 16 mittels Haftkraft auf der Zwischenschicht 14 zu halten.On the passivation layer 13 is an intermediate layer 14 arranged. This layer has the task to dampen the placement of the bonding tool and the free end of the bonding wire 16 by means of adhesive force on the intermediate layer 14 to keep.

Wenn die Passivierungsschicht 13 so gestaltet ist, dass sie beide Aufgaben übernehmen kann, kann die Zwischenschicht 14 entfallen. If the passivation layer 13 is designed so that they can take on both tasks, the intermediate layer 14 omitted.

Die Zwischenschicht 14 kann wie die Passivierungsschicht 13 aus einer fotolithografisch strukturierten Schicht bestehen, die auf die Halbleiterchips 11 aufgebracht wird. Sie kann alternativ aus einem einseitig oder zweiseitig haftfähigen Klebeband bestehen, welches abschnittsweise im Bereich des Bonddrahtes 16 auf die Passivierungsschicht 13 aufgebracht wird.The intermediate layer 14 can be like the passivation layer 13 consist of a photolithographically structured layer on the semiconductor chips 11 is applied. Alternatively, it can consist of a single-sided or double-sided adhesive tape, which in sections in the region of the bonding wire 16 on the passivation layer 13 is applied.

Es ist auch möglich die Eigenschaften Dämpfung und Haftfähigkeit auf zwei Materialien zu verteilen: Die Dämpfung übernimmt die Passivierungsschicht 13 und die Haftfähigkeit übernimmt die Zwischenschicht 14, oder die Dämpfung übernimmt die Passivierungsschicht 13 und die Haftung übernimmt ein im Bereich des Bonddrahtes 16 aufgetropftes oder aufgedrucktes Klebematerial. Eine dritte Variante ist, die Dämpfung mit der Zwischenschicht 14 zu gewährleisten und die Haftung übernimmt ein im Bereich des Bonddrahtes 16 aufgetropftes oder aufgedrucktes Klebematerial.It is also possible to distribute the properties damping and adhesion to two materials: the damping takes over the passivation layer 13 and the adhesion takes over the intermediate layer 14 , or the damping takes over the passivation layer 13 and the adhesion takes over in the area of the bonding wire 16 dripped or printed adhesive material. A third variant is the damping with the intermediate layer 14 to ensure and the liability takes over in the field of bonding wire 16 dripped or printed adhesive material.

Mit dem freien Ende des Bonddrahtes 16 ist ein beliebiger Teil des Bonddrahtes 16 außerhalb des Anschlusskontaktes 12 gemeint.With the free end of the bonding wire 16 is any part of the bonding wire 16 outside the connection contact 12 meant.

Gegenüber dem freien Ende des Bonddrahtes 16 befindet sich die Kontaktfläche 18 der Leiterplatte 19. Der Abstand zwischen Bonddraht 16 und Kontaktfläche 18 ist variabel im Bereich von wenigen μm bis zu 100 μm und mehr.Opposite the free end of the bonding wire 16 is the contact surface 18 the circuit board 19 , The distance between bonding wire 16 and contact area 18 is variable in the range of a few microns up to 100 microns and more.

Auf der Kontaktfläche 18 ist ein elektrisch leitfähiges Material 17 angebracht, welches nach der Annäherung den Bonddraht 16 umschließt und nach einem Stabilisierungsschritt eine feste Verbindung mit dem Bonddraht 16 eingeht. Das elektrisch leitfähige Material 17 kann ein Schmelzlot oder ein elektrisch leitfähiger Klebstoff sein.On the contact surface 18 is an electrically conductive material 17 attached, which after approach the bonding wire 16 encloses and after a stabilization step, a firm connection with the bonding wire 16 received. The electrically conductive material 17 may be a fusible link or an electrically conductive adhesive.

Wie 1 zeigt, werden auf einen Anschlusskontakt 12 eines Halbleiterchips 11 ein Drahtbondanschluss 15 mit einem Drahtbondverfahren aufgesetzt, dessen freies Ende des Bonddrahtes 16 auf dem Halbleiterchip 11 neben dem Anschlusskontakt 12 endet. Beim Ausbilden dieses Endes muss der Bonddraht 16 auf dem Untergrund haften um ein weiteres Stück Bonddraht aus der Kapillare der Drahtbondmaschine zu ziehen, aus dem der Ball für den folgenden Drahtbondanschluss 15 angeschmolzen wird. Weiterhin muss der Bonddraht 16 durch Klemmen in der Kapillare abreißbar sein, ohne dass das freie Ende des Bonddrahtes 16 vom Untergrund abhebt, der eine Passivierungsschicht 13 oder eine darauf aufgebrachte Zwischenschicht 14 sein kann.As 1 shows are on a connection contact 12 a semiconductor chip 11 a wire bond connection 15 fitted with a wire bonding method, the free end of the bonding wire 16 on the semiconductor chip 11 next to the connection contact 12 ends. When forming this end, the bonding wire must be 16 stick to the ground to pull another piece of bonding wire from the capillary of Drahtbondmaschine, from which the ball for the following Drahtbondanschluss 15 is melted. Furthermore, the bonding wire must 16 be torn off by clamping in the capillary, without the free end of the bonding wire 16 stands out from the ground, which has a passivation layer 13 or an intermediate layer applied thereto 14 can be.

Um die Strukturen des Halbleiterchips 11 beim Drahtbonden vor mechanischer Überbelastung zu schützen und den Drahtbond-Prozess zu unterstützen, kann vor dem Aufbringen der Drahtverbindungen 15 auf die Passivierungsschicht 13 eine Zwischenschicht 14 aufgebracht werden, die die mechanischen Belastungen aufnimmt und eine Haftung des freien Endes des Bonddrahtes 16 bewirkt. Die Zwischenschicht 14 kann die Oberfläche des Halbleiterchips 11 mit Ausnahme der Anschlusskontakte 12 vollständig bedecken oder nur in den Bereichen um die Anschlusskontakte 12 angeordnet sein. Die Zwischenschicht 14 besteht vorzugsweise aus einem elastischen dielektrischen Material mit einer Dicke im Bereich von 5 bis 50 μm. Das Material kann ein geeignetes Polymer oder ein Kunstharz sein. Dieses Material kann per Siebdruck auf den einzelnen Halbleiterchip 11 oder den die Halbleiterchips enthaltenden Wafer aufgebracht werden. Alternativ kann die Zwischenschicht 14 aus einem Klebeband bestehen, welches auf die Oberfläche des Halbleiterchips 11 aufgebracht wird. Das Klebeband kann einseitig oder zweiseitig haftfähig sein.To the structures of the semiconductor chip 11 To guard against mechanical overload during wire bonding and to support the wire bonding process may be prior to applying the wire bonds 15 on the passivation layer 13 an intermediate layer 14 be applied, which absorbs the mechanical stresses and adhesion of the free end of the bonding wire 16 causes. The intermediate layer 14 may be the surface of the semiconductor chip 11 with the exception of the connection contacts 12 completely cover or only in the areas around the terminals 12 be arranged. The intermediate layer 14 is preferably made of an elastic dielectric material having a thickness in the range of 5 to 50 microns. The material may be a suitable polymer or a synthetic resin. This material can be screen printed on the individual semiconductor chip 11 or the wafers containing the semiconductor chips are applied. Alternatively, the intermediate layer 14 consist of an adhesive tape, which on the surface of the semiconductor chip 11 is applied. The tape may be single-sided or double-sided adhesive.

Die Oberfläche der Passivierungsschicht 13 oder der Zwischenschicht 14 kann vor dem Drahtbonden durch eine Plasma-Behandlung, z. B. mit Wasserdampf, aktiviert werden. Damit wird diese Oberfläche vorübergehend haftfähig. Durch Absorption von Luftfeuchtigkeit nimmt diese Haftfähigkeit mit der Zeit wieder ab. Die Aktivierung der Oberfläche zur zeitweise verbesserten Haftung kann alternativ durch den Kontakt mit einem Lösemittel erreicht werden.The surface of the passivation layer 13 or the intermediate layer 14 can before wire bonding by a plasma treatment, for. B. with water vapor, activated. Thus, this surface is temporarily liable. By absorbing moisture, this adhesion decreases over time. The activation of the surface for temporarily improved adhesion can alternatively be achieved by contact with a solvent.

Eine andere Möglichkeit besteht darin, auf die nichthaftende Oberfläche der Passivierungsschicht 13, der Zwischenschicht 14 oder des Klebebandes im Bereich des Bonddrahtes 16 einen zusätzlichen Klebstoff aufzubringen. Dieser Klebstoff besteht vorzugsweise aus einem viskosen Material, welches einen Teil des Bonddrahtes 16 aufnimmt und fixiert. Der Klebstoff sollte jedoch vorzugsweise nicht im Aufsetzbereich der Bondkapillare angeordnet sein.Another possibility is to apply to the non-adhesive surface of the passivation layer 13 , the intermediate layer 14 or of the adhesive tape in the region of the bonding wire 16 to apply an additional adhesive. This adhesive is preferably made of a viscous material, which is a part of the bonding wire 16 picks up and fixes. However, the adhesive should preferably not be arranged in the contact area of the bonding capillary.

Die Zwischenschicht 14 und die nachfolgende Drahtbond-Verbindung können auf den bereits vereinzelten Halbleiterchip oder auf den Halbleiterchip aufgebracht werden, wenn dieser noch im Waferverbund ist.The intermediate layer 14 and the subsequent Drahtbond connection can be applied to the already isolated semiconductor chip or on the semiconductor chip, if this is still in the wafer assembly.

Auf der Leiterplatte 19 sind Kontaktflächen 18 vorgesehen, die mit einem elektrisch leitfähigen Material 17, beispielsweise mit Lotpaste bedruckt werden können, beispielsweise mittels Siebdruck.On the circuit board 19 are contact surfaces 18 provided with an electrically conductive material 17 , For example, can be printed with solder paste, for example by screen printing.

Nach dem Platzieren des Halbleiterchips 11 mit einem freien Ende des Bonddrahtes 16 gegenüber einer Kontaktfläche 18 der Leiterplatte 19 wird die Lotpaste in einen Reflow-Prozess aufgeschmolzen und damit eine formschlüssige elektrische Verbindung 17 zwischen Halbleiterchip 11 mit dem freien Ende des Bonddrahtes 16 und Leiterplatte 19 hergestellt. Vor dem Aufschmelzen der Lotpaste kann Flussmittel zur besseren Kontaktierung der Lötstellen zugegeben werden.After placing the semiconductor chip 11 with a free end of the bonding wire 16 opposite a contact surface 18 the circuit board 19 the solder paste is melted in a reflow process and thus a positive electrical connection 17 between the semiconductor chip 11 with the free end of the bonding wire 16 and circuit board 19 produced. Before the solder paste melts, flux can be added to better contact the solder joints.

Alternativ zur Lotpaste kann auf die Kontaktflächen 18 der Leiterplatte ein Leitkleber aufgebracht werden, beispielsweise mittels Siebdruck. Der Leitkleber ist beim Aufbringen auf die Leiterplatte 19 und beim Zusammenfügen mit dem Halbleiterchip 11 pastös und härtet erst danach in einem Stabilisierungsschritt aus.Alternatively to the solder paste may be on the contact surfaces 18 the circuit board, a conductive adhesive are applied, for example by screen printing. The conductive adhesive is when applied to the circuit board 19 and when mating with the semiconductor chip 11 pasty and only then hardens in a stabilization step.

Dieser Stabilisierungsschritt kann je nach Material des Leitklebers selbsttätig mit Zeitfortschritt oder durch eine Wärmebehandlung erfolgen.Depending on the material of the conductive adhesive, this stabilization step can be carried out automatically with time progress or by heat treatment.

Zur mechanischen Unterstützung kann nach der Stabilisierung der formschlüssigen elektrischen Verbindung ein kriechfähiges Material in den Spalt zwischen Halbleiterchip 11 und Leiterplatte 19 eingebracht werden, welches nach dem Aushärten den Halbleiterchip 11 mechanisch auf der Leiterplatte 19 fixiert (sog. Underfill). Zusätzlich oder alternativ kann der Halbleiterchip 11 auf der Leiterplatte 19 oder die komplette Leiterplatte 19 mit Halbleiterchip 11 mit einem Kunstharz versehen werden, welches nach dem Aushärten einem mechanischen Schutz vor Umwelteinflüssen darstellt.For mechanical support, after the stabilization of the positive electrical connection, a creeping material can enter the gap between the semiconductor chip 11 and circuit board 19 are introduced, which after curing the semiconductor chip 11 mechanically on the circuit board 19 fixed (so-called underfill). Additionally or alternatively, the semiconductor chip 11 on the circuit board 19 or the complete circuit board 19 with semiconductor chip 11 be provided with a synthetic resin, which represents a mechanical protection from environmental influences after curing.

In den 2 und 3 ist beispielsweise gezeigt, wie die Verbindung der Anschlusskontakte 12, die in einem engen Raster auf dem Halbleiterchip 11 angeordnet sind, mittels Bonddrahtanschluss 15 und Bonddraht 16 auf die Kontaktflächen 18 der Leiterplatte erfolgt, wenn diese Kontaktflächen 18 in einem größeren Raster als die Anschlusskontakte 12 angeordnet sind.In the 2 and 3 For example, it shows how the connection of the terminals 12 in a tight grid on the semiconductor chip 11 are arranged by means of bonding wire connection 15 and bonding wire 16 on the contact surfaces 18 the circuit board takes place when these contact surfaces 18 in a larger grid than the connection contacts 12 are arranged.

2 ist ein Beispiel für Halbleiterchips 11 mit einer Reihe von Anschlusskontakten 12, 3 ist ein Beispiel für Halbleiterchips 11 mit zwei Reihen von Anschlusskontakten 12. 2 is an example of semiconductor chips 11 with a number of connection contacts 12 . 3 is an example of semiconductor chips 11 with two rows of connection contacts 12 ,

BezugszeichenlisteLIST OF REFERENCE NUMBERS

1111
Chipchip
1212
Anschlusskontakt auf dem ChipConnection contact on the chip
1313
Passivierungsschichtpassivation
1414
Zwischenschichtinterlayer
1515
DrahtbondanschlussWire bond
1616
Bonddrahtbonding wire
1717
elektrisch leitfähiges Materialelectrically conductive material
1818
Kontaktfläche auf der LeiterplatteContact surface on the circuit board
1919
Leiterplattecircuit board

Claims (19)

Chip-Leiterplatten-Anordnung, aufweisend: – eine Leiterplatte (19) mit einer Kontaktfläche (18); – einen Halbleiterchip (11) mit einem elektrischen Anschlusskontakt (12) und einer Passivierungsschicht (13), die neben dem Anschlusskontakt (12) angeordnet ist; – eine Drahtbondverbindung (15) mit Bonddraht (16) auf dem Anschlusskontakt (12) des Halbleiterchips, wobei – der Bonddraht (16) auf der Passivierungsschicht (13) des Halbleiterchips (11) endet, wobei die Passivierungsschicht (13) zum Zeitpunkt des Drahtbondens eine haftfähige Oberfläche aufweist, und wobei – die Kontaktfläche (18) der Leiterplatte (19) gegenüber dem Ende des Bonddrahtes (16) angeordnet ist und – der Bonddraht (16) mit der Kontaktfläche (18) der Leiterplatte (19) über ein elektrisch leitfähiges Material (17) verbunden ist.Chip circuit board assembly comprising: - a printed circuit board ( 19 ) with a contact surface ( 18 ); A semiconductor chip ( 11 ) with an electrical connection contact ( 12 ) and a passivation layer ( 13 ) next to the terminal 12 ) is arranged; A wire bond ( 15 ) with bonding wire ( 16 ) on the connection contact ( 12 ) of the semiconductor chip, wherein - the bonding wire ( 16 ) on the passivation layer ( 13 ) of the semiconductor chip ( 11 ), wherein the passivation layer ( 13 ) has an adhesive surface at the time of wire bonding, and wherein - the contact surface ( 18 ) of the printed circuit board ( 19 ) opposite the end of the bonding wire ( 16 ) is arranged and - the bonding wire ( 16 ) with the contact surface ( 18 ) of the printed circuit board ( 19 ) via an electrically conductive material ( 17 ) connected is. Chip-Leiterplatten-Anordnung gemäß Anspruch 1, wobei auf der Passivierungsschicht (13) bereichsweise eine Zwischenschicht (14) angeordnet ist.A chip circuit board assembly according to claim 1, wherein on the passivation layer ( 13 ) an intermediate layer ( 14 ) is arranged. Chip-Leiterplatten-Anordnung gemäß Anspruch 2, wobei die Zwischenschicht (14) ein dielektrisches Material aufweist.A chip circuit board assembly according to claim 2, wherein the intermediate layer ( 14 ) comprises a dielectric material. Chip-Leiterplatten-Anordnung gemäß einem der Ansprüche 2 bis 3, wobei die Zwischenschicht (14) ein elastisches Material aufweist.A chip circuit board assembly according to one of claims 2 to 3, wherein the intermediate layer ( 14 ) comprises an elastic material. Chip-Leiterplatten-Anordnung gemäß einem der Ansprüche 2 bis 4, wobei die Zwischenschicht (14) zum Zeitpunkt des Drahtbondens eine haftfähige Oberfläche aufweist.Chip circuit board arrangement according to one of claims 2 to 4, wherein the intermediate layer ( 14 ) has an adhesive surface at the time of wire bonding. Chip-Leiterplatten-Anordnung gemäß einem der Ansprüche 2 bis 5, wobei die Zwischenschicht (14) aus einem einseitig haftfähigen Klebeband besteht.Chip circuit board arrangement according to one of claims 2 to 5, wherein the intermediate layer ( 14 ) consists of a one-sided adhesive tape. Chip-Leiterplatten-Anordnung gemäß einem der Ansprüche 2 bis 5, wobei die Zwischenschicht (14) aus einem zweiseitig haftfähigen Klebeband besteht.Chip circuit board arrangement according to one of claims 2 to 5, wherein the intermediate layer ( 14 ) consists of a double-sided adhesive tape. Chip-Leiterplatten-Anordnung gemäß einem der Ansprüche 2 bis 4, wobei die Zwischenschicht (14) eine nichthaftende Oberfläche aufweist und im Bereich des Bonddrahtes (16) ein zusätzlicher Klebstoff auf der Zwischenschicht (14) angeordnet ist.Chip circuit board arrangement according to one of claims 2 to 4, wherein the intermediate layer ( 14 ) has a non-adhesive surface and in the region of the bonding wire ( 16 ) an additional adhesive on the intermediate layer ( 14 ) is arranged. Chip-Leiterplatten-Anordnung gemäß einem der Ansprüche 1 bis 8, wobei das elektrisch leitfähige Material (17) ein Schmelzlot ist.A chip circuit board assembly according to any one of claims 1 to 8, wherein the electrically conductive material ( 17 ) is a fusible link. Chip-Leiterplatten-Anordnung gemäß einem der Ansprüche 1 bis 8, wobei das elektrisch leitfähige Material (17) ein Leitkleber ist.A chip circuit board assembly according to any one of claims 1 to 8, wherein the electrically conductive material ( 17 ) is a conductive adhesive. Verfahren zum Herstellen einer Chip-Leiterplatten-Anordnung, aufweisend die Schritte: – Bereitstellen eines Halbleiterchips (11) mit einem elektrischen Anschlusskontakt (12) und einer Passivierungsschicht (13) auf dem Halbleiterchip (11), die neben dem Anschlusskontakt (12) angeordnet ist, wobei die Passivierungsschicht (13) eine haftfähige Oberfläche aufweist; – Herstellen einer Drahtbondverbindung (15) auf dem Anschlusskontakt (12) des Halbleiterchips, wobei das offene Ende des Bonddrahtes (16) auf der Passivierungsschicht (13) des Halbleiterchips endet; – Bereitstellen einer Leiterplatte (19) mit einer Kontaktfläche (18) und einem darauf aufgebrachten leitfähigen Material (17); – Anordnen der Leiterplatte (19) gegenüber dem Chip (11) so, dass sich die Kontaktfläche (18) der Leiterplatte mit dem elektrisch leitfähigen Material (17) über dem offenen Ende des Bonddrahtes (16) befindet und – Durchführen eines Stabilisierungsschrittes, wobei das elektrisch leitfähige Material (17) mit einem Teil des Bonddrahtes (16) eine feste Verbindung eingeht. A method of manufacturing a chip circuit board assembly, comprising the steps of: - providing a semiconductor chip ( 11 ) with an electrical connection contact ( 12 ) and a passivation layer ( 13 ) on the semiconductor chip ( 11 ) next to the terminal 12 ), wherein the passivation layer ( 13 ) has an adhesive surface; - making a wire bond connection ( 15 ) on the connection contact ( 12 ) of the semiconductor chip, wherein the open end of the bonding wire ( 16 ) on the passivation layer ( 13 ) of the semiconductor chip ends; Providing a printed circuit board ( 19 ) with a contact surface ( 18 ) and a conductive material applied thereto ( 17 ); - arranging the printed circuit board ( 19 ) opposite the chip ( 11 ) so that the contact surface ( 18 ) of the printed circuit board with the electrically conductive material ( 17 ) over the open end of the bonding wire ( 16 ) and performing a stabilization step, wherein the electrically conductive material ( 17 ) with a part of the bonding wire ( 16 ) enters a firm connection. Verfahren gemäß Anspruch 11, wobei auf der Passivierungsschicht (13) des Halbleiterchips (11) vor dem Herstellen der Drahtbondverbindung eine Zwischenschicht (14) abgeschieden wird.Method according to claim 11, wherein on the passivation layer ( 13 ) of the semiconductor chip ( 11 ) prior to making the wire bond an intermediate layer ( 14 ) is deposited. Verfahren gemäß Anspruch 11, wobei auf der Passivierungsschicht (13) des Halbleiterchips (11) vor dem Herstellen der Drahtbondverbindung als Zwischenschicht (14) ein Klebeband angeordnet wird.Method according to claim 11, wherein on the passivation layer ( 13 ) of the semiconductor chip ( 11 ) prior to making the wire bond as an intermediate layer ( 14 ) An adhesive tape is arranged. Verfahren gemäß einem der Ansprüche 11 bis 13, wobei die Oberfläche der Passivierungsschicht (13) oder der Zwischenschicht (14) vor dem Herstellen der Drahtbondverbindung durch eine Plasmabehandlung aktiviert und haftfähig gemacht wird.Method according to one of claims 11 to 13, wherein the surface of the passivation layer ( 13 ) or the intermediate layer ( 14 ) is activated and made adhesive by plasma treatment prior to making the wire bond. Verfahren gemäß einem der Ansprüche 11 bis 13, wobei die Oberfläche der Passivierungsschicht (13) oder der Zwischenschicht (14) vor dem Herstellen der Drahtbondverbindung durch die Einwirkung eines Lösemittels haftfähig gemacht wird.Method according to one of claims 11 to 13, wherein the surface of the passivation layer ( 13 ) or the intermediate layer ( 14 ) is rendered adhesive by the action of a solvent prior to making the wire bond. Verfahren gemäß einem der Ansprüche 11 bis 13, wobei auf die nichthaftende Oberfläche der Passivierungsschicht (13) oder der Zwischenschicht (14) vor dem Herstellen der Drahtbondverbindung im Bereich des Bonddrahtes (16) ein zusätzlicher Klebstoff aufgebracht wird.Method according to one of claims 11 to 13, wherein the non-adhesive surface of the passivation layer ( 13 ) or the intermediate layer ( 14 ) prior to making the wire bond in the region of the bonding wire ( 16 ) an additional adhesive is applied. Verfahren gemäß einem der Ansprüche 11 bis 16, wobei der Stabilisierungsschritt ein Erwärmen des elektrisch leitfähigen Materials (17) umfasst.A method according to any one of claims 11 to 16, wherein the stabilizing step comprises heating the electrically conductive material ( 17 ). Verfahren gemäß Anspruch 17, wobei der Stabilisierungsschritt ein Aufschmelzen des elektrisch leitfähigen Materials (17) umfasst.A method according to claim 17, wherein the stabilizing step comprises melting the electrically conductive material ( 17 ). Verfahren gemäß Anspruch 17, wobei der Stabilisierungsschritt ein Aushärten des elektrisch leitfähigen Materials (17) umfasst.The method of claim 17, wherein said stabilizing step comprises curing said electrically conductive material ( 17 ).
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6211461B1 (en) * 1998-06-29 2001-04-03 Hyundai Electronics Industries Co., Ltd. Chip size package and method of fabricating the same
US6972496B2 (en) * 2001-06-12 2005-12-06 Hynix Semiconductor Inc. Chip-scaled package having a sealed connection wire

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6211461B1 (en) * 1998-06-29 2001-04-03 Hyundai Electronics Industries Co., Ltd. Chip size package and method of fabricating the same
US6972496B2 (en) * 2001-06-12 2005-12-06 Hynix Semiconductor Inc. Chip-scaled package having a sealed connection wire

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