DE102008026347A1 - Power-electronic arrangement, has electrically conducting regions arranged in edge region, where arrangement between one of conducting regions and base body comprises electrically conductive connection - Google Patents
Power-electronic arrangement, has electrically conducting regions arranged in edge region, where arrangement between one of conducting regions and base body comprises electrically conductive connection Download PDFInfo
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- DE102008026347A1 DE102008026347A1 DE102008026347A DE102008026347A DE102008026347A1 DE 102008026347 A1 DE102008026347 A1 DE 102008026347A1 DE 102008026347 A DE102008026347 A DE 102008026347A DE 102008026347 A DE102008026347 A DE 102008026347A DE 102008026347 A1 DE102008026347 A1 DE 102008026347A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/62—Protection against overvoltage, e.g. fuses, shunts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
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Abstract
Description
Die Erfindung beschreibt eine leistungselektronische Anordnung mit einem Substrat und einem Grundkörper, wie sie beispielhaft Teil eines Leistungshalbleitermoduls ist.The Invention describes a power electronic device having a Substrate and a basic body, as example part a power semiconductor module.
Grundsätzlich
bekannt sind Leistungshalbleitermodule mit einem Grundkörper,
der als Grundplatte des Leistungshalbleitermoduls selbst oder als
zusätzlicher Kühlkörper ausgebildet ist.
Derartige Leistungshalbleitermodule bieten gegenüber diskreten Leistungsschaltern
(z. B. Scheibenzellen, TO220) den großen Vorteil der inneren
Isolierung gegenüber einer Wärmesenke, hier beispielhaft
dem Grundkörper. Diese innere Isolierung wird gemäß dem
Stand der Technik beispielhaft durch den Einsatz von keramischen
Substraten erreicht, die eine hohe Durchschlagsfestigkeit mit einer
großen Wärmeleitfähigkeit verbinden.
Sie erlauben den effizienten Aufbau von Leistungsschaltungen, da
sie neben der Basisisolierung, der Isolation zur Umgebung auch eine
Funktionsisolierung, die Isolierung verschiedener Bereiche gegeneinander
auf einer strukturierten und mit Bauelementen versehenen Fläche,
bereitstellen. Derartige Leistungshalbleitermodule, mit keramischen
Substraten sind beispielhaft aus der
All diesen Ausgestaltungen von Leistungshalbleitermodulen nach dem Stand der Technik ist gemeinsam die Verwendung eines keramischen Isolierstoffkörpers mit Leiterbahnen auf dessen erster und einer flächigen Metallkaschierung auf dessen zweiter Hauptfläche, hergestellt z. B. durch eine Spinellbindung zwischen Aluminiumoxid (Al2O3) und Kupferoxid nach dem ”Direct Copper Bonding”(DCB)-Verfahren oder durch ein Aktivlötverfahren ”Active Metal Brazing” (AMB).All these embodiments of power semiconductor modules according to the prior art, the use of a ceramic insulating material with interconnects on the first and a flat metal lamination on the second major surface, prepared z. Example by a spinel bond between alumina (Al 2 O 3 ) and copper oxide by the "Direct Copper Bonding" (DCB) method or by an active soldering method "Active Metal Brazing" (AMB).
Bei
allen bekannten Ausgestaltungen dieser Substrate dehnen sich die
Leiterbahnen nicht bis an den Rand des Substrats aus, wodurch dort
ein elektrisch nicht leitender Bereich ausgebildet wird. Typischerweise
reicht auch die flächige Metallkaschierung auf der zweiten
Hauptfläche des Isolierstoffkörpers nicht an den
somit durch diesen gebildeten Rand des Substrats heran. Durch diese
Anordnung ergibt sich eine bis zu gewissen Spannungsgrenzen ausreichende
Durchschlagsfestigkeit der Anordnung aus Substrat, hierauf angeordneten
Leiterbahn und einem typischerweise auf Grundpotential liegendem Grundkörper.
Es ist aus der
Beispielhaft
aus der nicht vorveröffentlichten
Der Erfindung liegt die Aufgabe zugrunde eine leistungselektronische Anordnung mit einem Substrat und einem Grundkörper anzugeben, wobei die Durchschlagsfestigkeit am Randbereich unabhängig von der Art des Substrats erhöht wird.Of the Invention is based on a power electronic Specify arrangement with a substrate and a base body, the dielectric strength at the edge area is independent is increased by the type of substrate.
Diese Aufgabe wird erfindungsgemäß gelöst, durch ein Leistungshalbleitermodul mit den Merkmalen des Anspruchs 1. Bevorzugte Ausführungsformen sind in den abhängigen Ansprüchen beschrieben.These Problem is solved according to the invention, by a power semiconductor module having the features of the claim 1. Preferred embodiments are in the dependent Claims described.
Ausgangspunkt der erfindungsgemäßen Lösung sind Leistungshalbleitermodule gemäß dem oben beschrieben Stand der Technik, wobei die folgenden Ausführungen nicht nur hierauf und auch nicht auf die oben genannten Ausbildung der Substrate beschränkt sind.starting point The solution according to the invention are power semiconductor modules according to the above-described prior art, the following not only apply thereto and also not limited to the above-mentioned formation of the substrates are.
Die erfindungsgemäße leistungselektronische Anordnung weist ein Substrat und einen Grundkörper, beispielhaft einen Kühlkörper eines Leistungshalbleitermoduls, auf. Dieser Grundkörper schließt sich an der zweiten Hauptfläche des Substrats an und ist mit diesem zumindest thermisch leitend verbundenen. Der Grundkörper besteht hierbei aus einem elektrisch leitenden oder leitfähigen Material und liegt auf Grundpotential.The inventive power electronic device has a substrate and a base body, by way of example a heat sink of a power semiconductor module, on. This basic body closes at the second Main surface of the substrate and is at least with this thermally conductively connected. The basic body exists in this case of an electrically conductive or conductive Material and is based on ground potential.
Auf einer ersten elektrisch isolierend ausgebildeten Hauptfläche des Substrats ist mindestens eine erste, hohes Potential gegenüber dem Grundkörper aufweisende, Leiterbahn angeordnet. In Leistungshalbleitermodulen sind auf derartigen Leiterbahnen die Leistungshalbleiterbauelemente angeordnet, ebenso sind die schaltungsgerechten Verbindungen zumindest teilweise mittels derartiger Leiterbahn ausgebildet. Typischerweise sind in Leistungshalbleitermodulen eine Mehrzahl derartiger Leiterbahn angeordnet, die im Betrieb unterschiedliches Potential aufweisen.On a first electrically insulating main surface of the substrate is at least a first, high potential opposite arranged the main body, conductor track. In Power semiconductor modules are on such traces the Power semiconductor devices arranged, as are the circuit right Compounds at least partially formed by means of such a conductor track. Typically, in power semiconductor modules, a plurality arranged such a track, the different potential during operation exhibit.
Gemäß dem Stand der Technik sind diese Leiterbahnen räumlich begrenzt wobei ihre Außengrenze diejenige dem Rand des Substrats zugewandte Begrenzung darstellt. Diese Außengrenze ist von dem Außenrand des Substrats beabstandet. In dem hierdurch gebildeten Randbereich sind zwischen der Leiterbahn und der Außengrenze mindestens ein erster und ein zweiter elektrisch leitender Bereich angeordnet. Es ist hierbei offensichtlich bevorzugt, wenn der mindestens eine erste und der zweite leitende Bereich voneinander und von der mindestens einen ersten hohes Potential aufweisenden Leiterbahn elektrisch isoliert sind. Weiteres Kennzeichnen für die erfindungsgemäße Anordnung ist hierbei, dass zwischen dem zweiten leitenden Bereich und dem Grundkörper eine elektrisch leitende Verbindung angeordnet ist. Es kann hierbei bevorzugt sein, wenn diese Verbindung hochohmig ausgebildet ist.According to the prior art, these interconnects are spatially limited, with their outer boundary representing the boundary facing the edge of the substrate. This outer boundary is spaced from the outer edge of the substrate. At least one first and one second electrically conductive region are arranged between the conductor track and the outer boundary in the edge region formed as a result. It is obviously here before zugt if the at least one first and the second conductive region from each other and from the at least one first high potential having conductor track are electrically isolated. Another characteristic of the arrangement according to the invention here is that between the second conductive region and the base body, an electrically conductive connection is arranged. It may be preferred in this case if this connection is formed high impedance.
Es kann ebenso bevorzugt sein, wenn das Substrat einen Isolierstoffkörper und hiermit verbunden eine flächige elektrisch leitende Schicht, ein Metallkaschierung, gemäß dem oben beschriebenen Stand der Technik aufweist. Hierbei bildet die dem Isolierstoffkörper abgewandte Oberfläche dieser Metallkaschierung die zweite Hauptfläche des Substrats aus.It may also be preferred if the substrate is an insulating material and connected thereto a planar electrically conductive Layer, a metal lamination, according to the above has described prior art. This forms the insulating body opposite surface of this metal lamination the second Main surface of the substrate.
Eine besonders bevorzugte Anordnung ergibt sich, wenn die mindestens eine erste und die zweite leitende Schicht auf dem Randbereich des Substrats vollständig umlaufend um diesen Randbereich ausgebildet sind. Hierbei bilden sich um den aktiven Bereich, hier die auf dem Substrat angeordnete Schaltung, eine Art Feldringstruktur vergleichbar einer Leistungsdiode aus, wodurch die Durchschlagsfestigkeit der Anordnung erhöht wird.A particularly preferred arrangement results when the at least a first and second conductive layers on the edge region of the substrate completely formed circumferentially around this edge region are. This form around the active area, here on the Substrate arranged circuit, a kind of field ring structure comparable a power diode, whereby the dielectric strength of the Arrangement is increased.
Aus Gründen der inneren Isolation, beispielhaft im Inneren eines Leistungshalbleitermoduls ist es bevorzugt, wenn die die Zwischenräume zwischen der ersten Leiterbahn und dem ersten leitenden Bereich und zwischen den leitenden Bereichen mit einem Isolationsstoff verfüllt sind.Out For reasons of internal isolation, exemplary inside a power semiconductor module, it is preferable if the the gaps between the first conductive line and the first conductive region and filled between the conductive areas with an insulating material are.
Besonders
bevorzugte Weiterbildungen dieser Schaltungsanordnung sind in der
jeweiligen Beschreibung der Ausführungsbeispiele genannt.
Die erfinderische Lösung wird zudem an Hand der Ausführungsbeispiele
der
Auf
der ersten Hauptfläche (
Diese
Leiterbahn (
In
diesem Randbereich (
Für
die Ausbildung der ersten (
Weiterhin
ist schematisch dargestellt, dass der zweite elektrisch leitende
Bereich (
Weiterhin
unterscheidet sich diese Ausgestaltung dahingehend, dass die Außengrenze
(
Weiterhin
dargestellt ist die elektrisch leitende Verbindung (
Weiterhin
dargestellt und speziell auch bei diese Ausgestaltung der ersten
(
Ebenso
kann es bevorzugt sein, wenn die Zwischenräume (
Dargestellt
ist hier nicht nur eine Leiterbahn (
Dargestellt
sind hier ebenfalls wie unter
ZITATE ENTHALTEN IN DER BESCHREIBUNGQUOTES INCLUDE IN THE DESCRIPTION
Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.
Zitierte PatentliteraturCited patent literature
- - US 5466969 [0002] US 5466969 [0002]
- - EP 0750345 A2 [0002] EP 0750345 A2 [0002]
- - DE 19700963 A1 [0002] DE 19700963 A1 [0002]
- - DE 10063714 A1 [0004] - DE 10063714 A1 [0004]
- - DE 102007062305 A1 [0005] - DE 102007062305 A1 [0005]
Claims (8)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102008026347A DE102008026347B4 (en) | 2008-05-31 | 2008-05-31 | Power electronic device with a substrate and a base body |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102008026347A DE102008026347B4 (en) | 2008-05-31 | 2008-05-31 | Power electronic device with a substrate and a base body |
Publications (2)
Publication Number | Publication Date |
---|---|
DE102008026347A1 true DE102008026347A1 (en) | 2010-02-18 |
DE102008026347B4 DE102008026347B4 (en) | 2010-08-19 |
Family
ID=41527853
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE102008026347A Expired - Fee Related DE102008026347B4 (en) | 2008-05-31 | 2008-05-31 | Power electronic device with a substrate and a base body |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE102008026347B4 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102011004544A1 (en) | 2011-02-22 | 2012-08-23 | Semikron Elektronik Gmbh & Co. Kg | circuitry |
EP2525402A1 (en) * | 2011-05-17 | 2012-11-21 | ALSTOM Transport SA | Electrical insulation device with improved breakdown voltage |
DE102016214741B4 (en) | 2016-08-09 | 2022-05-12 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Structure for at least one carrier fitted with electronic and/or electrical components |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5077595A (en) * | 1990-01-25 | 1991-12-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
US5466969A (en) | 1991-11-07 | 1995-11-14 | Kabushiki Kaisha Toshiba | Intelligent power device module |
EP0750345A2 (en) | 1995-06-19 | 1996-12-27 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG | Power semiconductor module |
DE19700963A1 (en) | 1997-01-14 | 1998-07-16 | Telefunken Microelectron | Method for producing a power module with an active semiconductor component and a circuit arrangement having passive semiconductor components |
EP1063700A2 (en) * | 1999-06-22 | 2000-12-27 | Siemens Aktiengesellschaft | Substrate for high voltage modules |
DE10063714A1 (en) | 2000-12-20 | 2002-07-04 | Semikron Elektronik Gmbh | Power semiconductor module comprises a housing, contacting elements, a semiconductor component and a ceramic substrate with a metal coating partially covering the first and the second surface of the ceramic substrate |
DE10135348A1 (en) * | 2001-07-20 | 2003-01-30 | Abb Research Ltd | Method for manufacturing. semiconductor modules, or structures for them, or semiconductor elements for HV |
-
2008
- 2008-05-31 DE DE102008026347A patent/DE102008026347B4/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5077595A (en) * | 1990-01-25 | 1991-12-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
US5466969A (en) | 1991-11-07 | 1995-11-14 | Kabushiki Kaisha Toshiba | Intelligent power device module |
EP0750345A2 (en) | 1995-06-19 | 1996-12-27 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG | Power semiconductor module |
DE19700963A1 (en) | 1997-01-14 | 1998-07-16 | Telefunken Microelectron | Method for producing a power module with an active semiconductor component and a circuit arrangement having passive semiconductor components |
EP1063700A2 (en) * | 1999-06-22 | 2000-12-27 | Siemens Aktiengesellschaft | Substrate for high voltage modules |
DE10063714A1 (en) | 2000-12-20 | 2002-07-04 | Semikron Elektronik Gmbh | Power semiconductor module comprises a housing, contacting elements, a semiconductor component and a ceramic substrate with a metal coating partially covering the first and the second surface of the ceramic substrate |
DE10135348A1 (en) * | 2001-07-20 | 2003-01-30 | Abb Research Ltd | Method for manufacturing. semiconductor modules, or structures for them, or semiconductor elements for HV |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102011004544A1 (en) | 2011-02-22 | 2012-08-23 | Semikron Elektronik Gmbh & Co. Kg | circuitry |
EP2492957A2 (en) | 2011-02-22 | 2012-08-29 | SEMIKRON Elektronik GmbH & Co. KG | Switching assembly |
EP2525402A1 (en) * | 2011-05-17 | 2012-11-21 | ALSTOM Transport SA | Electrical insulation device with improved breakdown voltage |
FR2975528A1 (en) * | 2011-05-17 | 2012-11-23 | Alstom Transport Sa | DEVICE FOR ELECTRICALLY INSULATING A CONDUCTIVE PLAN HAVING A FIRST ELECTRICAL POTENTIAL IN RELATION TO A SECOND POTENTIAL, COMPRISING MEANS FOR REDUCING THE ELECTROSTATIC FIELD VALUE AT A POINT OF THE PERIPHERAL EDGE OF THE CONDUCTIVE PLANE |
US9287223B2 (en) | 2011-05-17 | 2016-03-15 | Alstom Transport Sa | Device for electric insulation of a conducting plane |
DE102016214741B4 (en) | 2016-08-09 | 2022-05-12 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Structure for at least one carrier fitted with electronic and/or electrical components |
Also Published As
Publication number | Publication date |
---|---|
DE102008026347B4 (en) | 2010-08-19 |
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