DE102008018011B4 - Circuit arrangement for operating a capacitive load and use of such a circuit arrangement - Google Patents

Abstract

Circuit arrangement for operating a capacitive load (P), comprising - a first supply terminal (E1) and a second supply terminal (E2) for applying a first supply potential (GND) or a second supply potential (VBAT), - a first output terminal (A1) and a second output terminal (A2) for connecting the load (P), the first output terminal (A1) being connected to the first supply terminal (E1), a capacitor arranged between a first circuit node (K1) and a second circuit node (K2) ( C), - a first inductance (L1) arranged between the second supply terminal (E2) and the first circuit node (K1), - a first controllable switch (Q1) arranged between the first circuit node (K1) and the first supply terminal (E1), - A between the second circuit node (K2) and the first supply terminal (E1) arranged second inductance (L2), - ei NEN between the second circuit node (K2) and the second output terminal (A2) arranged second controllable switch (Q2), and - a control device (ST) for providing control signals (q1, q2) for driving the two switches (Q1, Q2), characterized in that the circuit arrangement further comprises a transistor (Q3) arranged between the second output terminal (A2) and the first output terminal (A1) and means (OPAMP, Rs3) for controlled adjustment of a current flowing through the transistor (Q3).

Description

The present invention relates to a circuit arrangement for operating a capacitive load, such. B. a piezoelectric actuator.

Such circuit arrangements are known in various embodiments, in particular from the field of automotive electronics, namely for the operation of piezoelectric actuators in fuel injectors. Due to the high demands placed there in terms of a rapid, exact and reproducible opening and closing of fuel injection valves, however, the known circuit arrangements are designed relatively complex.

So revealed the DE 101 47 168 A1 a converter circuit with a storage choke, which is connected upstream of a primary storage capacity and a secondary storage capacity, in particular a piezoelectric actuator, downstream. By actuating a primary switching element and a secondary switching element, energy can be transferred from the primary storage capacity to the secondary storage capacity and recovered.

The EP 1 398 489 A1 discloses a primary clocked flyback converter circuit.

Also the DE 199 44 733 A1 and the DE 101 13 801 A1 disclose primary and secondary clocked flyback converter circuits, these flyback converter circuits on the primary side, a capacitor is connected in parallel to recover energy during discharge of a load-side piezoelectric actuator can.

In all these converter circuits, the load-side piezoelectric actuator is discharged via the secondary-side choke coil.

It is therefore an object of the present invention to provide a simple circuit arrangement for charging and controlled discharging of a capacitive load.

This object is achieved according to the invention by a circuit arrangement according to claim 1 or 3. The dependent claims relate to advantageous developments of the invention.

• – einen ersten Versorgungsanschluss und einen zweiten Versorgungsanschluss zum Anlegen eines ersten Versorgungspotentials bzw. eines zweiten Versorgungspotentials,
• – einen ersten Ausgangsanschluss und einen zweiten Ausgangsanschluss zum Anschluss der Last, wobei der erste Ausgangsanschluss mit dem ersten Versorgungsanschluss verbunden ist,
• – einen zwischen einem ersten Schaltungsknoten und einem zweiten Schaltungsknoten angeordneten Kondensator,
• – eine zwischen dem zweiten Versorgungsanschluss und dem ersten Schaltungsknoten angeordnete erste Induktivität,
• – einen zwischen dem ersten Schaltungsknoten und dem ersten Versorgungsanschluss angeordneten ersten ansteuerbaren Schalter,
• – eine zwischen dem zweiten Schaltungsknoten und dem ersten Versorgungsanschluss angeordnete zweite Induktivität,
• – einen zwischen dem zweiten Schaltungsknoten und dem zweiten Ausgangsanschluss angeordneten zweiten ansteuerbaren Schalter,
• – eine Steuereinrichtung zur Bereitstellung von Steuersignalen zur Ansteuerung der beiden Schalter, und
• – einen zwischen dem zweiten Ausgangsanschluss und dem ersten Ausgangsanschluss angeordneten Transistor und Mittel zur geregelten Einstellung eines über den Transistor fließenden Stromes.

According to a first aspect of the invention, the circuit arrangement comprises:

• A first supply connection and a second supply connection for applying a first supply potential or a second supply potential,
• A first output terminal and a second output terminal for connection of the load, wherein the first output terminal is connected to the first supply terminal,
• A capacitor arranged between a first circuit node and a second circuit node,
• A first inductor disposed between the second supply terminal and the first circuit node,
• A first controllable switch disposed between the first circuit node and the first supply terminal,
• A second inductor disposed between the second circuit node and the first supply terminal,
• A second controllable switch disposed between the second circuit node and the second output terminal,
• - A control device for providing control signals for controlling the two switches, and
• A transistor arranged between the second output terminal and the first output terminal and means for controlled adjustment of a current flowing through the transistor.

In a development of the first aspect of the invention, the two inductances are inductively coupled, that is, for example, formed as coils wound on a common core.

• – einen ersten Versorgungsanschluss und einen zweiten Versorgungsanschluss zum Anlegen eines ersten Versorgungspotentials bzw. eines zweiten Versorgungspotentials,
• – einen ersten Ausgangsanschluss und einen zweiten Ausgangsanschluss zum Anschluss der Last, wobei der erste Ausgangsanschluss mit dem ersten Versorgungsanschluss verbunden ist,
• – eine zwischen dem ersten Versorgungsanschluss und dem zweiten Versorgungsanschluss angeordnete Reihenschaltung aus einer ersten Induktivität und einem ersten ansteuerbaren Schalter,
• – eine induktiv mit der ersten Induktivität gekoppelte zweite Induktivität, die einerseits mit dem ersten Versorgungsanschluss und andererseits über einen zweiten ansteuerbaren Schalter mit dem zweiten Ausgangsanschluss verbunden ist,
• – eine Steuereinrichtung zur Bereitstellung von Steuersignalen zur Ansteuerung der beiden Schalter, und
• – einen zwischen dem zweiten Ausgangsanschluss und dem ersten Ausgangsanschluss angeordneten Transistor und Mittel zur geregelten Einstellung eines über den Transistor fließenden Stromes.

According to a second aspect of the invention, the circuit arrangement comprises:

• A first supply connection and a second supply connection for applying a first supply potential or a second supply potential,
• A first output terminal and a second output terminal for connection of the load, wherein the first output terminal is connected to the first supply terminal,
• A series circuit, which is arranged between the first supply connection and the second supply connection, and comprises a first inductance and a first controllable switch,
• A second inductance which is inductively coupled to the first inductance and which is connected to the first supply terminal on the one hand and to the second output terminal via a second controllable switch on the other hand,
• - A control device for providing control signals for controlling the two switches, and
• A transistor arranged between the second output terminal and the first output terminal and means for controlled adjustment of a current flowing through the transistor.

In a further development, the circuit arrangement according to the second aspect of the invention further comprises a capacitor arranged between the first supply terminal and the second supply terminal.

The circuit arrangement according to the invention can be realized with relatively few components and thus very simple and allows by appropriate control of the two switches charging and discharging the capacitive load with in principle arbitrary temporal courses of a corresponding load current.

In addition, this circuit concept has a number of further advantages, especially when used to drive a piezoelectric actuator (eg in a proportional valve).

Well suited to the invention z. B. for controlling a (relative to fuel injectors) "relatively slow" actuator in an adjustable fluid valve (eg., Proportional valve), for example, in a provided as a pressure reducer gas valve. A piezobetätigtes adjustable gas valve can, for. Example, as a pressure reducer between a fuel gas reservoir area and a fuel gas inlet portion of a gas-fueled internal combustion engine (gas engine) are used. With the circuit arrangement according to the invention, temporal change rates of the output voltage (load voltage) can be achieved, which are completely sufficient for driving such a pressure reducing valve (typically in the ms range).

In addition, the circuit arrangement according to the invention makes it possible to generate from a relatively low supply voltage (= difference between the two supply potentials) a higher voltage required for the deflection of a piezoactuator. Accordingly, the output-side voltage swing is advantageously very large (because the output voltage can also be reduced to 0 V).

Furthermore, the circuit arrangement can be used to hold a constant output voltage in a simple manner over a longer period of time (for example, it can be adjusted to a setpoint value). B. for the above-mentioned application in a piezo-driven pressure reducer often occurs in practice.

Despite the extremely simple construction of the circuit arrangement, the power loss during operation can be kept relatively low. It is also possible to recover the electrical energy stored in the capacitive load when the load is unloaded, thus enabling low-loss work in dynamic operating phase stop start.

In one embodiment, the two supply potentials are provided by a battery, for example by a battery provided in a motor vehicle for the supply of an electrical vehicle electrical system. In this case, the circuit arrangement z. B. for operating a piezoelectric actuator in the region of a drive of the motor vehicle may be provided (eg., To operate a proportional valve).

In one embodiment, it is provided that the circuit components are designed such that an output voltage exceeding the supply voltage can be achieved. Such an up-conversion of the supply voltage to the output voltage is z. As in an automotive application particularly interesting, such as when it comes to drive from an electrical system with relatively low voltage (eg., In the range of 12 V to 16 V), a piezoelectric actuator, which typically for full deflection relatively high voltages requires (eg more than 50 V, in particular more than 100 V).

The first controllable switch and / or the second controllable switch can be designed in a simple manner as a transistor, in particular a field effect transistor (FET). If a bipolar transistor is used, an insulated gate bipolar transistor ("IGBT") is preferred in view of low electrical losses.

With regard to the most accurate possible adjustment of the output voltage, it is advantageous if means for measuring the current flowing through the first switch and / or means for measuring the current flowing through the load are provided. Such a current measuring means can, for. B. include a shunt resistor, which is arranged in the corresponding current path and whose voltage drop is detected as representative of the flowing current measured variable from an evaluation unit. In particular, the evaluation unit may be part of the control device provided anyway for providing the control signals for the two switches.

The invention will be further described by means of an embodiment with reference to the accompanying drawings. They show:

1 a circuit diagram of a circuit arrangement for operating a piezoelectric actuator according to a first embodiment, and

2 a circuit diagram of a circuit arrangement for operating a piezoelectric actuator according to another embodiment.

1 shows a circuit arrangement 10 (Output stage) for operating a capacitive load in the form of a piezoelectric actuator P.

The circuit arrangement 10 includes supply terminals E1 and E2 for applying supply potentials GND and VBAT, here z. B. be provided from a motor vehicle battery.

The supply voltage (difference between VBAT and GND) is z. B. 12 V. On the output side, between output terminals A1 and A2, an output voltage (load voltage) for the piezoelectric actuator P can be adjusted during operation, the z. B. in a range of 0 V to 200 V is variable.

The piezoelectric actuator P is used for. B. for actuating a pressure reducer at an inlet region of a gas engine of the motor vehicle.

• – einen zwischen einem ersten Schaltungsknoten K1 und einem zweiten Schaltungsknoten K2 angeordneten Kondensator C,
• – eine zwischen dem zweiten Versorgungsanschluss E2 und dem ersten Schaltungsknoten K1 angeordnete erste Induktivität L1,
• – einen zwischen dem ersten Schaltungsknoten K1 und dem ersten Versorgungsanschluss E1 angeordneten Schalttransistor Q1,
• – eine zwischen dem zweiten Schaltungsknoten K2 und dem ersten Versorgungsanschluss E1 angeordnete zweite Induktivität L2,
• – einen zwischen dem zweiten Schaltungsknoten K2 und dem zweiten Ausgangsanschluss A2 angeordneten zweiten Schalttransistor Q2, und
• – eine Steuereinrichtung ST zur Bereitstellung von Steuersignalen q1 und q2 zur Ansteuerung der beiden Transistoren Q1 und Q2. Die Einrichtung ST bewirkt diese Ansteuerung auf Basis eines zugeführten Vorgabesignals S (welches z. B. von einer programmgesteuerten Rechnereinrichtung (z. B. Mikrocontroller) erzeugt wird).

The circuit arrangement 10 further includes

• A capacitor C arranged between a first circuit node K1 and a second circuit node K2,
• A first inductance L1 arranged between the second supply terminal E2 and the first circuit node K1,
• A switching transistor Q1 arranged between the first circuit node K1 and the first supply terminal E1,
• A second inductance L2 arranged between the second circuit node K2 and the first supply terminal E1,
• A second switching transistor Q2 arranged between the second circuit node K2 and the second output terminal A2, and
• A control device ST for providing control signals q1 and q2 for driving the two transistors Q1 and Q2. The device ST effects this activation on the basis of a supplied default signal S (which is generated, for example, by a program-controlled computer device (eg microcontroller)).

In the illustrated embodiment, the first transistor Q1, a current measuring resistor Rs1 is connected in series, the voltage drop Us1 is representative of the current flowing through Q1 current. The measured quantity Us1 is supplied to the control device ST for improving the control accuracy.

In addition, in the illustrated example, a voltage drop Us2 is taken into account in the control, which drops at a second current measuring resistor Rs2, which is arranged in the connection path between the first supply terminal E1 and the first output terminal A1. Us2 is thus representative of the current flowing through the piezoelectric actuator P.

In accordance with a simple mode of operation of the circuit arrangement 10 it is provided that a charging of the piezoelectric actuator P by a clocked operation of the first transistor Q1 takes place, whereas a discharging of the load P by a clocked operation of the second transistor Q2 takes place.

With regard to the charging process, it should be noted that the circuit arrangement 10 essentially like a so-called SEPIC (Single Ended Primary Inductance Converter) converter. The clocked charge can be described as follows:
If, at the beginning of the circuit operation, both transistors Q1 and Q2 are off, then a charging voltage is established at the capacitor C which corresponds to the supply voltage. At node K1 there is the potential VBAT and at node K2 the potential GND prevails.

Now, when Q1 is turned on, the potential at node K1 abruptly reduces to GND. This has the consequence that a gradually increasing current of E2 flows through the first inductance L1 (choke) and further via Q1 to E1, and that the potential at the node K2 abruptly drops to a value of -VBAT, that is below the potential GND. The latter has the consequence that also a gradually increasing current flows through the second inductance L2 (second choke) from E1 to the node K2. In the example shown, the inductances L1 and L2 are the same size.

After a certain time, the potential at the node K2 will again rise to approximately the value GND, at which moment comparatively large currents flow through both inductances L1 and L2.

If Q1 is switched off again at this moment, the current which continues to flow through L1 leads to an increase in the potential prevailing at node K1. Furthermore, there is an increase in the prevailing at the node K2 potential (far beyond the value of VBAT addition) and it flows a load current from K2 via the intrinsic source-drain diode (not shown) of the transistor Q2 and the output terminal A2 to the piezoelectric actuator P. In this phase, the output voltage is increased and the piezoelectric actuator P thus charged.

Thus, by repetitively turning on and off Q1, the piezo actuator P can be charged to a desired extent or a desired output voltage (load voltage) can be set.

In the illustrated embodiment, in which the second switch Q2 is used as a field-effect transistor with the "intrinsic source-drain diode" polarized in the described manner, switching on of Q2 in the charging phase is unnecessary. If, unlike the illustrated embodiment, a controllable switch without such an intrinsic or parallel to the switch diode is used at this point, the second switch Q2 must be turned on accordingly in the charging phase.

In a development of the described control of the transistors Q1 and Q2, the transistor Q2 is actively turned on during the charging phase in order to reduce the flow resistance and thus the losses in each charging phase.

In order to keep the output voltage between the output terminals A1 and A2 constant and thus keep the charge stored in the piezo actuator P constant, both switches Q1 and Q2 are simply turned off (opened). To a gradual unwanted discharge z. B. to compensate for leakage currents, the output voltage can be monitored and adjusted based on the monitoring.

In order to reduce the output voltage again and thus to discharge the piezoelectric actuator P, the transistor Q2 is switched on permanently or clocked. In this way, a desired temporal discharge curve can be accomplished.

With a view to the most accurate possible control of the two switches Q1 and Q2 for the most precise setting of the output voltage, it is advantageous to use the above-mentioned current measurement signals Us1 and Us2 in the determination of the switching times by the control device ST.

Alternatively or additionally, it is possible to detect other measurement signals in the region of the illustrated circuit for the determination of optimized switching times. In this regard, z. B. the detection of the output voltage in many cases advantageous, such as to realize a control loop, by which the output voltage is set to a desired value.

In the following description of a further embodiment, the same reference numerals are used for equivalent circuit components. In this case, essentially only the differences from the exemplary embodiment already described will be discussed and, moreover, reference is hereby explicitly made to the description of the preceding exemplary embodiment.

2 shows a circuit arrangement 10a (Power amplifier) for operating a piezoelectric actuator P.

• – einen ersten Versorgungsanschluss E1 und einen zweiten Versorgungsanschluss E2 zum Anlegen eines ersten Versorgungspotentials GND bzw. eines zweiten Versorgungspotentials VBAT,
• – einen ersten Ausgangsanschluss A1 und einen zweiten Ausgangsanschluss A2 zum Anschluss der Last P, wobei der erste Ausgangsanschluss A1 mit dem ersten Versorgungsanschluss E1 verbunden ist,
• – eine zwischen dem ersten Versorgungsanschluss E1 und dem zweiten Versorgungsanschluss E2 angeordnete Reihenschaltung aus einer ersten Induktivität L1 und einem ersten Schalttransistor Q1,
• – eine induktiv mit der ersten Induktivität L1 gekoppelte zweite Induktivität L2, die einerseits mit dem ersten Versorgungsanschluss E1 und andererseits über einen zweiten Schalttransistor Q2 mit dem zweiten Ausgangsanschluss A2 verbunden ist, wobei die beiden Induktivitäten einen Transformator bilden, und
• – eine Steuereinrichtung ST zur Bereitstellung von Steuersignalen q1, q2 zur Ansteuerung der beiden Schalter Q1, Q2. Die Einrichtung ST bewirkt diese Ansteuerung auf Basis eines Vorgabesignals S (wie oben für das Beispiel gemäß 1 bereits beschrieben).

The circuit arrangement 10a includes

• A first supply connection E1 and a second supply connection E2 for applying a first supply potential GND or a second supply potential VBAT,
• A first output terminal A1 and a second output terminal A2 for connecting the load P, the first output terminal A1 being connected to the first supply terminal E1,
• A series arrangement of a first inductance L1 and a first switching transistor Q1 arranged between the first supply terminal E1 and the second supply terminal E2,
• A second inductance L 2 inductively coupled to the first inductance L 1, which is connected to the first supply terminal E 1 on the one hand and to the second output terminal A 2 via a second switching transistor Q 2, the two inductances forming a transformer, and
• - A control device ST for providing control signals q1, q2 for controlling the two switches Q1, Q2. The device ST effects this activation on the basis of a default signal S (as described above for the example according to FIG 1 already described).

For measuring currents flowing through the first transistor Q1 and through the piezoelectric actuator P, current measuring resistors Rs1 and Rs2 are provided.

In accordance with a simple mode of operation of the circuit arrangement 10a is provided that a charging of the piezoelectric actuator P by a clocked operation of the first transistor Q1 and the second transistor Q2 takes place, whereas a discharge of the load P z. B. by means of the second transistor Q2, the z. B. clocked or can be operated permanently.

With regard to the charging process, it should be noted that the circuit arrangement 10a essentially like a so-called flyback converter works.

To buffer the supply voltage VBAT-GND, a capacitor C is provided in the illustrated example, which is arranged between the two supply terminals E1 and E2.

The clocked charge of the piezoelectric actuator P can be described as follows:
If, at the beginning of the circuit operation, the transistor Q1 is turned off, a charging voltage is established at Capacitor C on, which corresponds to the supply voltage. The capacitor C is dimensioned here such that its charging voltage remains essentially constant in circuit operation.

Now, when Q1 is turned on, a gradually increasing current flows from E2 via the first inductance L1 (primary side of the transformer) and further via Q1 to E1. The inductively coupled inductor L2 (secondary side of the transformer) is arranged (wound) such that the voltage induced therein attempts to flow a current from A2 via Q2, L to A1. However, such a current flow does not take place, since in this phase by the control device ST, a control signal q2 is output, which causes a blocking of the transistor Q2.

After a certain time, a comparatively large current flows through the inductance L1.

Then, when Q1 is turned off again and the primary current collapses, a relatively large voltage is induced in the second inductor L2, so that a load current of L2 flows through the second transistor Q2 (turned on) and the output terminal A2 to the piezoactuator P. In this phase, the output voltage is increased and the piezoelectric actuator P thus charged.

Thus, by repetitively turning on and off Q1 (and correspondingly synchronizing switching of Q2), the piezo actuator P can be charged to a desired extent or a desired output voltage (load voltage) can be set.

To keep the output voltage between the output terminals A1 and A2 constant and thus keep the charge stored in the piezo actuator P constant, both switches Q1 and Q2 are turned off (opened). To a gradual unwanted discharge z. B. to compensate for leakage currents, the output voltage can be monitored and adjusted based on the monitoring.

In order to reduce the output voltage again and thus to discharge the piezoelectric actuator P, the transistor Q2 is switched on permanently or clocked. In this way, a desired temporal discharge history (and energy recovery into the supply) can be accomplished.

When the two switches Q1 and Q2 are actuated, the current measurement signals Us1 and Us2 already mentioned above are used by the control device ST to determine advantageous switching times.

In the illustrated example, the circuit arrangement further comprises a transistor Q3 arranged between the second output connection A2 and the first output connection A1, by means of which an additionally usable discharge passage is created. As an alternative or in addition to switching on Q2, the discharging process can thus also be initiated by switching on Q3 (eg in order to achieve faster discharging of the piezoactuator P). In the example shown, a shunt resistor Rs3 is connected in series with the transistor, which advantageously limits the maximum discharge current.

A peculiarity of the illustrated, realized by means of Q3 and Rs3 discharge passage is that the driving of the transistor Q3 is accomplished not by directly applying a provided by the device ST control signal q3 to the control input (here: gate) of the transistor Q3, but by means of an operational amplifier OPAMP a discharge current control is realized, in which a voltage value of the control signal q3 is a default for the discharge current to be set. For this purpose, the signal q3 is applied to a non-inverting input of the operational amplifier OPAMP, of which an inverting input is connected to the source terminal of Q3 and an output terminal is connected to the gate terminal of Q3. In addition, the source terminal of Q3 is not connected directly but via the mentioned shunt resistor Rs3 to the connection path from E1 to A1. As a result of these measures, a discharge current flowing through Q3 and Rs3 sets in as a function of the control signal q3.

In the circuit arrangement 10a The voltage dropping at the shunt resistor Rs3 could also be taken into account during the activation (for example as an alternative or in addition to the voltage Us2).

An additional discharge passage (Q3) as above for the circuitry 10a from 2 and their modifications or peculiarities (Rs3, OPAMP, use of the voltage dropping across Rs3) can also be described in the circuit arrangement described above 10 be provided.

In summary, with the described circuit arrangements 10 and 10a each created simple and therefore cost-effective power amplifiers for controlling a piezoelectric actuator. The circuit arrangements are only single-stage and there is no downstream linear regulator required. In principle, any output voltages and input voltages can be set. Due to the capacitive or inductive decoupling between the supply side and the output side, it can be ensured that, in the event of a fault, there is no high current or high voltage at the output. In addition, the energy stored in the load can be at least partially recovered when unloading the load.

Claims (11)

Circuit arrangement for operating a capacitive load (P), comprising - a first supply terminal (E1) and a second supply terminal (E2) for applying a first supply potential (GND) or a second supply potential (VBAT), - a first output terminal (A1) and a second output terminal (A2) for connecting the load (P), the first output terminal (A1) being connected to the first supply terminal (E1), a capacitor arranged between a first circuit node (K1) and a second circuit node (K2) ( C), - a first inductance (L1) arranged between the second supply terminal (E2) and the first circuit node (K1), - a first controllable switch (Q1) arranged between the first circuit node (K1) and the first supply terminal (E1), - A between the second circuit node (K2) and the first supply terminal (E1) arranged second inductance (L2), - ei NEN between the second circuit node (K2) and the second output terminal (A2) arranged second controllable switch (Q2), and - a control device (ST) for providing control signals (q1, q2) for driving the two switches (Q1, Q2), characterized in that the circuit arrangement further comprises a transistor (Q3) arranged between the second output terminal (A2) and the first output terminal (A1) and means (OPAMP, Rs3) for controlled adjustment of a current flowing through the transistor (Q3). Circuit arrangement according to claim 1, wherein the two inductors (L1, L2) are inductively coupled. Circuit arrangement ( 10a ) for operating a capacitive load (P), comprising - a first supply terminal (E1) and a second supply terminal (E2) for applying a first supply potential (GND) or a second supply potential (VBAT), - a first output terminal (A1) and a second output terminal (A2) for connecting the load (P), wherein the first output terminal (A1) is connected to the first supply terminal (E1), - a series circuit arranged between the first supply terminal (E1) and the second supply terminal (E2) a first inductance (L1) and a first controllable switch (Q1), a second inductance (L2) inductively coupled to the first inductance (L1), connected on the one hand to the first supply terminal (E1) and, on the other hand, via a second controllable switch (Q2 ) is connected to the second output terminal (A2), and - a control device (ST) for providing control signals (q1, q2 ) for driving the two switches (Q1, Q2), wherein the circuit arrangement further comprises a transistor (Q3) arranged between the second output terminal (A2) and the first output terminal (A1) and means (OPAMP, Rs3) for controlled setting of a via the transistor (Q3) flowing current. Circuit arrangement according to claim 3, further comprising a capacitor (C) arranged between the first supply terminal (E1) and the second supply terminal (E2). Circuit arrangement according to one of the preceding claims, wherein the two supply potentials (GND, VBAT) are provided by a battery. Circuit arrangement according to one of the preceding claims, wherein the circuit components are designed so that a supply voltage (VBAT-GND) exceeding the output voltage can be achieved. Circuit arrangement according to one of the preceding claims, wherein the first controllable switch (Q1) and / or the second controllable switch (Q2) as a transistor, in particular FET, is formed. Circuit arrangement according to one of the preceding claims, wherein means (Rs1) for measuring the current flowing through the first switch (Q1) and / or means (Rs2) for measuring the current flowing through the load (P) are provided. Circuit arrangement according to one of the preceding claims, wherein the means (OPAMP, Rs3) for current adjustment comprise a shunt resistor (Rs3) connected in series with the transistor (Q3) and an operational amplifier (OPAMP) of which an output is connected to a control input of the transistor (Q3). and an inverting input is connected to a circuit node between transistor (Q3) and shunt resistor (Rs3). Circuit arrangement according to claim 9, wherein the control device (ST) is designed to take into account a voltage drop across the shunt resistor (Rs3) during the activation. Use of a circuit arrangement ( 10 . 10a ) according to one of the preceding claims for driving a piezoelectric actuator.

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