DE102008003385A1 - Flip-flop circuit i.e. latch, for e.g. electronic component, has transmission circuit designed to couple signal and control signal strongly at node and to couple signal weakly at node without control signal or to decouple signal from node - Google Patents

Abstract

The circuit has circuit nodes (140, 190) coupled via a feedback path. A delay circuit is coupled with the node (140) and is designed to produce a signal based on another signal such that change of the latter signal leads to change of the former signal after elapsing of a time interval. A transmission circuit is coupled with the node (190) and is designed to couple the former signal and a control signal strongly at the node (190) and to couple the former signal more weakly at the node (190) without the control signal or to decouple the former signal from the node (190). An independent claim is also included for a method for compensation of interference of the flip-flop circuit.

Description

Technical area

In In many fields of technology, bistable multivibrators are used and circuits based on bistable multivibrators for storing, buffering or buffering individual or several bits used. Bistable flip-flops, the Also referred to as a latch, so for example in the field Computer technology in the context of memories, processors, arithmetic units (ALU = Arithmetic Logic Unit) and other integrated circuits used. Beyond that they will too in the context of frequency dividers, shift registers and a variety used in other circuits where individual bits of information at least temporarily stored.

But Also in other areas of technology are bistable flip-flops for example in the context of switches, frequency dividers, counters and other electrical and electronic components and components used. To name just one example, bistable flip-flops, for example in the context of switches for the suppression of bounce effects or used to measure the holding time of the switch by a user become.

Thereby, that bistable flip-flops or latches for storing at least one bit in many applications often the interest that this information does not occur through disorders falsified or deleted become. disorders can here come from various sources, such as electrical or otherwise physical or chemical noise. disorders can do that for example in the form of fluctuations in the supply voltage, due to radiation or inherent (eg shot noise, thermal noise). Examples for radiation-related Noise sources thus provide light quanta of corresponding frequencies, Neutrons, electrons, positrons or alpha particles from the cosmic rays or other sources. In the field of integrated circuits can for example, radiation already by the so-called Packaging process (housing in solid assemblies or also Encapsulation) used.

Brief description of the figures

embodiments The present invention will be described below with reference to FIGS enclosed drawings closer explained.

1a shows a block diagram of a fuselatch circuit;

1b shows three waveforms of voltage signals during the turn-on of the fuselatch circuit 1a ;

2 shows a block diagram of a bistable flip-flop circuit;

3 shows a block diagram of a flip-flop bistable circuit with a compensation circuit according to an embodiment of the present invention;

4a to 4c show voltage curves at different circuit nodes of the 3 shown circuit in the case of an alpha particle hit;

5a to 5d show different voltage curves at circuit nodes of in 3 shown circuit in the case of another alpha particle hit; and

6 shows a block diagram of another bistable flip-flop circuit with a compensation circuit according to another embodiment of the present invention.

Detailed description the embodiments

Referring to the 1a to 6 In the further course of the present description, a fuselatch circuit will first be described in connection with FIGS 1a . 1b and 2 described before in connection with the 3 to 6 In the present description embodiments of the present invention in the form of bistable flip-flops with compensation circuits will be explained in terms of their structure and operation.

in this connection are used to simplify the description in the further course for objects, Structures, switching elements and other objects the same or similar Reference numeral used when these same or similar functional relationships and Functioning have. Passages of the description referring to similar or relate functionally identical structures, switching elements or other objects, can so between different embodiments of the present invention and other structures and circuits unless explicitly stated otherwise is a shorter one and more concise description of the embodiments of the present invention To enable invention.

In addition, in the context of the before summary description of switching elements, structures and objects that either occur multiple times in one embodiment or occur in similar contexts in several embodiments, unless reference is made to a particular structure of a particular embodiment.

1a shows a circuit diagram of a Fuselatch circuit 100 with a resistance element 110 , this in 1a also referred to its resistance value as R_FUSE. In the resistance element 110 As already indicated by the designation R_FUSE, it may be a fuse-like resistance element, which has, for example, a one-off or one-way closable electrical connection between its terminals. The resistance element 110 For example, it may represent a single metallic or semiconducting connection of a programmable read-only memory (PROM) or related memory technology. In the resistance element 110 Thus, information 1 or 0 can be permanently stored by the resistance element 110 has a low resistance value or a high resistance value. Is it the resistance element 110 that is, a fuse based on a metallic or (optionally doped or highly doped) semiconducting connection between the terminals of the resistor element 110 Thus, the information 1 or 0 may be stored by opening or blowing the fuse (high resistance value) or being closed or not blown (low resistance value).

The resistance element 110 is with a connection to a potential reference potential 120 or to a connection for a reference potential 120 which can be, for example, ground (GND = ground) or else a negative supply voltage (for example, based on another reference potential or a positive supply voltage).

Another connection of the resistor element 110 is connected to a source terminal of an NMOS transistor 130 (TN1) connected to a drain terminal to a first circuit node 140 (N1) is coupled. To a gate terminal of the NMOS transistor 130 can also have an in 1a not shown control circuit, a control signal FPUN are applied.

In 1a are also for the individual field effect transistors, so for example for the NMOS transistor 130 exemplary information regarding the channel width or channel width W and the channel length L specified. The NMOS transistor 130 For example, in the case of 1a represented circuit has a width or width of W = 0.76 microns and a channel length of L = 0.185 microns. If given in a transistor only a single number, this is the channel width W in microns, the channel length L is given in this case by the overall process underlying structure length or structure width, in this context as Standard length or standard channel length is called. In the 1a For example, the circuit shown is based on a 70 nm technology, so that when only a single number is given to a transistor or other structure, the channel length is L = 0.1 μm. For example, in the case of a 70 nm technology, the word line width or the bit line width may be 70 nm.

Of course, the in 1a and the other figures of the present description with respect to channel lengths L and channel widths W are exemplary values only, which are not to be considered as limiting with respect to the specific embodiment. Instead, deviating implementations of channel lengths L and channel widths W can be made. In this context, it should be pointed out that neither the relationships of the two values to each other should be understood as a limiting boundary condition for concrete implementations. Thus, with regard to the concrete dimensioning of the individual components, further parameters play a role, for example the doping, doping profiles, doping depths, oxide thicknesses and other parameters with respect to which no information is reproduced in the figures.

The drain terminal of the NMOS transistor 130 (NMOS = n-channel metal oxide semiconductor = n-channel metal oxide semiconductor) is via the first circuit node 140 (N1) with a drain terminal of a PMOS transistor 140 (PMOS = p-channel metal oxide semiconductor = p-channel metal oxide semiconductor) coupled. The PMOS transistor 150 is with a source connection to a supply voltage or a connection for a supply voltage 160 coupled in 1a Also referred to by their supply voltage value as Vint. The supply voltage Vint may be, for example, a positive supply voltage, which may be, for example, a supply voltage 1a not shown internal stabilization circuit generated and at the terminal 160 provided. The supply voltage Vint can thus be an internal supply voltage derived from an external one.

The PMOS transistor 150 can also over the aforementioned, not in 1a shown, control circuit to be supplied with a further control signal bFPUP, in connection with 1b will be discussed in more detail. The NMOS transistor 130 has a channel width of W = 0.86 microns and a channel length L, which, as previously explained, from the characteristic feature width (standard length or standard channel length) of the production of Fuselatch circuit 100 underlying manufacturing process results. For example, if the bit line width and / or word line width achievable in the production is about 70 nm, the technology is also referred to as 70 nm technology. In this case, the standard length or standard channel length is about 100 nm. Concretely, therefore, the PMOS transistor 150 a channel length of L = 0.1 μm. The channel width is also referred to as the channel width.

Both the NMOS transistor 130 as well as the PMOS transistor 150 are designed in the present example as about the same size transistors. The strength of an NMOS transistor is determined not least by the ratio of the channel width W to the channel length L, so that the NMOS transistor 130 has a thickness of about 4 (= 0.76 μm / 0.185 μm). However, it should be remembered that these "strength indications" tend to be coarser estimates, as they depend on other parameters. However, they represent a good starting point for the underlying circuit design, especially in the field of practice.

Due to the different mobility of electrons in the case of n-channel transistors and of holes in the case of p-channel transistors, an NMOS transistor typically has about twice the strength of a PMOS transistor with identical channel width W and identical channel length L. For this reason, the strength of a PMOS transistor is about half the ratio of the channel width W and the channel length L. Thus, the PMOS transistor also has 150 a thickness of about 4 (= 0.5 x 0.86 μm / 0.1 μm).

The first circuit node 140 who in 1a also referred to as N1 is in parallel with a gate terminal of a PMOS transistor 170 (TP2) and a gate terminal of an NMOS transistor 180 (TN2) coupled. The PMOS transistor 170 is with a source connection also with the supply voltage or a connection 160 coupled for the supply voltage. A drain terminal of the PMOS transistor 170 is via a second circuit node 190 who in 1a also referred to as N2, with a drain terminal of the NMOS transistor 180 which in turn is connected via a source connection to the reference potential potential or a connection 120 coupled to the reference potential. The two transistors 170 . 180 again have an approximately comparable magnitude of about 5, since the PMOS transistor 170 has a channel width of W = 0.69 μm at the standard channel length (about L = 0.1 μm), while the NMOS transistor has a channel width of W = 0.71 μm at a channel length of about L = 0.14 μm. Together, the two transistors form 170 . 180 So a CMOS inverter (CMOS = complementary metal oxide semiconductor = complementary metal oxide semiconductor).

The second circuit node 190 is still with gate electrodes of an NMOS transistor 200. , a PMOS transistor 210 and a PMOS transistor 220 coupled. The source terminals of the two PMOS transistors 210 . 220 are also connected to the supply voltage or its connection 160 coupled. A drain terminal of the PMOS transistor 210 (Channel width W = 0.965 μm, channel length L = 0.4 μm) is the first circuit 140 coupled to which also a drain terminal of the NMOS transistor 200. (Channel width W = 0.8 microns at the standard channel length) is coupled.

The PMOS transistor 220 is with the first circuit node 140 via a PMOS transistor 230 (TP5), wherein a drain terminal of the PMOS transistor 220 with a source terminal of the PMOS transistor 230 connected is. A drain terminal of the PMOS transistor 230 is finally connected to the first circuit node 140 coupled. Both PMOS transistors have a channel width of W = 0.9 μm at the standard channel length. However, while the gate terminal of the PMOS transistor 220 with the second circuit node 190 is a gate terminal of the PMOS transistor 230 also with the control signal FPUN not in 1a coupled control circuit coupled.

The NMOS transistor 200. is connected to a source via an NMOS transistor 240 (TN4) via its drain terminal and source terminal to the reference potential 120 or a connection 120 coupled for the reference potential. The gate terminal of the NMOS transistor 240 is coupled to the further control signal bFPUP the control circuit. Both NMOS transistors 200. . 240 have a channel width of 0.8 μm at the standard channel length.

So while the PMOS transistor 170 and the NMOS transistor 180 form the previously explained CMOS inverter, between the first circuit node 140 and the second circuit node 190 is coupled, form the two transistors 220 and 200. analogous to a CMOS inverter, however, via the two other transistors 230 . 240 from the in 1a not shown control circuit is controllable.

Apart from the additional transistors 210 . 230 and 240 on the one hand to define a defined output state and on the other hand to control the Fuselatch circuit 100 through the in 1a serve not shown control circuit, thus includes the Fuselatch circuit 100 the two circuit nodes 140 (N1) and 190 (N2), on the one hand, has a path connecting the CMOS inverter to the transistors 170 . 180 (TP2, TN2) and also via a feedback path with the CMOS inverter with the two transistors 220 . 200. (TP4, TN3) are coupled together. These two CMOS inverters thus provide together with the two circuit nodes 140 . 190 a bistable flip-flop circuit whose commissioning and operation is to be briefly illuminated below.

After a start-up or a power-up, the supply voltage Vint rises from a time t0 at a voltage value of 0 V to a value of about 1.2 V, as in 1b is illustrated. At a time t1, therefore, the (internal) supply voltage has assumed its stable value of about 1.2 V, while the two control signals bFPUP and FPUN have been assigned by the in 1a not shown control circuit are still on the reference potential (0 V), which corresponds to a logic state 0.

At At this point, it is worth mentioning that embodiments of the present invention, as well as other circuit examples in the context of the present description, not to the example here Voltage values are bound. These are merely to understand and understand by example be replaced by corresponding values in other implementations. So can for example embodiments of the present invention and other circuit examples in the context TTL implementations (TTL = transistor-transistor-logic) or other technologies are implemented. The specified later Voltage values of 1.2 V for the (internal positive) supply voltage Vint and 0 V for the reference potential are therefore to be understood as exemplary only. It can be next to negative also higher (eg TTL technology 5 V) or lower voltage values become.

At time t1, ie immediately after the supply voltage has reached its end value of about 1.2 V during the switch-on process, the two control signals bFPUP and FPUN each have the logic state 0, so that the PMOS transistor 150 (TP1) turned on, so considered as a switch is closed. At the same time is the NMOS transistor 130 (TN1), so that the first circuit node 140 (N1) rises to the supply voltage value Vint. The PMOS transistor 170 (TP2) is thus turned off, that is, when opened as a switch, and the NMOS transistor 180 (TN2) accordingly switched conductive, so closed. The second circuit node 190 (N2) thus falls on the reference potential or the value of the reference potential. With regard to the reference potential, therefore, the second circuit node has 190 a voltage of 0 V, which corresponds to the logic state 0. Due to the described voltage value of the second circuit node 190 (N2) and due to the control signal FPUN are thus the PMOS transistors 210 . 220 . 230 closed (turned on), so that the first circuit node 140 (N1) is also connected via these three transistors to the supply voltage. At the same time, the two NMOS transistors 200. . 240 due to the voltage value of the second circuit node 190 and the control signal bFPUP open (not turned on), so that the first circuit node 140 (N1) via the two NMOS transistor 200. . 240 are separated from the reference potential or the associated connection.

After starting up the supply voltage to the final value Vint of approximately 1.2 V in the case of 1a Thus, this circuit is in an initialized state to an in 1b before t1. The first circuit node 140 (N1) assumes the logic state 1 (voltage value Vint), while the second circuit node 190 (N2) assumes the logic state 0 (voltage value 0 V of the reference potential).

Thus, after the supply voltage Vint has reached its operating or final value of about 1.2 V, the in 1a not shown control circuit, the value of the control signal bFPUP. This goes from the logic state 0 (voltage value of the reference potential 0 V) in the logic state 1 (voltage value Vint), the control signal bFPUP also until the actual power-down of the circuit 100 maintains. The control signals thus reach at in time t2 in 1b shown state that on the one hand the supply voltage has reached its final value, the control signal bFPUP has also assumed the voltage value Vint, while on the other hand, the control signal FPUN has the logic state 0 (voltage value 0 V of the reference potential).

This will cause the fuselatch circuit 100 as they are in 1a is shown in the state of a bistable Kippstu fenschaltungen brought, since on the one hand, the PMOS transistor 150 now locks, so (considered as a switch) is opened and on the other hand, the NMOS transistor 240 is turned on, so (considered as a switch) is closed. Thus, on the one hand, the first circuit node 140 over the two transistors 130 . 150 from the supply voltage 160 , the reference potential 120 and the resistance element 110 while, in particular, the two "strong" transistors 230 . 240 switch through and so the CMOS inverter with the transistors 200. . 220 activate.

Thus, the fuselatch circuit is in the state of a flip-flop bistable circuit, in which due to the previous initialization of the first circuit node 140 (N1) the logic state 1 and the second circuit node 190 (N2) has assumed the logical state 0. This locks the transistors 170 and 200. while the transistors 180 . 220 and also the transistor 210 are switched on. For the sake of completeness it should be mentioned at this point that in the inverted state (N1 = 0, N2 = 1) the transistors 180 . 220 and 210 lock while the two transistors 170 . 200. are switched on. This state is also stable, that is, the second of the two bistable states of the circuit 100 represents.

Shortly after the control signal bFPUP has gone to the voltage value Vint, the in 1a not shown control circuit and the second control signal FPUN for a certain, with respect to a typical duty cycle time to the voltage value Vint, ie in the logic state 1. While the control signal FPUN is at the voltage value Vint, so for example to the in 1b shown time t3, the transistor 130 turned on, so (considered as a switch) is closed. Because at the same time the PMOS transistor 150 is disabled in the logic state 1 and the first circuit node due to the control with the control signal bFPUP 140 (N1) is present in the logic state 1 due to the initialization, the potential Vint of the first circuit node lies 140 via the through-connected NMOS transistor 130 at the resistance element 110 at. At the same time, the control signal FPUN, which is at logic state 1, causes the PMOS transistor 230 locked, so (considered as switch) opened, so that the first circuit node 140 (N1) at least not over the PMOS transistor 220 and the connection 160 for the supply voltage can be pulled up to the voltage value Vint of the supply voltage.

Further, due to the initialization state of the fuselatch circuit 100 the second circuit node 190 (N2) is in the logic state 0, the comparatively weakly dimensioned (channel width 0.965 μm, channel length 0.4 μm) is PMOS transistor 210 switched on. In this way, therefore, a voltage divider between the connection for the supply voltage 160 and to the resistance element 110 connected connection 120 for the reference potential, in which the switched-through PMOS transistor 210 in series with the resistor element 110 lies, wherein the first circuit node 140 (N1) lies just between these two switching elements.

As a result, it depends on the state of the resistance element 110 whether the first circuit node 140 (N1) remains at the voltage value Vint corresponding to the logic state 1 or the voltage value of the first circuit node 140 (N1) decreases so far that the voltage value of the first circuit node 140 is interpreted as a logic state 0, so that a bistable flip-flop corresponding switching elements of the fuse latch circuit 100 tilt.

So if the resistance element 110 (for example, the fuse element (fuse, fuse) 110 ), this in 1a Also referred to as R_FUSE has been separated, is its associated resistance value relative to a Einschaltwiderstandswert the PMOS transistor 210 very large, so that in comparison to this Einschaltwiderstandswert the total resistance by the resistance element 110 is dominated. In this case, therefore, the first circuit node remains 140 in the logic state 1. In other words, this means that the first circuit node 140 (Node 140 (N1)) not via the NMOS transistor 130 to the reference potential, so 0 V, can be brought. The bistable flip-flop circuit thus remains in the state that the first circuit node 140 (N1) on the voltage value Vint and the second circuit node 190 (N2) remains at 0V.

Became the resistance element 110 or the fuse 110 not separated, is the resistance value R_FUSE of the resistive element 110 opposite the on-resistance of the PMOS transistor 210 small, leaving the first circuit node 140 (N1) via the NMOS transistor 130 is brought to the reference potential (0 V) while the control signal FPUN is at the voltage value Vint. In this case, the second circuit node goes 190 (N2) due to the CMOS inverter with the transistors 170 . 180 to the voltage value Vint (logic state 1).

For completeness, it should be mentioned at this point that in the state not reached by the initialization, the first circuit node 140 (N1) is in the logic state 0, the circuit is stable at the time t3, since in this case the first circuit node 140 anyway on the reference potential, so this does not have the NMOS transistor 130 and the resistance element 110 regardless of its resistance value can be discharged. In other words, in this case, the ratio of the resistance values R_FUSE of the resistive element 110 and the on-resistance of the PMOS transistor 210 irrelevant, since the circuit is also stable in this case. However, this also means that a period of time during which the control circuit, which in 1a not shown, the control signal FPUN can leave in the logic state 1, is not critical at least with respect to an upper bound, as long as this period of time is only sufficiently long, if necessary, the first circuit node 140 (N1) over the transistor 130 and the resistance element 110 to unload. This generally depends on sizing and other parameters.

As already indicated, the brings in 1a not shown control circuit, the control signal FPUN back to the state of logic 0, so that the voltage value of the control signal FPUN goes back to 0V. This state of the control signal FPUN (voltage value 0 V), for example, to an in 1b is present until the next start or the next start-up of the fuselatch circuit (power-up) and the subsequent shutdown (power-down) is maintained and the fuselatch circuit is again in the state of a bistable flip-flop circuit. This means that the nodes 140 (N1) and 190 (N2) keep their respective voltage values just as long in principle.

bistable Flip-flop circuits, also referred to as latches or flip-flops are used in many areas of technology. One frequent Field of application is at least temporary caching of single bits (with two states) of information. This can be done for example in the context of counter circuits, where the meter reading in a corresponding register with flip-flops bistable circuits is stored. Also in frequency dividers are corresponding bistable Toggle circuits used. In addition, latches are also in the context of SRAM memories (SRAM = static random access memory = static random access memory), such as those in the Range of cache memories.

But also in DRAN memories (DRAN = dynamically random access memory = dynamic random access memory) and DRAN derivatives are bistable flip-flops, for example, in the context used by Fuselatch circuits. In DRAN stores and DRAN derivatives are common in the row and row redundancy circuits (row and column redundancy circuits) many thousands of fuselatch circuits integrated. These fuselatch circuits, but also others bistable Flip-flops, must a certain strength or resistance to the Influence external disturbance to a change the bits of information stored in them as possible unlikely to make. disorders can for example, in the context of noise effects, which may be physical can (eg shot noise or thermal noise) due to fluctuations of supply voltages or other signals or by physical and other chemical influences. For example, can It may be advisable to fuselatch circuits with a certain strength to provide against alpha and neutron radiation, for example come from the cosmic radiation. But also from other sources can corresponding physical influences come. For example, alpha particles and neutrons also from the potting compound of memory modules be emitted to the circuits. In addition, also can disorders by high-energy photons (X-ray quanta and gamma quanta) or other physical and / or chemical influences become.

in the Trap of such disturbances, can Electron-hole pairs are generated in the area of the circuit, the the bistable flip-flop circuit influence so that they their State changes. In other words, you can for example, in the case of an alpha or neutron radiation strike Electron-hole pairs in the substrate or other parts of the circuit in question be generated, the bistable flip-flop or the latch as possible should not tip over.

To explain this in more detail, is in 2 in the 1a shown circuit in a simplified form, wherein in the latch circuit in 2 in particular those for the tax possibilities by the in 1a not shown control circuit used components have been reproduced for simplicity of illustration.

2 shows such a latch 100 ' , which is the Fuselatch circuit 100 out 1a essentially corresponds to the actual latch components. To emphasize this similarity are in 2 for the functionally identical or functionally similar components, the same reference numerals and the same designations have been used. The latch 100 ' out 2 thus differs from the Fuselatch circuit 100 out 1a First of all in that the transistors 150 . 130 and the resistance element 110 with the associated connections for the supply voltage 160 and the reference potential 120 absence. Likewise, the to Control of the Fuselatch circuit 100 implemented transistors 230 . 240 as well as the additional transistor 210 in the context of reading the resistance value of the resistive element 110 is used as a resistive element in the previously described voltage divider, not implemented or not shown. This results in the in 2 simplified representation of the latches 100 ' ,

The latch 100 ' thus in turn comprises a series connection of the PMOS transistor 170 (TP2) and the NMOS transistor 180 (TN2), which is between a connection for the supply voltage 160 with the voltage value Vint and a connection 120 are switched for the reference potential (voltage value 0 V). Here is the PMOS transistor 170 again with a source connection to the supply voltage 160 and the NMOS transistor 180 with a source connection to the connector 120 connected to the reference potential (0 V). Both transistors are via their respective drain terminals to the second circuit node 190 (N2) connected.

The second circuit node 190 (N2) is with two gate terminals of the two transistors 200. . 220 connected. The transistor 220 is in turn a PMOS transistor (TP4), which has a source connection to the connection for the supply voltage 160 is coupled. Accordingly, a source terminal of the NMOS transistor is also 200. (TN3) with a connection 120 coupled for the reference potential. The two drain terminals of the two transistors 200. . 220 are with the first circuit node 140 (N1) connected in turn to the gate terminals of the two transistors 170 . 180 connected is.

2 Thus, FIG. 2 essentially shows the two CMOS inverters in their feedback circuit configuration. The first CMOS inverter in this case comprises the PMOS transistor 170 (TP2) and the NMOS transistor 180 (TN2) while the second CMOS inverter is the NMOS transistor 200. (TN3) and the PMOS transistor 220 (TP4). As a result, as already stated in 1a Again, the two circuit nodes 140 . 190 (N1, N2) are coupled together via a coupling path comprising one of the two CMOS inverters and a feedback path comprising the other CMOS inverter. The first circuit node 140 (N1) is thus, for example, with the second circuit node 190 (N2) via the coupling path with the inverter with the two transistors 170 . 180 coupled. Accordingly, via the parallel feedback path with the CMOS inverter with the two transistors 200. . 220 the second circuit node 190 with the first circuit node 140 coupled.

However, the electron-hole pairs generated by an alpha or neutron beam hit can cause the latch 100 ' out 2 let tilt. That is, the circuit nodes 140 (N1) and 190 (N2) can take a wrong voltage value due to an alpha or neutron beam hit.

To illustrate this, here are a few remarks on the stability of the circuit 2 made. Save that in 2 shown latch 100 ' for example, in the node 190 (N2) a logic state 0 (voltage value 0 V) and in the circuit node 140 (N1) a logical 1 (voltage value Vint = 1.2 V), for example, by an alpha or neutron beam hit a positive charge quantity Q on the node 190 (N2). This creates the risk that the second circuit node 190 (N2) rises above about 0.6 V, thereby increasing the NMOS transistor 200. (TN3) could be turned on, so that the first circuit node 140 (N1) is discharged and brought to a voltage value of less than about 0.6V. This would make the latch 100 ' tilt, so that at the second circuit node 190 (N2) the voltage value rises to about 1.2 V and at the first circuit node 140 (N1) the voltage drops to about 0V.

In this situation would be the latch circuit 100 ' the more stable the lower the NMOS transistor 180 (TN2) is in the on state, as this allows the charge Q to be derived more quickly from the reference potential (eg ground, GND) and the higher the impedance of the NMOS transistor 200. (TN3) is. This would result in a reloading of a capacitance value or a capacitance associated with the first circuit node 140 (N1) is associated, enlarged or extended.

However, since an alpha or neutron beam hit also has a positive charge amount Q on the node 140 (N1), it follows that the latch 100 ' out 2 In principle, it can not be made more resistant to alpha or neutron beam hits by a simple dimensioning of the transistors involved. In such a case, just the roles of the two transistors would be 180 . 200. with respect to the to be increased or decreased Einschaltwiderstandswert reversed. An improvement in alpha or neutron beam hit resistance could only be achieved by having the capacitances or capacitance values associated with the two circuit nodes 140 . 190 (N1, N2) were sufficiently enlarged, which, however, could lead to a significant increase in a required chip area on the one hand and on the other hand to a reduction of possible switching times (due to the resulting low-pass filter characteristics).

The previous explanations with regard to the latch circuit 100 ' out 2 can be adjusted accordingly to the Fuselatch circuit 100 out 1a transfer. Thus, an alpha or neutron beam resistance improved accordingly only by dimensioning of the transistors used is hardly feasible in this case as well. Also, the previous problems with the increase of capacitance values or capacities of the two circuit nodes 140 . 190 to achieve at least some strength against alpha or neutron radiation would result in similar effects. An increase in the capacities or capacitance values of the two circuit nodes 140 . 190 could thus lead to an increase in the required size of the structures in question, so that especially for highly integrated components, a relatively large chip area should be used to achieve a corresponding effectiveness.

The problem that the capacitances of the circuit nodes 140 . 190 (N1, N2) should be or should have a certain size, thereby increasing consumption of the chip area, especially with fuselatch circuits with each new generation of memory chips (eg DRAM memory chips), as with every new generation the increasing integration density (shrink) this chip surface consumption would continue to increase.

It There is thus a need, an improvement in area efficiency and / or the stability improvement across from external interference to achieve bistable flip-flops. For example, there is a need for Fuselatch circuits for DRAM memory chips or Memory circuits and DRAM derivatives (eg memory for graphics systems or graphics subsystems (graphics chips)) improvement by reduction in area and / or an increase in stability against To achieve alpha and neutron radiation.

Embodiments of the present invention are thus based on the finding that a space-saving improvement in the stability against interference can be achieved by implementing an active compensation of a disturbance in a bistable flip-flop circuit. The stability of a bistable flip-flop circuit (latch), for example, against alpha or neutron radiation can be achieved to save space by detecting a change and generating a corresponding control signal within a first period, while possibly a change occurred is delayed at least so far that only after a lapse of a second time period, which is longer than the first time period, leads to a change of a signal which is coupled into the bistable stage circuit more strongly in response to the control signal. If there is no control signal, the relevant signal is weaker injected into the bistable multivibrator or completely decoupled. In some embodiments of the present invention, the supply potential or the supply voltage or the reference potential is thus coupled into the bistable flip-flop circuit in dependence on the delayed signal with a coupling strength dependent on the control signal. By using an active compensation circuit, for example, capacitances or capacitance values of the circuit points can be achieved 140 . 190 (N1, N2) in a Fuselatch circuit, as in the 1a and 2 shown are reduced (saved).

3 shows a bistable flip-flop circuit 300 according to an embodiment of the present invention. The bistable flip-flop circuit 300 includes a fuse latch circuit 100 as related to 1a already structurally described and explained. Unlike the in 1a shown Fuselatch circuit 100 However, at the in 3 shown circuit, some transistors dimensioned differently. So points the PMOS transistor 170 (TP2) now has a channel width of W = 0.28 μm at the standard channel length of L = 0.1 μm. The NMOS transistor 180 (TN2) now has a channel length of 0.28 μm and a channel length of 0.14 μm. The PMOS transistor 210 has a channel width of 0.3 μm and a channel length of 0.12 μm. The PMOS transistors 220 and 230 (TP4 and TP5) now have channel widths of 0.3 microns in the standard channel length. The NMOS transistors 200. . 240 (TN3, TN4) now have channel widths of 0.3 .mu.m each at the standard channel length.

For further structural description and operation of the Fuselatch circuit 100 will continue to be related to the description 1a directed.

The bistable flip-flop circuit 300 now also has one to the coupling path and the feedback path to the first node 140 (N1) and the second circuit node 190 (N2) parallel compensation circuit 310 on. The compensation circuit 310 in this case comprises a first inverter 320 who in 3 also referred to as InvA and having an input to the first circuit node 140 (N1) is coupled. The first inverter 320 serves inter alia as a driver stage for decoupling the first circuit node 140 (N1) of the other components of the compensation circuit 310 which, however, can in principle also be omitted. At the in 3 In the embodiment shown according to the present invention, the first inverter is used 320 a CMOS inverter comprising at least one NMOS transistor and a PMOS transistor, however, for simplicity of illustration in FIG 3 are not shown individually. The NMOS transistor of the first inverter 320 has a channel width of 0.7 μm, while the PMOS transistor of the first inverter 320 has a channel width of 0.28 microns. Both transistors of the inverter 320 in this case have as the respective channel lengths the standard channel length of L = 0.1 μm determined by the production process. As the specified channel widths already show, the in 3 shown embodiment of the present invention, the first inverter 320 a comparatively strong driver stage for the other circuit components of the compensation circuit 310 represents.

at Inverters are thus basically at least in the illustrations in the figures of the present Describes the channel widths of the NMOS transistors used and the PMOS transistors used, where the upper number the width of the NMOS transistor and the lower number the width of the NMOS transistor PMOS transistor reproduces. If four digits are given, refer to the additional ones in each case above or below a slash indicated values the corresponding channel lengths of the two implemented transistors. In this context should be reiterated that in the figures dimensions given in the present description by way of example and that the concrete dimensions of the implementations and the fields of application of the embodiments of the present invention Depend on invention as previously explained has been.

An output of the first inverter 320 is connected to a first terminal of a change detection circuit 330 and with an input of a delay circuit 340 coupled. A transmission circuit 350 is via a first input to an output of the delay circuit 340 and via a second input to a second terminal of the change detection circuit 330 coupled. The transmission circuit 350 is also connected to the second circuit node via a third connection 190 the fuselatch circuit 100 (bistable multivibrator) connected.

About the first inverter 320 as the driver circuit are thus the change detection circuit 330 and the delay circuit 340 with the first circuit node 140 (N1) coupled. In the context of the present description, two components which are coupled to one another are understood to mean those which are connected to each other either directly or indirectly. So for example is the change detection circuit 330 indirectly with the first circuit node 140 namely via the first inverter 320 coupled.

The change detection circuit 330 is now adapted to respond to a change in the state or signal at the first circuit node 140 to provide, within a first time period, at the second port, a control signal that is just indicating an occurrence of the change in the state of the first circuit node (first signal). The delay circuit 340 also connected to the first circuit node 140 via the first inverter acting as the driver 320 is now configured to provide a second signal based on the first signal of the first circuit node 140 such that only after a lapse of a second period of time, which is longer than the first time period, a change of the first signal leads to a corresponding change of the second signal.

The second signal is in this case to the first terminal of the transmission circuit 350 which transmits the second signal in response to the control signal from the change detection circuit 330 at the third terminal at the second circuit node 190 couples. The coupling strength with which the transmission circuit 350 makes this coupling is now dependent on the control signal. Shows the change detection circuit 330 via the control signal just a change, the second signal, that is the delayed signal of the delay circuit 340 in the second circuit node 190 more coupled, while without the control signal, a corresponding coupling takes place weaker or the second signal completely from the second circuit node 190 is decoupled.

The coupling in the case of the presence of a control signal is in this case by the transmission circuit 350 performed such that the transmission circuit 350 a dominant influence on the state of the second circuit node 190 (N2) exercises. For this purpose, the transmission circuit 350 , the delay circuit 340 or another component of the compensation circuit 310 (eg the first inverter operating as a driver 320 ) is dimensioned so that just a change in the state of the second circuit node 190 (N2) from the compensation circuit 310 can be effected when the other circuit components, ie in particular the CMOS inverter of the Fuselatch circuit 100 an adverse effect on the second circuit node 190 Exercise (N2).

At the in 3 shown concrete implementation of an embodiment of the present The present invention is the delay circuit 340 as a second inverter 360 executed in 3 also referred to as InvB. The second inverter 360 is again designed as a CMOS inverter, in which an NMOS transistor has a channel width of 0.28 microns and a channel length of 0.8 microns. Accordingly, the PMOS transistor of the second inverter 360 a channel width of 0.28 microns and a channel length of 1.6 microns. That from the first inverter 320 output signal is referred to in the further course of the present invention as INT_N2, whereas that of the second inverter 360 output signal is referred to as DEL_N2.

As already the dimensioning of the channel lengths of the second inverter 360 indicates this, for example, compared to the first inverter 320 significantly weaker. Just about this dimensioning, it is possible that the second inverter 360 (InvB) the delay in conjunction with an input capacitance value of the transmission circuit 350 generated. Together with an output impedance value significantly influenced by the sizing and an input capacitance value of the transmission circuit 350 This results in an RC time (R = resistance value or impedance value, C = capacitance value), which significantly influences, if not determines, the second time period, which is longer than the first time period.

The change detection circuit 330 is also connected to the output of the first inverter 320 coupled and has a coupled with a first terminal to this capacity circuit 370 on, the two PMOS transistors 380 . 390 includes in 3 also referred to as C1 and C2, which illustrates their function as capacitances (C). The first connection of the capacitance circuit 370 , that is the output of the first inverter 320 is in this case in parallel with a source terminal and a drain terminal of the PMOS transistor 380 coupled, while a gate terminal of the PMOS transistor 380 with the second terminal of the capacitance circuit 370 is coupled. In contrast, the PMOS transistor is 390 with its gate connected to the output of the first inverter 320 coupled and in parallel via its drain terminal and its source terminal also to the second terminal of the capacitance circuit 370 coupled.

The two PMOS transistors 380 . 390 the capacity circuit 370 So are antiparallel between the two terminals of the capacitance circuit 370 coupled so as to symmetrize the capacitive behavior of the capacitance circuit 370 to achieve. Thus, in concrete implementations, field-effect transistors connected as capacitances may have asymmetrical capacitance values with respect to polarity and optionally an additional voltage dependence of the capacitance values, since the threshold voltage ranges of the relevant field-effect transistors differ from one another, which may lead to a dependence of the charge carrier concentration in the channel region of the transistors.

The second connection of the capacitance circuit 370 is over a resistive path 410 with a reference potential Vbleq or a connection 400 coupled to the reference potential. In this case, the reference potential has a value Vbleq which is typically between the supply voltage Vint and the reference potential (0 V or ground). In other words, in the case of a supply voltage of Vint = + 1.2V, the reference potential Vbleq = 0.6V.

The Reference potential Vbleq may be, for example, via a voltage divider circuit can be realized from resistive elements that are between the supply potential Vint and the reference potential are switched. In the case of a symmetrical Design of the resistor elements of the voltage divider can be just so a reference potential at a center tap between the two resistive elements be realized, which has an arithmetic mean between has the two voltages or potentials. Depending on the implementation It may be advisable in this context, even a burden the center tap optionally in the design of the resistor elements to take into account. Of course can be over asymmetrical designed voltage divider realized a different voltage become. Also, the reference potential can change in another way be generated.

The resistive path is through a PMOS transistor 410 formed, for example, with a source terminal to the second terminal of the capacitance circuit 370 and with a drain connection to the connector 400 for the reference potential Vbleq is coupled. The PMOS transistor 410 who in 3 also referred to as TP7, in this case has a width of the channel of 0.28 microns and a length of 1 micron. The gate terminal of the PMOS transistor 410 is beyond that with a connection 120 coupled for the reference potential. Due to the coupling of the gate terminal of the PMOS transistor 410 and the previously described design for channel width and length (sizing) is the PMOS transistor 410 essentially a resistor connected as a resistor transistor, which tends to be high impedance compared to the operating points of the other previously discussed transistors. The transistor 410 In particular, it has a channel length that corresponds approximately to ten times the standard channel length.

At the second terminal of the capacitance circuit and at the second circuit of the change detection circuit, respectively 330 , which coincide, is applied to a signal BOOSTN2, which as the control signal voltage signal of the transmission circuit 350 provided.

The transmission circuit 350 includes at the in 3 shown embodiment, at the first terminal a third inverter 420 who in 3 also referred to as InvC. The third inverter 420 is so with an input to the first terminal of the transmission circuit 350 and in turn is implemented as a CMOS inverter comprising a NMOS transistor with a channel width of 1.2 μm at the standard channel length and a PMOS transistor with a channel width of 0.6 μm at the standard channel length. At an output of the third inverter 420 this one outputs in the further course of the present description as RESTOR_N2 designated signal. In addition, in the further course of the present description of the output of the third Inver age 420 corresponding circuit nodes referred to as node RESTOR_N2.

The output of the third inverter 420 is connected to a source terminal of a PMOS transistor 430 (TP6) and a drain terminal of an NMOS transistor 440 (TN5) coupled. Both transistors 430 . 440 are with their gate terminals to the second terminal of the change detection circuit 330 coupled so that the potential BOOSTN2 is applied to this. The third connection of the transmission circuit 350 that is connected to the second circuit node 190 the fuselatch circuit 100 is coupled to the drain terminal of the PMOS transistor 430 and the source terminal of the NMOS transistor 440 coupled. The PMOS transistor 430 here has a channel width of 0.9 microns at the standard channel length and the NMOS transistor 440 a channel width of 0.6 microns at the standard channel length.

With regard to the dimensioning is the third inverter 420 (InvC) designed so that this together with the two transistors 430 . 440 stronger than the CMOS inverter with the two transistors 170 . 180 the fuselatch circuit 100 is. This makes it possible that the transmission circuit 350 at the in 3 In the embodiment of the present invention shown, the above-described dominating influence on the second circuit node 190 (N2) can exercise. About flows about the NMOS transistor of the third inverter 420 and due to the potential at the gate terminal of the transistor 430 the current through this transistor, so there is a strength of this series circuit due to the specified dimensions of about 4. In contrast, the two transistors 170 . 180 the fuselatch circuit 100 a strength of about 2, giving the dominant influence that the compensation circuit 310 , which is also referred to as Latch Restore circuit, clearly illustrated.

In addition, the two transistors 430 . 440 in connection with the reference potential Vbleq, which is connected to the connection 400 the compensation circuit 310 is provided, is designed so that the reference potential together with the dimensioning of these two transistors ensures that it operates in the presence of the reference potential Vbleq at the gate electrodes, the transistors in the bending region of their characteristics, so that these compared to their Einschaltwiderstandswerten in this case are high impedance. The coupling strength with which the transmission circuit 350 the output of the third inverter 420 to the second circuit node 190 is thus the resistance value of the respective transistors 430 . 440 ,

Before the mode of operation is to be explained in greater detail below simulation results in the further course of the present description, the operation of the compensation circuit will be described first 310 basically described. The stability of in 3 shown bistable flip-flop circuit 300 against disturbances, for example in the form of alpha or neutron beam hits, is achieved by the fact that the conductivity between the output of the third inverter 420 (Node RESTOR_N2) and the second circuit node 190 (N2) depending on whether at the output of the third inverter 420 (Node RESTOR_N2) the original in the second circuit node 190 (N2) stored voltage or the corresponding inverse voltage. In other words, the conductivity of the transistors 430 (TP6) and 440 (TN5) depending thereon by the change detection circuit 330 controlled, whether originally in the second circuit node 190 (N2) state (1 or 0) coincides with that at the output of the third inverter 420 is present.

Is so for example at the output of the third inverter 420 (RESTOR_N2) originally in the second circuit node 190 (N2) stored voltage, then the conductivity is between the output of the third inverter 420 and the second circuit node 190 , that is, the conductivity of the two transistors 430 . 440 big and possibly a tilted second knot 190 (N2) is via the two aforementioned transistors 430 . 440 and the third inverter 420 (InvC) brought back to the originally stored voltage value. So there is a tilting of the node 190 (N2), the first circuit node also starts 140 (N1) to tilt, what about the first inverter 320 to a change the voltage INT_N2 at the output of the first inverter 320 and thus at the capacity circuit 370 leads. Due to the design of the resistive path in the form of the PMOS transistor 410 Thus, a correspondingly changed voltage is also at the output of the capacitance circuit 370 to (BOOSTN2), so that (at least) one of the two transistors 430 . 440 the transmission circuit 350 is controlled so that it has a relation to the original state increased conductivity.

As a result, but that at the output of the third inverter 420 applied potential in the second circuit node 190 (N2) coupled, so that this due to the dominating influence of the compensation circuit 310 is prevented from tipping. Due to the delay circuit 340 in the form of the second inverter 360 This is at the output of the third inverter 420 nor the original voltage, so the voltage before the onset of the fault on.

Is on the other hand at the output of the third inverter 420 (Node RESTOR_N2) after an alpha or neutron beam hit the inverse originally in the node 190 (N2) stored voltage, then the conductivity is between the output of the third inverter 420 and the second circuit node 190 (N2) due to the non-driving of the two transistors 430 . 440 very low, leaving the second circuit node 190 not over the two transistors 430 . 440 and the third inverter 420 can be tilted. In other words, in this scenario where the alpha or neutron ray hit is not within the range of the actual fuselatch circuit 100 leads to a buildup of charge, but in a region of the compensation circuit 310 "Behind" the change detection circuit 330 therefore harmless, since in this case the change detection circuit 330 the transmission circuit 350 provides no corresponding control signal to the conductivity of the two transistors 430 (TP6) and 440 (TN5) to change. These therefore continue to exist in their high-impedance state defined by the reference potential Vbleq.

The following are based on the 4 and 5 illuminated two different scenarios in which an alpha particle hit a massive disturbance of the state of the bistable flip-flop circuit 300 is triggered. The impact of the alpha particle or the alpha particles is modeled by a current pulse, which rises rapidly to a current value of +/- 1 mA and then drops off exponentially over a period of typically 80 ps. The polarity of the impressed current pulse depends on the exact location, the type of impact of the respective alpha particles and the charge change to be described at one of the nodes.

4 Illustrates in the partial illustrations a to c the case that the second circuit node 190 (N2), which is previously for example at the voltage 0 V, ie at the reference potential, is brought by an alpha or neutron beam hit to a voltage value of about 2.2 V, ie well above the supply voltage value of Vint = 1.2 V. lies. The exact voltage value generated by the alpha or neutron beam hit is, of course, dependent on the amount of charge introduced and thus on the shape and parameters of the current pulse explained above.

4a shows a plot of the two voltage waveforms at the output of the as a delay circuit 340 working second inverter 360 (DEL_N2) and the voltage waveform at the output of the third inverter 420 (RESTOR_N2). 4b also shows the voltage curve at the inputs of the two transistors 430 . 440 (BOOSTN2 or BOOST_N2) of the transmission circuit 350 , as well as the voltage at the output of the first inverter 320 (INT_N2). 4c finally shows a plot of the voltage waveform at the first circuit node 140 (N1) and the second circuit node 190 ("Alpha hit on N2"), where the time scale extends along the abscissa of the three subpaintings in 4 each from 0 ns to 1.4 ns.

Due to the alpha or neutron beam hit modeled above by the current pulse described above, the second circuit node is at a time of about 100 ps 190 (N2) has increased to about 2.2 V (cf. 4c ) also becomes the voltage at the output of the third inverter 420 initially on the not completely blocking transistors 430 . 440 pulled to a maximum value of about 0.8V (RESTOR_N2). Due to the strong third inverter 420 (InvC) are at the output of this inverter 420 initially reaches values of about 0.6 V and later reaches a value of about 0 V.

The first circuit node 140 (N1) tilts due to the second circuit node 190 (N2) present voltage value of about 1.2 V (= Vint) to 0 V, so that the output of the first inverter 320 (Node INT_N2) increases from 0V to about 1.2V. Because of that at this output of the first inverter 320 the voltage value rises from 0 V to about 1.2 V, is via the two connected as capacitors transistors 380 . 390 in the context of capacity switching 370 also the output of the capacity circuit 370 (Node BOOSTN2) is raised from its original voltage value Vbleq = 0.6V to about 1.2V. It should be noted that, as previously explained, the output the capacity circuit 370 (Node BOOSTN2) via the high-impedance transistor 410 is brought as a resistive path to a voltage value Vbleq = Vint / 2 = 0.6 V (precharge).

As a result, the NMOS transistor 440 (TN5) fully turned on, so that the logic state 0, that is, at the output of the third inverter 420 (Node RESTOR_N2) voltage applied to the second circuit node 190 (N2) can be coupled. This becomes the second circuit node 190 (N2) again via the NMOS transistor 440 (TN5) and the n-channel transistor of the third inverter 420 (InvC) brought to 0V.

After at the output of the first inverter 320 (Node INT_N2) the voltage has risen from 0 V to 1.2 V, the voltage value starts at the output of the second inverter 360 (Node DEL_N2) slowly drop from 1.2V to 0V. The reason for this is that, as previously explained, the second inverter 360 (InvB) is very weak compared to the other components.

After the voltage value at the output of the first inverter 320 (Node INT_N2) has risen from 0 V to 1.2 V, the voltage value at the output of the delay circuit decreases 340 , ie at the output of the second inverter 360 (Node DEL_N2) slowly decreases from about 1.2V to about 0V. As previously explained, the second inverter is 360 (InvB) tends to be rather weak compared to the other components. The width of the p-channel transistor is 0.28 μm, while the length of the p-channel transistor is 0.8 μm. The width of the associated n-channel transistor is also 0.28 microns, whereas the length of the n-channel transistor is even at 1.6 microns. Characterized in that at the output of the second inverter 360 (Node DEL_N2) comparatively long (second period), the logic state 1 is maintained, is also due to the output of the third inverter 420 (Node RESTOR_N2) for a sufficiently long time, a voltage value of about 0 V, so that the logic state 0 in the second circuit node 190 (N2) can be written back as described above.

So after the second circuit node 190 (N2) was brought back to 0 V, also tilts the first circuit node 140 (N1) due to the feedback described above in connection with the fuselatch circuit 100 in 1a back to the original state of tension that this circuit node had before the alpha or neutron beam hit. The same applies to the voltage values at the output of the first inverter 320 (Node INT_N2) and the output of the second inverter 360 (Node DEL_N2).

While as related to 4 Simulation results of the circuit 3 for a positive alpha or neutron beam hit the node 420 (N2) are in 5a to 5d corresponding simulation results of this circuit for a negative alpha or neutron beam hit on the second circuit node 190 (N2). Here is in 5a the voltage at the output of the third inverter 420 (Node RESTOR_N2) shown while in 5b the voltage waveform at the output of the second inverter 360 (Node DEL_N2) is shown. In the 5c and 5d are each as a function of time t in the time range between 0 ns and 1.4 ns, the voltage waveforms at the output of the first inverter 320 (Node INT_N2), at the output of the capacitance circuit 330 (Node BOOST_N2) and at the two circuit nodes 140 (N1) and 190 (Alpha hit on N2) shown.

Will, as in the 5a to 5d is shown, for example, the second circuit node 190 (N2) is brought to -1 V by an alpha or neutron beam hit, the second circuit node having previously stored a voltage of 1.2 V, becomes the output of the third inverter 420 (Node RESTOR_N2) pulled briefly to 0 V, but by the strong third inverter 420 (InvC) is immediately corrected again so that at the output of the third inverter 420 the voltage value rises again to approx. 1.2V. Due to the feedback of the Fuselatch circuit 100 The first circuit node also tilts 140 (N1) due to the voltage dip of the second circuit node 190 (N2) from 0V to 1.2V, so that also at the output of the first inverter 320 (Node INT_N2) the voltage value changes from 1.2 V to 0 V.

About the capacity circuit 370 with the two connected as capacitors transistors 380 . 390 (C1, C2) also becomes the output of the capacitance circuit 370 (Node BOOST_N2) changed from approx. 0.6 V to approx. 0 V. As a result, the p-channel transistor or PMOS transistor 430 (TP6) full for at the output of the third inverter 420 (Node RESTOR_N2) adjacent logical 1 turned on. This becomes the second circuit node 190 (N2) again via the transistor 430 and the p-channel transistor of the third inverter 420 (InvC) brought to 1.2V. After the second circuit node 190 (N2) returns to 1.2V, not just the first circuit node tilts 140 (N1) back to the original voltage state that it had before the alpha or neutron beam hit, but also the circuit nodes at the outputs of the first inverter 320 (Node INT_N2) and the second inverter 360 (Node DEL_N2). These too return to their original state of tension.

This in 3 shown embodiment of a bistable flip-flop circuit 300 is thus also able, in the event of a fault, which the node 190 (N2) reduced in magnitude by 2.2 V with respect to its voltage value to compensate them within a short time, more precisely, within less than 1 ns. Of course, depending on the design, implementation and other parameters of the implementation of the circuit in question faster or slower compensation times for stronger or weaker interference can be achieved.

Analogous considerations to an alpha or neutron beam hit on the second circuit node 190 (N2) apply to other nodes in the case of an alpha or neutron beam hit 3 shown circuit, so for example for the first node 140 (N1) and the output of the first inverter 320 (Node INT_N2), since in all these cases also via the change detection circuit 330 a corresponding counter-reaction via the transmission circuit 350 in the second circuit node 190 (N2) can be coupled. This is not least because the change detection circuit 330 within a first period of time, the control signal of the transmission circuit included in the voltage signal at the node BOOSTN2 350 provides while the delay circuit 340 the change of the signal from the first circuit node 140 (N1) only after a lapse of the second time period to the transmission circuit 350 passes.

On the other hand, for example, one or more alpha or neutron beam hits the second inverter 360 (the delay circuit 340 ) such that the voltage value at the output of the second inverter 360 (Node DEL_N2) is changed significantly, however, remains the output of the change detection circuit 330 or the capacity circuit 370 (Node BOOST_N2) unchanged at the reference voltage Vbleq, ie at the voltage value Vint / 2 = 0.6 V. However, at this gate voltage are the two transistors 430 . 440 (TB6, TN5) only weakly conductive, leaving the second circuit node 190 (N2) will most likely not tip over.

For example, the output of the third inverter 420 (InvC), ie the node RESTOR_N2, hit by an alpha or neutron beam hit, the output of the change detection circuit remains 330 or the capacity circuit 370 (Node BOOST_N2) initially unchanged at reference potential Vbleq (eg, Vbleq = Vint / 2 = 0.6V).

For example, the output of the third inverter 420 (Node RESTOR_N2), which has, for example, a voltage of 1.2 V, hit by an alpha or neutron beam, this can be brought to about -1 V, so that briefly the second circuit node 190 (N2) tilts to 0V. Due to the dimensions of the third inverter 420 (InvC), however, the output of this inverter (node RESTOR_N2) is quickly brought back to 1.2V. The second circuit node tilted to the reference potential (0 V) 420 (N2) has the consequence that also the circuit node 140 (N1) goes to 1.2 V and also the output of the first inverter 320 (Node Int_N2) goes to 0V. This further causes the node (BOOST_N2), that is, the output of the change detection circuit 330 with respect to its voltage value moves to the reference potential (0 V), which ultimately leads to the second circuit node 190 (N2) is brought back to 1.2V.

Such short-term potential fluctuations (glitches), which in the case of an alpha or neutron beam hit with typical durations of a maximum of about 0.5 ns at the two circuit nodes 140 (N1) and 190 (N2) are often harmless. That is, they do not cause malfunction in the subsequent redundancy evaluation circuits. In some implementations, for example, they are no longer detectable after two subsequent (logical) gates, so they are no longer visible in the voltage curve.

The in the 4 and 5 The voltage curves shown are based on simulation results, which in turn are based on the Fuselatch circuit, as in 3 is shown. The alpha or neutron beam hits are hereby modulated by current pulses imparted to the node in question and comprising a rapid increase to +/- 1 mA followed by an exponential decay with a characteristic current duration of typically 80 ps.

Like both in the 4 and 5 reproduced simulation results as well as corresponding comparison results based on a Fuselatch circuit 100 out 1a have the Fuselatch circuit 300 out 3 according to an embodiment of the present invention about twice the strength against alpha or neutron beam hits than the 1a shown Fuselatch circuit 100 on when their circuit nodes 140 . 190 (N1, N2) have capacitance values, so that the area consumption of the two in the 1a and 3 shown circuits is approximately identical.

Such a circuit is stable or resistant only to alpha or neutron beam hits up to a strength determined by a corresponding Current pulse can be modulated, but has a characteristic duration of only 40 ps. Since the characteristic time scale (80 ps vs. 40 ps) essentially characterizes the duration of the current pulse, the amount of charge applied to the node in question is inverse or inversely proportional to the characteristic time scale. Thus, it is clear that a fuse latch circuit with capacitance values or capacities of the two circuit nodes 140 . 190 (N1, N2), compared to the reference potential (ground), for example, by a connected between a gate terminal and a combined source and drain terminal NMOS transistor with a channel width of 4.5 microns and a channel length of 0.47 μm can be modulated, is about twice as resistant.

To a fuselatch circuit 100 as they are in 1a shown to bring to comparable strength against alpha or neutron Strahlstreffer, as the circuit according to the embodiment of the present invention from 3 It may be necessary to determine the capacities or capacitance values of the two circuit nodes 140 . 190 (N1, N2) to double in size. In the case of modulation by NMOS transistors, this may mean, for example, that they would have a channel width of 9 μm and a channel length of 0.47 μm.

As already at the beginning of the description of in 3 shown embodiment of the present invention are the widths of the transistors 170 (TP2), 210 (TP3), 220 (TP4), 230 (TP5) 180 (TN2) 200. (TN3) and 240 (TN4) in the circuit 3 opposite to the Fuselatch circuit 1a reduced. As in the embodiment of the present invention, as shown in the 3 In addition, no additional measures for increasing the capacity of the two circuit nodes 140 . 190 (N1, N2) are required, so in 3 shown embodiment of the present invention in comparison of the Fuselatch circuit 100 out 1a be replaced approximately neutral, with in addition about twice the strength against alpha or neutron beam hits can be realized.

Of course, depending on various implementation-specific details, a different change in alpha, neutron beam, or other interference may also be achieved. Alternatively, of course, also with the same strength against interference (for example, alpha or neutron beam hits) the Fuselatch circuit 1a by an embodiment of the present invention in the form of a bistable flip-flop circuit 300 out 3 be replaced, so as to save chip area. Also, implementations are possible within the scope of embodiments of the present invention in which both are at least partially realized.

6 shows a further embodiment of the present invention in the form of a bistable flip-flop circuit 300 ' that differ from the in 3 shown bistable flip-flop circuit 300 essentially different with respect to two points. On the one hand, the bistable flip-flop circuit 300 ' out 6 a modified compensation circuit 310 ' on, relating to the transmission circuit 350 ' from the compensation circuit 310 with its compensation circuit 350 out 3 different.

However, before the resulting changes in the structure of the compensation circuit 310 ' and the driver circuit 350 ' will be described and explained in more detail, is first the second change between the two embodiments in the 3 and 6 considered closer and explained. So differ with the exception of the two transistors 150 . 130 the sizing of the others not to the transmission circuit 350 respectively. 350 ' In some cases, the transistors belonging to them are quite clear, which in turn illustrates that the values shown in the figures are exemplary.

In the 6 For example, due to the different dimensioning of the transistors, the circuit shown can, for example, have improved stability with respect to process variations in the production in comparison to that in FIG 3 exhibit. So it may be z. For example, in the case of circuits produced in the same manufacturing step, the NMOS transistors are particularly good in one case, but the PMOS transistors are particularly bad, or vice versa. Sizing, as exemplified in 6 For example, this can contribute to a further optimization of a circuit which is more stable than process fluctuations.

So points the PMOS transistor 170 (TP2) now has a width of 0.2 microns at a channel length of 0.18 microns. The NMOS transistor 180 (TN2) has a channel width of 0.28 μm with a channel length of 0.36 μm. The PMOS transistor 210 (TP3) has a channel length of 0.3 μm and a channel width of 0.12 μm. The two PMOS transistors 220 . 230 (TP4, TP5) each have channel widths of 0.7 .mu.m in the previously described standard channel length of 0.1 .mu.m. Likewise, the two NMOS transistors 200. . 240 (TN3, TN4) each have a width of 0.6 microns on the standard channel length.

Also in terms of compensation circuit 310 ' are with the exception of the transmission circuit 350 ' in otherwise identical structure, the dimensions of the transistors slightly compared to the dimensions of the in 3 modified embodiment shown. For example, the first inverter includes 320 (InvA) has a 0.28 μm channel width NMOS transistor at the standard channel length and a 0.9 μm channel size PMOS transistor at the standard channel length. Also as a delay circuit 340 serving second inverter 360 (InvB) has an NMOS transistor with a channel width of 0.28 microns and a channel length of 0.66 microns, while the associated PMOS transistor has a channel width of also 0.28 microns with a channel length of 1.6 microns. The two PMOS transistors connected as capacitors 380 (C1) and 390 (C2) the capacity circuit 370 the change detection circuit 330 each have channel widths of 0.5 μm at channel lengths of 0.46 μm. The as resistive path 410 working PMOS transistor 410 (TP7) has a channel width of 0.2 μm with a channel length of 1 μm.

The main difference between the in 6 shown embodiment of a bistable flip-flop circuit 300 ' and the bistable flip-flop circuit 300 out 3 However, according to one embodiment of the present invention is in the field of transmission circuit 350 ' respectively. 350 , While at the in 3 shown embodiment, a transmission gate-like transmission circuit 350 is implemented at the in 6 a tristate inverter has been implemented. More specifically, the third inverter 420 (InvC) and the two transistors 430 . 440 (TP6, TN5) 3 against the in 6 shown tristate inverter 350 ' been replaced.

The transmission circuit 350 ' or the tristate inverter 350 ' thus comprises transistors connected in series with respect to the source and drain terminals, respectively 450 . 460 . 470 and 480 on that between a connection 160 for the supply voltage Vint and a connection 120 are switched for the reference potential. A PMOS transistor 450 (TP7) is so with a source connection to the connector 160 for the supply voltage and with a drain connection to a source terminal of a PMOS transistor 460 (TP6) switched. A gate terminal of the PMOS transistor 450 (TP7) is connected to the output of the second inverter 360 , so coupled to the node (DEL_N2). The transistor 450 indicates at the in 6 implementation shown a channel width of 1 micron at the standard channel length.

The PMOS transistor 460 is with a drain terminal on the one hand to the second circuit node 190 the fuselatch circuit 100 and on the other hand to a drain terminal of an NMOS transistor 470 (TN5) coupled. The PMOS transistor 460 (TP6) with a channel width of 0.7 μm at the standard channel length is connected to the output of the change detection circuit with a gate connection 330 or to the second terminal of the capacitance circuit 370 coupled. The PMOS transistor 460 is thus able to receive via its gate terminal the potential at the node BOOST_N2, which comprises the control signal.

Also a gate terminal of the NMOS transistor 470 (TN5) is connected to the output of the change detection circuit 330 , so the capacity circuit 370 coupled. This transistor has a channel width of 0.5 μm at the standard channel length. It has a source connection to a drain terminal of an NMOS transistor 480 coupled, which has a channel width of 0.9 microns at the standard channel length. Via a source terminal is the NMOS transistor 480 (TN6) with the connection 120 coupled to the reference potential, wherein a gate terminal of this transistor is also connected to the output of the second inverter 360 coupled.

Due to the interconnection of the gate terminals of the PMOS transistor 450 (TP7) and the NMOS transistor 480 (TN6) to the output of the third inverter 360 These form the inverter stage of the Tristate inverter 350 ' , The PMOS transistor 460 (TP6) and the NMOS transistor 470 (TN5) enable decoupling of the output of the tristate inverter 350 ' , which is the connection for the second circuit node 190 (N2) acts by connecting these two transistors to the second circuit node 190 from the two transistors operating as inverters 450 . 480 decouple. Also with the tristate inverter 350 ' are just the two transistors 460 . 470 in connection with the reference potential Vbleq designed such that these two transistors are operated when the reference potential at their respective gate terminals in the bending region of their characteristics. Thus, these two transistors have high resistance values in comparison to their respective turn-on resistances in this operating state, which corresponds to a decoupling of the inverter components from the output. The operation of the tristate inverter 350 ' thus resembles that of the transmission circuit 350 from the in 3 shown embodiment. This also allows coupling of the second circuit node 190 (N2) to the supply potential or to the reference potential with a dependent on the control signal coupling strength in the form of the resistance value. So while the second signal at the output of the second inverter 360 or the delays approximately circuit 340 indicates whether the second circuit node 190 via the tristate inverter 350 ' is to be coupled to the supply potential or to the reference potential, the control signal shows the change detection circuit 330 the strength of this coupling.

In further embodiments of the present invention may deviate from the in 3 and 6 The embodiments shown, the change detection circuit 330 also be executed deviating. For example, the capacity switch 370 not on the basis of field effect transistors, ie based on the PMOS transistors shown or corresponding NMOS transistors can be realized, but it can also other capacitive components, such as semiconductor capacitor circuits or trench capacitors (trench capacitances, trench capacitances) implemented become.

Also, instead of the resistive path in the form of the PMOS transistor 410 an NMOS transistor, a metal resistive element or a semiconductor resistive element may be implemented as a resistive path. Thus, for example, in the case of a semiconductor resistance element, a resistance value of the resistive path can be adjusted not only by the dimensioning (length, width and thickness of the respective semiconductor structure) but also by their doping. Of course, it is also possible to use mixed forms of the abovementioned elements, that is to say, for example, semiconductor structures doped with metal clusters, purely metallic alloys or semiconductors / metal alloys (for example addition of silicon into metallic interconnects or structures).

In the in the 3 and 6 In the embodiments shown, inverters have been used as delay circuits which, due to their output impedance and the input impedance capacitance, of the subsequent switching unit (of the transmission circuits 350 . 350 ' ) realize the delaying effect. In principle, however, other circuits having a propagation time-influencing characteristic, which typically implements beyond a mere delay extending beyond the finite propagation velocity of the electromagnetic forces, may be used. Examples of this are in addition to the use of inverters, as the embodiments in the 2 and 6 Transistor circuits, operational amplifier circuits, RL gates, LC gates or RC gates.

Of course, in the in the 3 and 6 shown embodiments series circuits of two transistors are also changed by reversing the order of the two transistors. For example, the transistors 220 and 230 , the transistors 200. and 240 , the transistors 450 and 460 , the transistors 470 and 480 or more complex groups of transistors are each interchanged.

The in the 3 and 6 In addition, embodiments shown use a driver circuit, in which it is in each case and the first inverter 320 is. It goes without saying that corresponding embodiments of the present invention can also be implemented and operated without a corresponding inverter or a corresponding driver or with otherwise designed drivers which, for example, do not lead to an inversion of the signal.

Furthermore, exemplary embodiments of the present invention can also be used with a number of inverters differing from FIG. 3 in the context of the compensation circuit 310 respectively. 310 ' being constructed. For example, a non-inverting driver instead of the first inverter 320 used or may possibly omit the use of a driver stage entirely, for example, the delay circuit 340 or the transmission circuit 350 respectively. 350 ' be performed with only a single inverting circuit element. In this case, for example, could be realized that as a delay circuit 340 a corresponding RC circuit is used, so is the compensation circuit 310 the first circuit node 140 and the second circuit node 190 (N2) are coupled together via a single inverting circuit component. Of course, other numbers of inverting circuit components, in the context of the compensation circuit 310 between the two circuit nodes 140 . 190 are implemented, provided that it is an odd number of these. So can the delay circuit 340 also be executed as a cascade of several inverters.

Further, in the embodiments shown in FIGS 3 and 6 are shown instead of the single inverter 320 both for the subsequent second inverter 360 or delay circuit 340 as well as for the change detection circuit 330 each a separate driver stage are used. These may be either inverting or non-inverting driver stages, depending on the specific design. Of course, these may also be omitted, as the previous discussion has shown.

Embodiments of the present invention may of course be designed for other than positive supply voltages to the reference potential. In one In such case, it may be advisable to replace the PMOS transistors by NMOS transistors and the implemented NMOS transistors by PMOS transistors. In other words, in such a case, it may be advisable to change the polarity of the transistors in question. Of course, in addition to bipolar transistors can also be used instead of field effect transistors, which is why in the further course of the present description of source terminals, drain terminals and control terminals is spoken in connection with the transistors. In this case, the control connection in the case of a field effect transistor refers to a gate terminal and in the case of a bipolar transistor to a base terminal. Accordingly, source terminals are source terminals in the case of field effect transistors and emitter terminals in the case of bipolar transistors. Finally, sink connections are drain connections in the case of field-effect transistors and collector connections in the case of bipolar transistors.

Also If in the context of the present description so far embodiments of the present invention in the form of integrated circuits or ASICs (ASIC = application-specific integrated circuit = application-specific integrated circuit) Of course, these may also be described as discrete circuits with discrete switching elements or as a combination of discrete switching elements and integrated Circuits can be realized. For example, in the case of realizations of embodiments the present invention by means of discrete circuits disorders of Supply voltage or other external influences at least partially compensated become.

In In this context, it is appropriate to point out that in the context of the present description under a connection, an entrance or an outlet does not necessarily have plug connections, contact points, Solder joints or others for By external connections provided structures or connection surfaces meant are. Rather, the term connection also refers to parts a trace, an electrical connection or other parts a circuit. connections Thus, in the context of the present description, they do not necessarily indicate an external connection, but can currently be integrated Circuits, but also in the case of discrete circuits or combined Circuits refer to parts of tracks, the functional groups connect with each other.

Depending on The circumstances may embodiments the inventive method be implemented in hardware or in software. The implementation can on a digital storage medium, especially a floppy disk, CD or DVD with electronically readable control signals, the so can interact with a programmable computer system, the embodiments the erfindungsge MAESSEN method accomplished become. Generally there are exemplary embodiments The present invention thus also in a software program product or a computer program product or a program product with one on a machine-readable one carrier stored program code for carrying out an embodiment of the inventive method, if there software program product on a machine or a processor expires. In other words, can be an embodiment The present invention thus as a computer program or Software program or program with a program code for carrying out a embodiment a process can be realized when the program is on a Processor expires. Of the Processor can in this case from a computer, a smart card, an arithmetic logic unit (ALU = Arithmetic Logic Unit), an ASIC (application specific integrated circuit = application specific integrated circuit) or other integrated circuit be formed.

100

Fuselatch circuit

100 '

latch

110

resistive element

120

connection for reference potential

130

NMOS transistor

140

first circuit node

150

PMOS transistor

160

connection for supply voltage

170

PMOS transistor

180

NMOS transistor

190

second circuit node

200

NMOS transistor

210

PMOS transistor

220

PMOS transistor

230

PMOS transistor

240

NMOS transistor

300

bistable Kippstufenschaltung

310

compensation circuit

320

first inverter

330

Change detection circuit

340

delay circuit

350

transmission circuit

360

second inverter

370

capacitance circuit

380

PMOS transistor

390

PMOS transistor

400

connection for reference potential

410

PMOS transistor

420

third inverter

430

PMOS transistor

440

NMOS transistor

450

PMOS transistor

460

PMOS transistor

470

NMOS transistor

480

NMOS transistor

Claims (25)

Bistable flip-flop circuit ( 300 ) having the following characteristics: a first ( 140 ) and a second circuit node ( 190 ) coupled to each other via a feedback path; and a compensation circuit ( 310 ) parallel to the feedback path with the first circuit node (FIG. 140 ) and the second circuit node ( 190 ) and a change detection circuit ( 330 ) connected to the first circuit node ( 140 ) and configured to respond to a change in a first signal at the first circuit node ( 140 ) to provide within a first time period a control signal indicative of an occurrence of the change of the first signal; a delay circuit ( 340 ) connected to the first circuit node ( 140 ) and configured to generate a second signal based on the first signal such that a change in the first signal results in a change of the second signal only after an elapse of a second time period longer than the first time period; and a transmission circuit ( 350 ) connected to the second circuit node ( 190 ) and is adapted, in response to the control signal, to apply the second signal more strongly to the second circuit node ( 190 ) and without the control signal the second signal weaker to the second circuit node ( 190 ) or the second signal from the second circuit node ( 190 ) to decouple has. Bistable flip-flop circuit ( 300 ) according to claim 1, wherein the change detection circuit ( 330 ) a capacity circuit ( 370 ) having a first terminal connected to the first circuit node ( 140 ) and a second terminal connected via a resistive path ( 410 ) with a reference potential ( 400 ) is coupled and at which the control signal can be tapped comprises. Bistable flip-flop circuit ( 300 ) according to claim 2, wherein the capacitance circuit ( 370 ) and the resistive path ( 410 ) are formed so that an RC time from a capacitance value of the capacitance circuit ( 370 ) and a resistance value of the resistive path ( 410 ) is greater than or equal to the second time period. Bistable flip-flop circuit ( 300 ) according to one of claims 2 or 3, in which the transmission circuit ( 350 ) a first transistor ( 430 ) and a second transistor ( 440 ), each connected to a source terminal or a drain terminal to the second circuit node ( 190 ) are coupled and are formed so that they have a high resistance value relative to their on resistances at a reference of the reference potential at their respective control terminals. Bistable flip-flop circuit ( 300 ) according to one of the preceding claims, in which the transmission circuit ( 350 ) is designed to have a dominating influence on a state of the second circuit node ( 190 ) exercisable. Bistable flip-flop circuit ( 300 ) according to one of the preceding claims, in which the delay circuit ( 340 ) an inverter ( 360 ) connected to an input to the first circuit node ( 140 ) is coupled to an output with the transmission circuit ( 350 ) is configured to provide at the output the second signal and having an output impedance value such that an RC time based on the output impedance value and an input capacitance value of the transmission circuit ( 350 ) corresponds to the second time period. Bistable flip-flop circuit according to one of the preceding claims, in which the compensation circuit ( 310 ) a driver circuit ( 320 ) having an input to the first circuit node ( 140 ) and with an output to the change detection circuit ( 330 ) and the delay circuit ( 340 ) is coupled. Bistable flip-flop circuit ( 300 ) according to one of the preceding claims, in which the transmission circuit ( 350 ) an inverter ( 420 ) with an input connected to the delay circuit ( 340 ) and having an output connected to a parallel connection of a source terminal of a PMOS transistor ( 430 ) and a drain terminal of an NMOS transistor ( 440 ), wherein a drain terminal of the PMOS transistor ( 430 ) and a source terminal of the NMOS transistor ( 440 ) with the second circuit node ( 190 ), and wherein the gate terminals of the PMOS transistor ( 430 ) and the NMOS transistor ( 440 ) with the change detection circuit ( 330 ) are coupled to make them controllable by the control signal. Bistable flip-flop circuit ( 300 ) according to one of the preceding claims, in which the transmission circuit ( 350 ) a third scarf node, which is connected to the second circuit node ( 190 ), a series connection of a first PMOS transistor ( 450 ) and a second PMOS transistor ( 460 ) between a supply potential ( 160 ) and the third circuit node, and a series connection of a first NMOS transistor ( 480 ) and a second NMOS transistor ( 470 ) between the third circuit nodes and a reference potential ( 120 ), wherein a gate terminal of the first PMOS transistor ( 450 ) and the first NMOS transistor with the delay circuit ( 340 ) are coupled to make the second signal can be applied; and wherein a gate terminal of the second PMOS transistor ( 460 ) and the second NMOS transistor ( 470 ) with the change detection circuit ( 330 ) are coupled to make the control signal can be applied. Bistable flip-flop circuit ( 300 ) having the following characteristics: a first ( 140 ) and a second circuit node ( 190 ) coupled to each other via a feedback path; and a compensation circuit ( 310 ) parallel to the feedback path with the first circuit node (FIG. 140 ) and the second circuit node ( 190 ) and an inversion circuit ( 320 ) connected to an input to the first circuit node ( 140 ) and is adapted to (based on a first signal at the first circuit node ( 140 ) to provide a first inverted signal, a capacitance circuit ( 370 ) with a first terminal connected to the inversion circuit ( 320 ) to apply the first inverted signal, and to a second terminal connected via a resistive path (Fig. 410 ) with a reference potential ( 400 ) and to which a control signal can be tapped, an inverter ( 360 ) connected to an input to the inversion circuit ( 320 ) to apply the first inverted signal and having an output for a second signal based on the first inverted signal; and a transmission circuit ( 350 ) with one to the output of the inverter ( 360 ) coupled first terminal, with a to the second terminal of the capacitance circuit ( 370 ) coupled second terminal and one with the second circuit node ( 190 ) coupled third terminal, wherein the transmission circuit ( 350 ) is configured to more strongly couple the second signal in inverted form to the third terminal in response to the control signal, and configured to weaker couple or decouple the second signal in an inverted form to the third terminal without a control signal. Bistable flip-flop circuit ( 300 ) according to claim 10, wherein the inverter ( 360 ) has an output impedance value such that an RC time based on the output impedance value and an input capacitance value of the transmission circuit ( 350 ) with respect to the first terminal is greater than a first time period between a change of the first inverted signal and a change of the control signal. Bistable flip-flop circuit ( 300 ) according to one of claims 10 or 11, in which the capacitance circuit ( 370 ) and the resistive path ( 410 ) are configured such that an RC time based on a capacitance value of the capacitance circuit ( 370 ) and a resistance value of the resistive path ( 410 ) greater than or equal to the RC time based on the output impedance value of the inverter ( 360 ) and the input capacitance value with respect to the first terminal of the transmission circuit ( 350 ). Bistable flip-flop circuit ( 300 ) according to one of claims 10 to 12, in which the transmission circuit ( 350 ) a first transistor ( 430 ) and a second transistor ( 440 ), each connected to a source terminal or a drain terminal to the second circuit node ( 190 ) are coupled and are formed so that they have a high resistance value relative to their on resistances at a reference of the reference potential at their respective control terminals. Bistable flip-flop circuit ( 300 ) according to one of claims 10 to 13, in which the transmission circuit ( 350 ) is designed to have a dominating influence on a state of the second circuit node ( 190 ) exercisable. Bistable flip-flop circuit ( 300 ) according to one of claims 10 to 14, in which the transmission circuit ( 350 ) an inverter ( 420 ) with an input connected to the inverter ( 360 ) and having an output connected to a parallel connection of a source terminal of a PMOS transistor ( 430 ) and a drain terminal of an NMOS transistor ( 440 ), wherein a drain terminal of the PMOS transistor ( 430 ) and a source terminal of the NMOS transistor ( 440 ) with the second circuit node ( 190 ), and wherein the gate terminals of the PMOS transistor ( 430 ) and the NMOS transistor ( 440 ) with the capacity circuit ( 370 ) are coupled to make them controllable by the control signal. Bistable flip-flop circuit ( 300 ) after egg Nem of claims 10 to 15, wherein the transmission circuit ( 350 ) a third circuit node connected to the second circuit node ( 190 ), a series connection of a first PMOS transistor ( 450 ) and a second PMOS transistor ( 460 ) between a supply potential ( 160 ) and the third circuit node, and a series connection of a first NMOS transistor ( 480 ) and a second NMOS transistor ( 470 ) between the third circuit nodes and a reference potential ( 120 ), wherein a gate terminal of the first PMOS transistor ( 450 ) and the first NMOS transistor ( 480 ) with the inverter ( 360 ) are coupled to make the second signal detectable, and wherein a gate terminal of the second PMOS transistor ( 460 ) and the second NMOS transistor ( 470 ) with the capacity circuit ( 370 ) are coupled to make the control signal receivable. Bistable flip-flop circuit ( 300 ) having the following characteristics: a first ( 140 ) and a second circuit node ( 190 ) coupled to each other via a feedback path; and a compensation circuit ( 310 ) parallel to the feedback path with the first circuit node (FIG. 140 ) and the second circuit node ( 190 ), and a first inverter ( 320 ) connected to an input to the first circuit node ( 140 ) and is adapted to (based on a first signal at the first circuit node ( 140 ) provide a first inverted signal at an output of the first inverter; a capacity circuit ( 370 ) with a first connection to the output of the first inverter ( 320 ) and a second connection via a resistive path ( 410 ) with a reference potential ( 400 ), to which a control signal can be tapped, wherein the reference potential ( 400 ) between a supply potential ( 160 ) and a reference potential ( 170 ) lies; a second inverter ( 360 ) connected to an input to the output of the first inverter ( 320 ) and is configured to generate, based on the first inverted signal at an output of the second inverter, a second signal ( 320 ) to provide; and a transmission circuit ( 350 ) between the supply potential ( 160 ) and the reference potential ( 120 ), with a first connection to the output of the second inverter ( 360 ), with a second connection to the second terminal of the capacitance circuit ( 370 ) and with a third connection to the second circuit node ( 190 ) and is configured to connect the third connection to the supply potential (in dependence on the second signal with a coupling strength dependent on the control signal). 160 ) or the reference potential ( 120 ) to couple. Bistable flip-flop circuit ( 300 ) according to claim 17, in which the transmission circuit ( 350 ) a first transistor ( 430 ) and a second transistor ( 440 ) having a source terminal or a drain terminal connected to the third terminal of the transmission circuit ( 350 ) and which are designed to make it possible, as a coupling strength, to set a resistance value between the source terminals and the sink terminals by controlling the control terminals. Bistable flip-flop circuit ( 300 ) according to claim 18, wherein the capacitance circuit ( 370 ) and the restrictive path ( 410 ) are formed so that the reference potential in the control terminals compared to a Einschaltwiderstandswert the first transistor ( 430 ) and the second transistor ( 440 ) leads to a high resistance of the two transistors. Bistable flip-flop circuit ( 300 ) according to one of claims 17 to 19, in which the transmission circuit ( 350 ) is designed to have a dominating influence on a state of the second circuit node ( 190 ) exercisable. Bistable flip-flop circuit ( 300 ) according to one of claims 17 to 20, in which the second inverter ( 360 ) is configured to have an output impedance value such that an RC time based on the output impedance value and an input capacitance value of the transmission circuit ( 350 ) is greater than a first time period between a change of the first inverted signal and a change of the control signal. Bistable flip-flop circuit ( 300 ) according to one of claims 17 to 21, in which the transmission circuit ( 350 ) another inverter ( 420 ) with an input connected to the inverter ( 360 ) and having an output connected to a parallel connection of a source terminal of a PMOS transistor ( 430 ) and a drain terminal of an NMOS transistor ( 440 ), wherein a drain terminal of the PMOS transistor ( 430 ) and a source terminal of the NMOS transistor ( 440 ) with the second circuit node ( 190 ), and wherein the gate terminals of the PMOS transistor ( 430 ) and the NMOS transistor ( 440 ) with the capacity circuit ( 370 ) are coupled to make them controllable by the control signal. Bistable flip-flop circuit ( 300 ) according to any one of claims 17 to 22, wherein the transmissive circuit ( 350 ) a third circuit node connected to the second circuit node ( 190 ), a series connection of a first PMOS transistor ( 450 ) and a second PMOS transistor ( 460 ) between a supply potential ( 160 ) and the third circuit node, and a series connection of a first NMOS transistor ( 480 ) and a second NMOS transistor ( 470 ) between the third circuit nodes and a reference potential ( 120 ), wherein a gate terminal of the first PMOS transistor ( 450 ) and the first NMOS transistor ( 480 ) with the inverter ( 360 ) are coupled to make the second signal detectable, and wherein a gate terminal of the second PMOS transistor ( 460 ) and the second NMOS transistor ( 470 ) with the capacity circuit ( 370 ) are coupled to make the control signal receivable. Method for compensating for a fault in a bistable flip-flop circuit ( 300 ) with a first ( 140 ) and a second circuit node ( 190 ) coupled to one another via a feedback path, comprising: detecting a change of a first signal at the first circuit node ( 140 ) within a first period of time; Generating a second signal based on the first signal such that a change in the first signal results in a change in the second signal only after a lapse of a second time period that is longer than the first time period; and when a change of the first signal has been detected, coupling the second signal to the second circuit node (Fig. 190 ) with a greater coupling strength and if no change of the first signal has been detected coupling the second signal to the second circuit node ( 190 ) with a lower coupling strength; or decoupling the second signal from the second circuit node ( 190 ). Method for compensating for a fault in a bistable flip-flop circuit ( 300 ) with a first ( 140 ) and a second circuit node ( 190 ) coupled to each other via a feedback path, comprising: providing a first inverted signal based on a first signal at the first circuit node (Fig. 140 ); Detecting a change of the first inverted signal within a first period of time; Providing a control signal indicative of the change of the first inverted signal; Providing a second signal based on an inversion of the first inverted signal; Coupling a supply potential or a reference potential in dependence on the second signal with a coupling strength dependent on the control signal to the second circuit node ( 190 ).