DE102007042070B3 - Spread-spectrum-fractional-phase locked loop circuit for use as frequency generator, has interface circuit combining signals, where single signal is not guided, when stages require phase-step in same clock period and in different directions - Google Patents

Abstract

The circuit has a control block (CB) with a spread spectrum logic stage (SSC) that provides a direction control output signal and a phase step control signal. A fractional logic (Frac-N) stage provides another phase-step control signal. A logic interface circuit (Logic X) combines the signals, so that a single phase step control signal is guided to an interpolator (INT), when the stages require a phase-step in a same clock period and in same direction. The single signal is not guided to the interpolator, when the stages require the phase-step in same clock period and in different directions.

Description

The The present invention relates to a spread spectrum fractional phase locked loop, which can be used as a frequency generator.

electromagnetic disorder (EMI), which emanates from high-frequency applications, poses a problem This is the multiplication of wireless services and devices increases. Shielding is the conventional approach to counteract EMI. This approach requires significant hardware Investments. Another approach is spread spectrum clocking (SSC), which can be used in digital circuits, especially if the operating frequency required by a particular application a phase locked loop (PLL) is generated. At SSC will a center frequency according to a modulated corresponding pattern, so that the average frequency over time, the center frequency is still. In the PLL can you change the frequency reach by the feedback signal single phase steps in one of two opposite directions added become. In a "down spread" phase becomes the phase the feedback signal Turned clockwise, for "up spread" is the phase rotated in the clockwise direction, and for "center spread" becomes the phase once clockwise and then counterclockwise (based on a 360 ° phase diagram the feedback signal). To phase sequence to the feedback signal can add in one of the two opposite directions a phase selector used when the oscillator used in the PLL multiphase output signals has (such as a ring oscillator). When small phase steps needed A phase interpolator may be used in conjunction with the phase selector be to the phase gaps between adjacent phases of the plurality of oscillator output signals to share. Any logic circuit is provided to the phase selector and the phase interpolator according to a desired frequency pattern to control.

A PLL circuit can be used as a frequency generator to off an input reference frequency to produce an output frequency which through the relationship that used in the input divider and in the feedback divider Dividends is determined. If one for a particular application needed Frequency not achieved with fixed dividends in the input or feedback divider a "fractional-N phase locked loop" is required Fractional-N PLL can turn a reference frequency into a fractional frequency produce. additionally to the conventional one Input and feedback divider contains the PLL the feedback loop a phase selector or phase aligner, the feedback signal individual phase steps in one of the two opposite directions inflict can. The phase selector will controlled by a logic circuit, so that the feedback signal the for the desired output frequency the PLL needed Number of phase steps in one of the two directions is added.

In an application that requires a fractional-N PLL, it would be a great advantage if SSC could be used to reduce EMI. One potential The approach is to couple an SSC circuit with the fractional-N PLL. There both approaches, So Fractional-N and SSC, but the concept of adding Phase steps to the feedback signal can apply Situational conflicts occur. A first situation then exists if the fractional-N logic and the SSC logic both simultaneously request a phase step in the same direction. In this case two phase steps are needed but if both phase steps are performed simultaneously, learns the feedback divider a big Phase step and can fail. In addition, a phase shift circuit needed which can handle both phase steps at the same time, which is harder to do reach is. A second situation exists when the fractional-N logic and the SSC logic both simultaneously make one phase step into different ones Request directions. In such a case can at all no phase step needed become.

US 2007/0041486 A1 discloses a spread spectrum clocking with a phase locked loop having a polyphase output oscillator. In the feedback loop, two frequency dividers are provided. A control circuit receives the once-divided feedback signal and controls the selection of the phase-shifted VCO output signal.

US 7,043,202 62 discloses spread spectrum timing with a multi-phase clock signal, ensuring that a select signal for selecting one of the clock signals is out of phase with the selected clock signal.

DE 10 2005 050 828 A1 discloses a fractional divider and a fractional-N PLL for a jitter-free fractional division of a signal frequency. A multi-phase clock signal is provided, from which the subsequent phase-shifted signal is sequentially selected before the signal thus selected is fed to a divider.

It is an object of the present invention to provide a fractional-N phase-locked loop, in which SSC logic can be used to counter EMI.

The The present invention provides a phase-locked loop with combined Spread spectrum and fractional-N logic ready, the possible conflicts between eliminates the phase requirements of spread spectrum logic and fractional-N logic. In particular, the invention provides a chain of a reference clock divider, a phase / frequency detector, a charge pump with a loop filter, a voltage controlled oscillator, the polyphase output signals and a feedback loop from the multi-phase outputs of the voltage controlled oscillator to a feedback input of the phase / frequency detector ready. The feedback loop contains one Phase selector, a feedback divider and a control block having an output that activates the phase selector controls that he has a certain phase as input to the feedback divider selects. The control block contains a spread spectrum logic circuit that receives an input signal from the output of the phase selector receives and a direction control output and a phase step control signal provides. The control block further includes a fractional logic circuit which receives an input signal from the output of the phase selector and a phase step control signal provides. A logic interface circuit combines the direction control output signal from the spread spectrum logic circuit, the phase step control signal from the spread spectrum logic circuit and the phase step control signal from the fractional logic circuit. That means a single Phase step control signal is passed to the phase selector and in one subsequent feedback clock period another phase step control signal is passed to the phase selector, when both the spread spectrum logic circuit and the fractional logic circuit in the same clock period a phase step in the same direction Request. Furthermore, no phase step control signal is applied to the phase selector when the spread spectrum logic circuit and the fractional logic circuit in the same feedback clock period request a phase step in different directions.

The phase locked loop according to the present invention, like a conventional phase locked loop, comprises a phase / frequency detector, a charge pump and a loop filter and a voltage controlled oscillator, and a reference clock divider. The voltage controlled oscillator may be operated to provide multiphase output signals, and these multiphase output signals are fed back to the input of the phase locked loop at the feedback input of the phase / frequency detector. In the feedback loop, a phase selector, a feedback divider and a control block are provided between the output of the voltage controlled oscillator and the feedback input of the phase / frequency detector. The output of the control block may be operated to control the phase selector to select a particular phase from the multiphase output signal of the voltage controlled oscillator and to supply that phase to the feedback divider. The control block may include a spread spectrum logic circuit that outputs a direction control signal and a phase step control signal. The spread spectrum logic circuit operates by speeding up or slowing down the phase change rate in the feedback path. By integrating this phase change with a phase locked loop, one obtains a frequency change that can be used to counter EMI. In other words, the center frequency of the output of the PLL is modulated according to a corresponding pattern so that the average frequency remains at the center frequency over time. The control block may further include a fractional logic circuit and a logic interface circuit. The fractional logic circuit receives at its input the output of the phase selector and then outputs a phase step control signal. The logic interface circuit may be operated to combine the direction control output signal and the phase step control signal from the spread spectrum logic circuit together with the phase step control signal from the fractional logic circuit. In this way, if both the spread spectrum logic circuit and the fractional logic circuit request a phase step in the same direction in the same clock period, the logic interface circuit supplies the phase selector with a single phase step control signal in that clock period. In a subsequent clock period, the logic interface circuit passes another phase step control signal to the phase selector. However, if both the spread spectrum logic circuit and the fractional logic circuit request a phase step in different directions in the same clock period, the logic interface circuit will not pass a phase step control signal to the phase selector. Accordingly, by performing two phase steps in immediately consecutive periods, the logic interface circuit ensures that a large phase step is avoided if the fractional-N logic and the SSC logic both simultaneously request a phase step in the same direction. If the fractional-N logic and the SSC logic both simultaneously request a phase step in different directions, no phase step takes place at all, since in this case no phase shift is needed at all. This way, an EMI gets into the fractio counteracted Nal-N phase locked loop without requiring significant hardware investment for electromagnetic shielding. Depending on the specific architecture of the logic interface circuit, two requests may be considered concurrent if they arrive at the phase selector at the same time and not if they have been issued simultaneously.

Preferably contains the phase selector a phase interpolator which receives an output signal from the voltage controlled Oscillator receives. The Output of the interpolator is then sent to the fractional logic circuit and also applied to the logic interface circuit. The Logic interface circuitry can then control the interpolator so in that it is based on the output signals derived from the interpolator the spread spectrum logic circuit and the fractional-N logic the multiphase output signals of the voltage controlled oscillator selects a specific phase.

The Logic interface circuit may have two shift registers clocked by the output of the phase selector contain. A first of the shift registers has inputs for reception the direction control output from the spread spectrum logic circuit, the phase step control signal from the spread spectrum logic circuit and the phase step control signal from the fractional logic circuit. A second of the shift registers has inputs for receiving the direction control output signal from the spread spectrum logic circuit and the phase step control signal from the spread spectrum logic circuit. The outputs of the shift registers are linked to an OR gate, around the phase selector to provide a phase step control signal. A shift register receives three Input signals; the direction control signal and the phase step control signal from the spread spectrum logic circuit and the phase step control signal from the fractional logic circuit. The other register receives two Input signals; the direction control output and the phase step control signal from the spread spectrum logic circuit. Both shift registers received the same clock signal at their clock inputs, which is the output signal of the phase selector is. An OR gate can then be operated so that it Output signals of both shift registers with the output signal of OR gate, the phase selector supplied is linked. This output signal tells the phase selector how much he has Phase of the output signal should shift. Preferably presents the second shift register gives the phase selector a direction control signal ready, that the phase selector indicates the direction in which the phase is to be shifted (in Clockwise, counterclockwise or not at all).

Further Advantages and features of the invention will become apparent from the below Description of a preferred embodiment and from the accompanying drawings. Show it:

1 a simplified circuit diagram of a conventional phase locked loop, which uses spread spectrum logic;

2 a simplified circuit diagram of a phase locked loop, the fractional-N logic uses;

3 a simplified circuit diagram of a phase locked loop according to the invention;

4 a simplified schematic diagram of a logic interface circuit for a phase locked loop according to the invention;

5A and 5B simplified circuit diagrams of circuit blocks of a logic interface circuit for a phase locked loop according to the invention;

6 a first example of a timing diagram for a logic interface circuit in a phase locked loop according to the invention;

7 a second example of a timing diagram for a logic interface circuit in a phase locked loop according to the invention; and

8th a third example of a timing diagram for a logic interface circuit in a phase locked loop according to the invention.

1 shows a conventional spread spectrum logic phase locked loop with a phase / frequency detector which can be operated to receive input signals from a reference clock divider 1 / N and a feedback divider 1 / M. A phase / frequency detector PFD is supplied with a reference input clock signal REF and a feedback clock signal FB. The output of the phase / frequency detector is connected to the input of a charge pump CP, wherein the output of the charge pump via a loop filter LPF is connected to an input of a voltage controlled oscillator VCO. The voltage controlled oscillator VCO may be operated to output multiphase output signals, one of which is selected as the output frequency, and all of which are applied to a multiplexer MUX. The output of the multiplexer MUX is connected to the feedback divider 1 / M and also to the input of a control block CB. The control block CB is formed by a spread spectrum logic stage SSC having an input connected to the output of the multiplexer MUX and an output connected to a counter control stage CC connected is. The output of the counter control stage CC is connected to a control input of the multiplexer MUX.

A the output from the voltage controlled oscillator VCO phases is used as the output clock of a clock generator. The polyphase output signals of the voltage controlled oscillator VCO are then the inputs of the Multiplexer MUX supplied, wherein the output signal of the multiplexer MUX in a feedback loop via the Feedback divider 1 / M to the feedback input of the phase / frequency detector PFD is fed back. The output signal of the multiplexer MUX also becomes the spread spectrum logic stage SSC supplied. When the speed of phase changes in the feedback loop accelerated or slowed down and this phase change is integrated into the phase locked loop, one obtains a frequency change. The architecture and functionality of the spread spectrum stage SSC hang from the acceleration or deceleration profile. For a downward spread the frequency, the phases are rotated counterclockwise, and for one up spread the phases are turned clockwise. To generate the center spread The phases are once clockwise and then once counter turned clockwise.

2 shows a conventional fractional-N phase-locked loop. The phase locked loop is almost identical to that in 1 circuit except that a fractional logic stage FL is provided instead of the control block CB so that the output of the multiplexer MUX is connected to the input of the fractional logic stage FL and the output of the fractional logic stage FL to the control input of the multiplexer MUX connected is.

Of the Operation of this phase locked loop is also based on a phase shift in the feedback path, except, that the phase shift now from the fractional logic stage FL instead of the spread spectrum logic level SSC is requested. If you use the spread spectrum logic SSC and however, when combined with the fractional logic level, the following occur Conflicts on. First, you can the spread spectrum logic and the fractional-N logic simultaneously a phase change request send in the same direction. In this situation must be effective two phases are moved simultaneously. If a circuit is implemented to move two phases simultaneously Feedback divider 1 / M a big one Phase jump and can fail, and also the phase shift circuit complicated. Second, conflict can occur when the spread spectrum logic SSC and the Fractional-N logic simultaneously a phase shift request send in different directions. Effective in this case at all no phase shift required.

3 shows a phase-locked loop according to the invention in which the problems of coupling spread spectrum logic with fractional-N logic are overcome. A reference clock divider 1 / N is provided at the input of a phase frequency detector PFD and may be operated to receive a reference clock signal Ref. The output of the phase / frequency detector is connected to a charge pump and loop filter stage CPLF whose output is connected to a voltage controlled oscillator VCO. The voltage controlled oscillator VCO may be operated to provide multiphase output signals that are applied to an interpolator INT. The interpolator INT acts as a phase selector and could also be implemented as a multiplexer, for example. One of the multiphase output signals of the voltage-controlled oscillator VCO is selected as the synthesized frequency output signal.

Of the Interpolator INT is in the feedback loop the phase locked loop provided so that its output with a feedback divider 1 / M is connected, wherein the output of the feedback divider 1 / M the Feedback input the phase / frequency detector PFD is supplied. Besides that is the output of the interpolator INT with the inputs of a spread spectrum logic stage SSC, Frac-N fractional logic stage, and a logic interface circuit LOGIC X connected. The spread spectrum logic stage SSC, the fractional logic level Frac-N and the logic interface circuit LOGIC X form one Control block CB for controlling the interpolator such that it off the polyphase output signal of the voltage controlled oscillator VCO selects a specific phase. The spread spectrum logic stage SSC can be operated such that the logic interface circuit LOGIC X two output signals providing; a direction control signal and a phase step control signal. The fractional logic stage Frac-N can be operated such that they provide the logic interface circuit LOGIC X with a phase control output signal provides. The logic interface circuit LOGIC X then sets the interpolator INT based on the output signals that they are from the spread spectrum logic stage SSC and the fractional logic stage Frac-N receives, an input signal ready.

The spread spectrum logic stage SSC and the fractional logic stage Frac-N both receive the output signal of the interpolator INT selected from the multiphase output signals of the voltage controlled oscillator VCO. It Then, in both the spread spectrum logic stage SSC and the fractional logic stage Frac-N, it is determined how to control the interpolator INT to generate the correct next clock phase. When it is necessary to modulate the output frequency, the spread spectrum logic stage SSC, using the direction control output signal, indicates in which direction the phase of the feedback signal should be rotated. In this example, the phase of the feedback signal is rotated counterclockwise when it is necessary to decrease the frequency "down-spread", and the phase is rotated clockwise when it is necessary to increase the frequency "up-spread", where but it can be the other way around. The phase rotation of the signal is controlled by the direction control output signal output from the spread spectrum logic stage SSC. The spread spectrum logic stage SSC and the fractional logic stage Frac-N may then both indicate, by the phase step control signals provided at their outputs, that individual phase steps should be added to the feedback signal. If both the spread spectrum logic stage SSC and the fractional logic stage Frac-N request a phase step in the same direction in the same feedback clock period, the logic interface circuit LOGIC X passes a single phase step control signal to the interpolator INT, followed by another phase step control signal in the subsequent clock period , The interpolator INT then adjusts the phase of the feedback signal accordingly to modulate its center frequency to the required output frequency. However, if the spread spectrum logic stage SSC and the fractional logic stage Frac-N request a phase step in different directions in the same feedback clock period, the logic interface circuit LOGIC X will not pass a phase step control signal to the interpolator INT.

The logic interface circuit LOGIC X is in 4 and 5 shown in more detail, the 6 to 8th Show timing diagrams in various stages of the logic interface circuit LOGIC X. The logic interface circuit LOGIC X comprises two shift registers each consisting of three flip-flops DFF. The first shift register has a detection / set stage D & S at the set inputs of two DFFs which are in 5A is shown in detail and may be operated to receive two input signals D01 and D02 from the spread spectrum logic stage - the direction control signal (DIR or D01) and the phase step control signal (D02), respectively. The second shift register has a direction detection stage D & D at its input 5B shown in detail. The direction detection stage D & D may also be operated to receive the direction control input signal and the phase step control input D01 or D02 from the spread spectrum logic stage.

The operation of the logic interface circuit LOGIC X will now be described with reference to FIG 4 . 5A and 5B and with reference to the timing diagrams in FIG 6 to 8th described. How out 5A and 5B As can be seen, the detection / set stage D & S is activated and the direction detection stage D & D is not activated when the input D01 is low. Now, if input D1 is low and a rising edge arrives at D02, this leads to a rising edge on D06. If D07 is low during this rising edge, D08 remains low because flip flop DFF08 remains reset. However, if D07 is high during a rising edge on E01, D08 is set to DLY for a delay and then reset. This means that a rising edge is generated at D08. If now D01 is high, nothing happens in the detection / riser stage D & S during the rising edge on D02. However, in the direction detection stage D & D, the rising edge becomes as in 5B shown, forwarded to D001.

How out 4 As can be seen, the first shift register includes the flip-flops DFF01, DFF02, DFF03, DFF04, the gates AND01 and AND02, and the detection / set stage D & S. This shift register is operative in the event that both the spread spectrum logic stage and the fractional N logic stage attempt to rotate the phase in the same direction, for example clockwise. The second shift register includes the flip-flops DFF05, DFF06 and DFF07, the gates AND03 and AND04 and the direction detection stage D & D. In this case, it is assumed that the phase should be rotated clockwise when input D01 (= DIR) is logic 0, and that the phase should be rotated counterclockwise when it is logic 1. However, this is not a limitation of the circuit, and the phase could also be rotated counterclockwise for a logic 0 and clockwise for a logic 1. The first shift register also receives a phase step control signal D03 from the output of the fractional-N stage Frac-N. The signal D02 activates the phase shift, the signal D01 determines the direction of the phase shift, and the signal D03 triggers the phase change. When the signal D03 is received at the set input of the flip-flop DFF01 in the first shift register, the flip-flop DFF01 is set, and when the signal D02 is received at the direction detection circuit D & D, the direction detection circuit D & D is activated. When the signal D01 is logic low, it detects the detection / set stage D & S. At the same time, it monitors the output from flip-flop DFF02 in the first shift register bene signal D07. When D07 is logic 0, the detection / set stage D & S sets the flip-flop DFF02, and when D07 is logic 1, the detection / set stage D & S sets the next flip-flop in the serial shift register DFF03. In this case, the direction detection circuit D & D is not activated. This eliminates the conflict that occurs when both the spread spectrum stage and the fractional-N stage simultaneously attempt to shift the phase in the same direction. When the phase step control signal D02 arrives at the direction detection circuit D & D and the signal D01 is logic 1, the direction detection circuit D & D detects the signal D02 and sets the flip-flop DFF05 in the second shift register. The detection / setting stage D & S is not activated in this case. The flip-flop contents are shifted in the first shift register (DFF01; DFF02; DFF03) or in the second shift register (DFF05; DFF06) every clock period. When the signal D09 output from the flip-flop DFF03 in the first shift register is logic high and the signal D15 output from the flip-flop DFF06 in the second shift register is also logic high, the flip-flop DFF04 in the first shift register and the flip-flop DFF07 in the second shift register at the next clock edge on the negative edge of the clock, a logic 0 and the output of the logic level LOGIC X (hence the input of the interpolator INT) is logic 0. This indicates that there is no phase shift at all if there is a simultaneous shift in the Clockwise and a counterclockwise shift there.

Accordingly, the stage LOGIC X serves to serial-order two phase shift requests occurring at the input of the stage LOGIC X simultaneously. If the fractional-N stage Frac-N requests a phase shift, the request is pushed through the shift registers. After three clock periods, the corresponding phase shift is performed if no conflict occurs. When the stage SSC requests a phase shift, only the second flip-flop of the corresponding shift register is set. Thus, the required phase shift is performed after two clock periods if no conflict occurs. Consequently, when a phase shift is requested from both stages Frac-N and SSC simultaneously, the conflict is automatically eliminated by the differently specified number of clock periods, and the two requested phase shifts are distributed to two consecutive clock periods. However, if the spread spectrum stage SSC requests a phase shift one clock period later than the stage Frac-N, a conflict may occur at the output of the shift register. In this situation, no phase shift is performed. In the context of the present embodiment, the two opposite phase shift requests conflict if they occur simultaneously at the output of the two shift registers rather than at the input. This is due to the different number of clock periods required to pass the requests through the two registers. If the two requests occur in opposite directions simultaneously at the input, two phase shifts can be performed without conflict. Thus, the concurrency of two conflicting requests in the context of the present invention may refer to two requests issued by the respective stages in consecutive clock periods and not in the same clock period. However, in another embodiment with a different architecture, the conflict may occur when the requests are issued in the same clock period. This conflict can then be solved in the same way as with reference to the present embodiment of the invention by performing no phase shift at all. 6 to 8th turn three different situations for the in 4 . 5A and 5B shown embodiment.

6 shows the situation where the spread spectrum logic stage and the fractional-N stage Frac-N simultaneously request a phase shift in the same direction. As a result, the output D13 of the logic stage LOGIC X from the interpolator INT requests a phase change in successive clock periods. 7 shows a situation in which both the spread spectrum logic stage and the fractional N stage Frac-N simultaneously send a phase shift request in different directions. Again, this results in the logic stage LOGIC X requesting from the interpolator INT a phase change in successive clock periods. Thus, the circuit solves the conflict by providing two consecutive phase shifts, as indicated by the two pulses of D13. 8th shows the case where the spread spectrum logic stage and the fractional-N stage Frac-N send phase change requests in consecutive clock periods. In this case, the phase shift is canceled, and the output D13 of the logic stage LOGIC X remains at logic 0.

Claims (4)

A spread spectrum / fractional-N phase locked loop comprising a chain of: a reference clock divider (1 / N), a phase / frequency detector (PFD), a charge pump with a loop filter (CPLF), a voltage controlled oscillator (VCO) providing multiphase output signals, and a feedback loop from the multiphase outputs of the voltage controlled oscillator (VCO) to a feedback input of the phase / frequency detector (PFD); the feedback loop comprising a phase selector (INT), a feedback divider (1 / M) and a control block (CB) having an output which controls the phase selector (INT) to provide a particular phase as an input to the feedback divider (1 / M) selects, contains; wherein the control block (CB) includes: a spread spectrum logic circuit (SSC) receiving an input signal from the output of the phase selector (INT) and providing a direction control output signal and a phase step control signal; a fractional logic circuit (Frac-N) comprising Input signal from the output of the phase selector receives (INT) and provides a phase step control signal, and a logic interface circuit (LOGIC X) that combines: the direction control output signal from the spread spectrum logic stage (SSC) the phase step control signal from the spread spectrum logic stage (SSC) - the phase step control signal from the fractional logic stage (Frac-N) such that: a single phase step control signal is passed to the phase selector (INT) and another phase step control signal is passed to the phase selector (INT) in a subsequent feedback clock period if both the spread spectrum logic circuit (SSC) as well as the F raktional logic circuit (Frac-N) request a phase step in the same direction in the same clock period; and - no phase step control signal is supplied to the phase selector (INT) when the spread spectrum logic circuit (SSC) and the fractional logic circuit (Frac-N) request a phase step in different directions in the same clock period. Spread spectrum / fractional N-phase locked loop according to claim 1, in which the phase selector (INT) contains a phase interpolator. Spread spectrum / fractional N-phase locked loop according to claim 1 or claim 2, wherein the logic interface circuit (LOGIC X) two shift registers clocked by the output of the phase selector contains in which a first one of the shift register inputs for receiving the direction control output signal from the spread spectrum logic circuit (SSC), the phase step control signal from the spread spectrum logic circuit (SSC) and the phase step control signal from the fractional logic circuit (Frac-N), a second one the shift register inputs for the reception the direction control output signal from the spread spectrum logic circuit (SSC) and the phase step control signal from the spread spectrum logic circuit (SSC) has, and the outputs the shift registers are linked to an OR gate to the phase selector To provide phase step control signal. Spread spectrum / fractional N-phase locked loop according to claim 3, in which the second shift register the phase selector Provides direction control signal.