DE102007031278B4 - Nonvolatile memory devices with dummy word lines and related structures and methods - Google Patents

Abstract

A non-volatile memory device comprising: a semiconductor substrate (SUB) having an active area (ACT) on a surface thereof; a first ground selection line (GSL1) crossing the active area (ACT); a first row selection line (SSL1) crossing the active area (ACT) and spaced from the first ground selection line (GSL1); a plurality of memory cell word lines which cross the active area (ACT) between the first ground selection line (GSL1) and the first row selection line (SSL1), with approximately the same first distance (W1) between adjacent ones of the plurality of memory cell word lines (WL) is provided, wherein a second distance (W3) is provided between a last one of the plurality of memory cell word lines (WL2n) and the first row selection line (SSL1), and wherein the second distance (W3) is greater than the first distance (W1) and not is greater than twice the first distance (W1); and a dummy word line (WLd) between word lines (WL) and the first ground selection line (GSL1), where approximately the first distance ...

Description

FIELD OF THE INVENTION

The present invention relates generally to electronics, and more particularly to non-volatile dummy word line memory devices and related structures and methods.

BACKGROUND

Non-volatile memory devices such. B. Flash memory devices may be provided in a NOR type configuration or in a NAND type configuration. For example, NOR type flash memory devices can provide relatively fast random access, while NAND type flash memory devices can provide relatively low cost and / or relatively high integration. Thus, NOR type flash memory devices can be used for code data storage, while NAND type flash memory devices can be used for bulk data storage.

Nonvolatile semiconductor memory devices of the NAND type are e.g. In the US patent US 7,079,437 by Hasama et al. entitled "Nonvolatile Semiconductor Memory Device Having Configuration of NAND Strings with Dummy Memory Cells Adjacent to Select Transistors". More specifically, Hasama et al. a nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected to each other in series. A select gate transistor is connected in series with the serial combination of memory cells, and the memory cell that is adjacent to the select gate transistor is a dummy cell that is not used for data storage. During a data erase operation, the same bias voltage applied to the other memory cells is also applied to the dummy cell.

From the US 2004/0152262 A1 a non-volatile semiconductor memory device is known which has a plurality of word lines arranged in the row direction, a plurality of bit lines arranged in a column direction perpendicular to the word lines, memory cell transistors having a charge storage layer, a plurality of first selection transistors for selecting the memory cell transistors, and a first selection gate line; which is connected to each of the gate electrodes of the first selection transistors. In a specific embodiment of the non-volatile memory device, this is designed as a 32-bit NAND string.

From the US 2006/0139997 A1 For example, a flash memory device is known that has a first group of dummy memory cells arranged between source selection transistors and memory cells coupled to a first word line. The flash memory device further comprises a second group of dummy memory cells arranged between drain selection transistors and memory cells coupled to the last word line.

From the DE 41 23 158 A1 For example, a method is known which can be used to fabricate NAND EEPROMs whose word line width and word line spacing are below the resolution of the available mask pattern.

Notwithstanding known non-volatile memory devices, there continues to be a need in the art for structures and methods that provide more highly integrated memory devices.

SUMMARY

It is an object of the invention to provide a highly integrated non-volatile semiconductor memory device and a method for the production thereof, in which unwanted leakage currents are avoided as far as possible. This object is achieved by a non-volatile memory device according to claim 1 or 9 and by a method according to any one of claims 18, 23 or 29. Further developments of the invention are specified in the subclaims.

BRIEF DESCRIPTION OF THE DRAWINGS

1A FIG. 10 is a top view of a non-volatile memory device according to some embodiments of the present invention. FIG.

1B is a cross-sectional view along a line II 'from 1A ,

1C FIG. 10 is an enlarged cross-sectional view illustrating a mass-induced leakage current during a program operation. FIG.

1D FIG. 12 is an enlarged cross-sectional view illustrating a capacitance coupling during an erase operation. FIG.

2A FIG. 10 is a top view of a non-volatile memory device according to some embodiments of the present invention. FIG.

2 B is a cross-sectional view along section line II-II 'from 2A ,

3A FIG. 10 is a top view of a non-volatile memory device according to some other embodiments of the present invention. FIG.

3B is a cross-sectional view along section line III-III 'from 3A ,

4A FIG. 10 is a top view of a non-volatile memory device according to some other embodiments of the present invention. FIG.

4B is a cross-sectional view along section line IV-IV 'from 4A ,

5A - 5D 12 are cross-sectional views illustrating the operations of forming non-volatile memory devices 2A -B according to embodiments of the present invention.

6A - 6D 12 are cross-sectional views illustrating the operations of forming non-volatile memory devices 3A - 3B according to embodiments of the present invention.

7A - 7D 12 are cross-sectional views illustrating the operations of forming non-volatile memory devices 4A - 4B according to embodiments of the present invention.

DETAILED DESCRIPTION

The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present invention are shown. However, this invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, sizes and relative sizes of layers and regions may be exaggerated for the sake of clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is described as being "on," "connected to," or "coupled to," another element or layer, it is directly connected, coupled, or coupled to the other element or layer may be the other layer or intervening elements or layers may be present. In contrast, when an element is described as "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. As used herein, the term "and / or" includes any and all combinations of the one or more associated listed items.

It will be understood that although the terms first, second, third, etc. are used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections are not limited to these terms should be limited. These terms are used only to distinguish one element, component, region, layer, or portion from another region, layer, or section. Thus, a first element, component, first region, first layer, or first portion, discussed below, could be termed a second element, component, second region, second layer, or second portion, without departing from the teachings of U.S. Patent Nos. 4,314,474 deviate from the present invention.

Spatially relative terms such. "Below," "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element (other elements). or feature (other features) as shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation selected in the figures. For example, if the device is turned upside down in the figures, then elements described as "below" or "beneath" other elements or features would then be "above" the other elements or features. Thus, the exemplary term "under" may include both an orientation above and below. The device may be otherwise oriented (rotated 90 degrees or in any other orientation) and the spatially relative descriptions used herein interpreted accordingly. In addition, as used herein, "lateral" refers to a direction that is substantially orthogonal to a vertical direction.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used herein, the singular forms "a" and "the" are meant to include the plural forms unless the context says clearly different. It will as well it is to be understood that the terms "comprises" and / or "comprising" when used in this specification specify the presence of the specified features, numbers, steps, acts, elements and / or components, but not the presence or addition of any or several other features, numbers, steps, acts, elements, components and / or groups thereof.

Embodiments of the present invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (intermediate structures) of the invention. As such, deviations from the forms of representations as a result of z. B. manufacturing techniques and / or tolerances expected. Thus, the embodiments of the present invention should not be construed as limited to the particular forms of the ranges set forth herein, but are intended to indicate deviations of shapes as a result of e.g. As the production include. For example, an implanted region shown as a rectangle will typically have rounded or rounded features and / or a gradient of implant concentration at its edges, rather than a binary change from the implanted to the unimplanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which implantation takes place. Thus, the areas shown in the figures are of a schematic nature and their shapes are not intended to depict the true shape of a portion of a device and are not intended to limit the scope of the present invention.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such. For example, those commonly used in dictionaries are to be interpreted as having a meaning consistent with their meaning in the present description and in the context of the related art, and will not be interpreted in an idealized or highly formal sense Sense, except as expressly defined herein.

As in 1A and 1B As shown, a flash memory device may include a plurality of parallel active regions ACT in a semiconductor substrate separated by device isolation layers. In addition, ground select lines GSL, row select lines SSL and word lines WL may cross the active areas ACT. In particular, a respective charge storage gate may be provided between each word line WL and each active area ACT for providing a respective memory cell at each intersection of a word line WL with an active area ACT. Moreover, a plurality of memory cells along an active area ACT between a ground select line GSL and a row select line SSL may define a memory cell row. As in further 1A and 1B As shown, adjacent memory cell rows may be separated by two ground select lines GSL or by two row select lines SSL.

As in the enlarged cross section views 1C and 1D As shown, a gate insulating film GIL may be provided between the ground select line GSL and the active region ACT of the semiconductor substrate SUB. In addition, a charge storage gate CSG may be provided between the word line WL1 and the active area ACT of the substrate SUB, a tunnel insulating layer TIL may be provided between the charge storage gate CSG and the active area ACT, and a barrier insulating layer BIL may be provided between the charge storage gate CSG and the word line WL1 be.

During a programming operation (for a memory cell other than the one in 1C 0 volts may be applied to the ground select line GSL, and a continuity voltage Vpass may be applied to the unselected word line WL1 as shown in FIG 1C is shown. In addition, a program voltage Vpgm may be applied to a selected word line (not shown) corresponding to a memory cell to be programmed (memory cells to be programmed). Thus, a gate voltage of the ground select transistor (defined by the ground select line GSL and gate insulating layer GIL) may be 0 volts, while a drain voltage of the ground select transistor may be about 10 volts, resulting in a gate current leakage current GIDL.

During an erase operation, ground select line GSL may be allowed to float, and an erase voltage vers of about 20 volts may be applied to a p-well of substrate SUB, and 0 volts may be applied to word line WL1, as in FIG 1D shown. Accordingly, the erase voltage V s applied to the p-well can increase a potential of the ground select line GSL, and a potential of the charge storage gate CSG (adjacent to the ground select line GSL) may vary due to the capacitive coupling Cp between the ground select line GSL and the Charge storage rate CSG increase. An undesired erase fault can thus result at the charge storage gate CSG and / or the word line WL1.

2A Fig. 10 is a plan view of a non-volatile memory device 20 (such as a flash memory device) according to some embodiments of the present invention, and 2 B is a cross-sectional view along section line II-II 'from 2A , The flash memory device 20 , a plurality of parallel active regions ACT may be included in a semiconductor substrate SUB separated by device insulating layers. In addition, _{ground select lines} GSL _0-2 , _{row select lines} SSL _0-2 , dummy word lines WL _d, and memory cell word lines WL _1-2n (where n is an integer) may cross the active areas ACT. In particular, a respective charge storage _gate may be provided between each memory cell word line WL _1-2n and each active area ACT to provide a respective memory cell at each intersection of a memory cell word line WL _1-2n with an active area ACT. Similarly, a charge storage gate may be provided between each dummy word line WL _d and the active area ACT, so that the structures of the dummy word lines WL _d and the memory cell word lines WL _{1-2n are} the same.

An even number of memory cell word lines WL _1-2n along an active area ACT between a _{ground select} line GSL and a _{row select} line SSL (eg, between GSL ₁ and SSL ₁ ) may define a memory cell array having an even number of memory cells. As further in the 2A - B, adjacent memory cell rows may be separated by two ground select lines GSL (eg GSL ₀ and GSL ₁ ) or by two row select lines SSL (eg SSL ₁ and SSL ₂ ). More specifically can 2 ^k (where k is a positive integer) memory cell word lines WL _1-2n define a row of memory cells with 2 ^k used for storing data memory cells. However, the dummy word line WL _d is not used for storing data.

In addition, an array of memory cell word lines WL _1-2n and a dummy word line WL _d of adjacent memory cell rows may have mirror symmetry. For example, an array of memory cell word lines WL _1-2n and dummy word lines WL _d between _{ground select line} GSL ₀ and _{row select line} SSL _{0 may have} mirror symmetry relative to an array of memory cell word lines WL _1-2n and dummy word line WL _d between Mass selection line GSL ₁ and the series selection line SSL ₁ own. Similarly, an arrangement of memory cell word lines WL _1-2n and dummy word line WL _d between _{ground select line} GSL ₁ and _{row select line} SSL _{1 may} mirror symmetry relative to an array of memory cell word lines WL _1-2n and dummy word line WL _d the ground selection line GSL ₂ and the row selection line SSL ₂ have.

By providing a dummy word line WL _d between a ground select line GSL and a first memory cell word line WL _{1 of} a memory cell row, a ground-induced leakage current and / or an erase fault on the first memory cell word line WL _{1 can be} reduced. Moreover, a controller of the nonvolatile memory device may be connected to the ground select lines, the row select lines, the memory cell word lines, and the dummy word lines. During an erase operation, the controller z. B. configured to enable the ground select lines GSL ₁ to float applying an erase voltage vers of about 20 volts to a p-well of the substrate SUB and to _apply 0 volts to the memory cell word lines WL _1-2n , In addition, the controller may be configured to apply a bias voltage Vb to the dummy word line WL _d , where the bias voltage Vb is between a supply voltage Vcc and a pass voltage Vpass (ie, Vcc <Vb <Vpass) to thereby provide an erase fault in the first memory cell word line WL ₁ and / or reduced at respective charge storage layers.

During a write (or program) operation, the controller may be configured to apply the supply voltage Vcc to the ground select line GSL ₁ , to apply 0 volts to a p-well of the substrate SUB, to apply a pass voltage Vpass to the applying undelected word lines, and applying a programming voltage Vpgm to the selected word line. In addition, the controller may be configured to apply a bias voltage Vd to the dummy word line WL _d , where the bias voltage Vb between the supply voltage Vcc and the through voltage is Vpass (ie, Vcc <Vbc <Vpass) thereby to be ground-induced To reduce leakage current at the adjacent to the dummy word line ground selection line.

As in the 2A 3B, the dummy word line WL _d and each of the memory cell word lines WL ₁ to WL _{2n may be} approximately equal in width F ₁ . In addition, about a same width / spacing W _{1 may separate} a gate select line GSL and an adjacent dummy word line WL _d , approximately the same width / spacing W ₁ may include a dummy word line WL _d and an adjacent first memory cell word line WL ₁ , can be about the same width / the the same distance W _{1 separate} adjacent memory cell word lines WL _x and WL _{x + 1} , and approximately the same width / spacing W _{1 may separate} one last memory cell word line WL _2n and an adjacent row select line SSL. Moreover, the widths F ₁ and W _{1 may be} approximately equal and, in particular, each of the widths F ₁ and W _{1 may be} about one quarter (1/4) of a period P ₁ that is _even and WL _even by adjacent even memory cell word lines WL ₊₂ (ie even memory cell word lines, which are separated by only an odd memory cell word line) is defined or _umgerade by adjacent odd memory cell word lines WL and WL _{umgerade + 2} (ie, odd memory cell word lines by only an even memory cell Word line are separated) is defined. As further in the 2A B-B, adjacent ground select lines GSL ₀ and GSL _{1 may be} separated by approximately one width W ₂ , and adjacent row select lines SSL ₀ and SSL _{1 may be} separated by approximately the same width / distance W ₂ . The width W ₂ may be at least about 3 times larger than the width W ₁ .

Each memory cell word line WL ₁ to WL _2n may thus have a respective control electrode for a nonvolatile memory cell (such as a flash memory cell) of a memory cell array on a same active area ACT between a ground select line (eg, GSL ₁ ). and a row select line (e.g., SSL ₁ ). Each non-volatile memory cell may further include a charge storage layer between the respective memory cell word line and the active region, a tunnel insulating layer between the active region and the charge storage layer, and a barrier insulating layer between the memory cell word line and the charge storage layer.

Each dummy word line WL _d may have a construction similar to that discussed above with respect to the memory cell word lines (having a tunnel insulating layer, a charge storage layer, and a barrier insulating layer between each dummy word line and respective active regions). However, the dummy cell word lines (and associated tunnel insulating layers, charge storage layers, and barrier insulating layers) are not used to store data, but instead are designed to reduce bulk induced leakage current on adjacent ground select lines during programming operations and / or to reduce the erase bias on the adjacent memory cells during erase operations ,

The pattern of the ground select lines GSL, the dummy word lines WL _d , the memory cell word lines WL ₁ to WL _2n, and the row selection lines SSL may be formed using self-aligned double patterning as discussed in more detail below. For example, the ground selection lines GSL, the row selection lines SSL and the odd memory cell word lines (WL ₁ , WL ₃ , WL ₅ , ..., WL _2n-1 ) may be formed according to a pattern of a photolithography mask, and the dummy word lines WL _d and the even memory cell word lines (WL ₂ , WL ₄ , WL ₆ , ..., WL _2n ) are formed using self-aligned double patterning.

According to some embodiments of the present invention, which are incorporated in the 2A 1B, a first memory cell row on the active area (ACT) may include a first plurality of memory cell word lines WL ₁ to WL _2n crossing the active area ACT between the first ground select line GSL ₁ and the first row select line SSL ₁ , And about a same first distance W ₁ may be provided between adjacent ones of the first plurality of word lines. In addition, a second memory cell row on the active area ACT may include a second plurality of word lines WL ₁ to WL _2n crossing the active area ACT between a second ground select line GSL ₀ and a second row select line SSL ₁ , and about the same first distance WL ₁ may be provided between adjacent ones of the second plurality of word lines. Specifically, the first ground select line GSL _{1 may be} between the second ground select line GSL ₀ and the first plurality of word lines, and the second ground select line GSL ₀ may be between the first ground select line GSL ₁ and the second plurality of word lines. In addition, portions of the active region ACT between the first and second ground selection lines GSL ₁ and GSL _{0 may be} free of word lines, and the second distance W ₂ between the first and second ground selection lines GSL ₁ and GSL ₀ may be at least about three times larger than that be first distance W ₁ . For example, the second distance W _{2 may be} between about three to four times greater than the first distance W ₁ , and more specifically, the second distance W _{2 may be} more than three times greater than the first distance W ₁ and in particular more than four times greater than the first distance W Be ₁ .

In addition, the dummy word line WL _{d may be} between the first memory cell word line WL ₁ and the first ground select line GSL ₁ , and approximately the same first distance W ₁ may be provided between the first ground select line GSL ₁ and the dummy word line WL _d . About the same first distance W ₁ can also be provided between the dummy word line WL _d and the first memory cell word line WL ₁ and between the last memory cell word line WL _2n-1 and the row selection line SSL ₁ .

The 5A D are cross-sectional views illustrating the operations of forming the nonvolatile memory structures from FIGS 2A B using self aligned dual pattern according to some embodiments of the present invention. As in 5A a substrate can be shown 50 an etching target layer 52 contained on it, and can the etching target layer 52 Layers of materials include those used to form the memory cells, word lines, select transistors, and select lines 2A -B be used.

Specifically, the target layer may be a tunnel insulating layer (such as a layer of silicon oxide), a charge storage gate layer (such as a layer of polysilicon or silicon nitride), a barrier insulating layer (such as a layer of silicon oxide or other dielectric material, e.g. different from the charge storage gate layer) as well as a conductive layer (such as a layer of polysilicon and / or metal). The charge storage layer may be between the conductive layer and the substrate, wherein the tunnel insulating layer separates the charge storage layer and the substrate, and wherein the barrier insulating layer separates the charge storage layer and the conductive layer. In addition, a first hard mask layer 55 on the etching target layer 52 are formed, and the first hard mask layer 55 may be a silicon nitride layer 56 on a pad oxide layer 54 contain.

A photoresist layer on the first hardmask layer 55 can using the photomask 100 be patterned such that the photoresist pattern 58 with odd word line photoresist patterns 58w , Earth selection line photoresist patterns 58g and row selection line photoresist patterns 58s provided. More precisely contains the photomask 100 a photomask pattern 104 on a transparent substrate 102 , The photomask pattern 104 may have odd wordline photomask patterns 104w representing the odd word line photoresist patterns 58w Corresponds to ground selection photo-mask pattern 104g picking up the ground array photo resist patterns 58g and row select line photomask patterns 104s patterning the row selection line photoresist 58s correspond, included.

As in further 5A may show adjacent odd word line photomask patterns 104w be spaced apart by about a distance W ₁₁ , and may have adjacent odd word line photoresist patterns 58w be spaced apart by about the width / distance W ₁₁ . A first of the odd wordline photomask patterns 104w may be from an adjacent ground select line photomask pattern 104g by about the distance W ₁₁ and a last one of the odd word line photomask patterns 104w may be from an adjacent row select line photomask pattern 104s be spaced by about the width / distance W ₁₁ . Likewise, a first of the odd word line photoresist patterns may be used 58w from an adjacent ground select line photoresist pattern 58g may be spaced by about the distance W ₁₁ , and may be a last one of the odd word line photomask patterns 58w from an adjacent row select line photomask pattern 58s be spaced by about the width / distance W ₁₁ .

In addition, each of the odd word line photomask patterns 104w and each of the odd wordline photoresist patterns 58w have a width of about F ₁ , and the width / distance W ₁₁ may be about three times the width F ₁ . In addition, adjacent ones of the odd word line photomask patterns may be used 104w and adjacent the odd word line photoresist patterns 58w define a period P ₁ , and the period P ₁ may be about four times the width F ₁ . The width F ₁ may be a minimum feature size available in the photolithography technique used. Neighboring ground selection line photomask patterns 104g adjacent row select line photomask patterns 104s , neighboring ground selection line photoresist patterns 58g and adjacent row select line photoresist patterns 58s may be separated by a width W ₂ , and the width W ₂ may be greater than four times the width F ₁ . In addition, the second distance W _{2 may be} at least three times greater than the first distance W ₁ . For example, the second distance W _{2 may be} between about three and four times greater than the first distance W ₁ , and in particular, the second distance W _{2 may be} three times greater than the first distance W ₁ , and more specifically, more than four times greater than the first distance W ₂ Distance W ₁ .

More specifically, a continuous photoresist layer may pass through the photomask 100 be selectively exposed to radiation and then developed to provide the photoresist pattern 58 out 5A , Accordingly, an arrangement of the resist pattern becomes 58 by an arrangement of the photomask pattern 104 Are defined. In addition, the photoresist pattern corresponds 58 a pattern of gate select lines, row select lines, and odd word lines described above with respect to FIGS 2A -B were discussed.

Sections of the first hard mask layer 55 (with the silicon nitride layer 56 and the pad oxide 54 ) passing through the photoresist pattern 58 can be selectively removed (eg, by dry etching) to provide a first hard mask pattern 60 (with ground selection hardmask patterns 60g , Row selection line hard mask patterns 60s and odd wordline hardmask patterns 60w ), as in 5B is shown. When the first hard mask layer 55 separate send 54 and 56 can contain any element of the first hardmask pattern 60 also separate layers 54 and 56 contain. Approximately an equal distance / an equal width W ₁₁ may be provided between a ground select line hard mask pattern 60g and a first odd wordline hardmask pattern 60w , between adjacent odd word line hardmask patterns 60w , as well as between a last odd word line hard mask pattern 60w and a row select line hard mask pattern 60s , Each element of the first hardmask pattern 60 may contain a layer of silicon nitride and / or silicon oxide. After selectively removing portions of the first hardmask layer, the photoresist pattern may 58 be removed.

As in further 5B a victim mask layer can be shown 62 on the first hardmask pattern 60 and on portions of the etch target layer 52 formed by the first hard mask pattern 60 are exposed, and the victim mask layer 62 and the first hard mask pattern 60 can include different materials. For example, upper layers can 56 of the first hard mask pattern 60 a layer of silicon nitride, and the sacrificial mask layer 62 may be a layer of polysilicon. In addition, a thickness of the sacrificial mask layer 62 be provided such that: gaps between portions of the sacrificial mask layer 62 on sidewalls of adjacent ones of the odd word line hardmask patterns 60w stay; Gaps between sections of the victim mask layer 62 on sidewalls of adjacent ground select line hard mask patterns 60g stay; Gaps between sections of the victim mask layer 62 on sidewalls of adjacent row select line hardmask patterns 60s stay; Gaps between sections of the victim mask layer 62 on sidewalls of adjacent select line hardmask patterns 60g and first odd wordline hardmask patterns 60w stay; as well as gaps between sections of the victim mask layer 62 on sidewalls of adjacent select line hardmask patterns 60s and last odd word line hard mask patterns 60w stay.

A thickness of the sacrificial mask layer 62 on sidewalls of the first hard mask patterns 60w . 60g and 60s can be approximately equal to the width / distance W ₁ between adjacent word lines WL _x and WL _{n + 1} , which in 2A -B are shown. A distance / a distance between sections of the sacrificial mask layer 62 on adjacent odd wordline mask patterns 60w remaining gap may be approximately equal to a width F _{1 of} a straight word line WL ₂ , WL ₄ , ..., WL _2n , which in the 2A -B are shown.

After forming the sacrificial mask layer 62 may be a second hardmask layer 64 on the sacrificial mask layer 62 be formed, as further in 5B is shown. In addition, the second hard mask layer 64 may be a layer of silicon oxide, and may be the second hardmask layer 64 have a thickness which is at least half of the width F ₁ , thereby leaving gaps in the sacrificial mask layer 62 between odd wordline hardmask patterns 60w to fill. Because wider gaps between adjacent ground select line hard mask patterns 60g and between adjacent row select line hardmask patterns 60s can be provided, however, gaps 68 in the second hardmask layer 64 remain. When a thickness of the second hard mask layer 64 is about the width F _{1 of} a word line, adjacent ground select line patterns 60g and adjacent row selection line patterns 60s separated by a distance / distance of more than four times F ₁ .

The second hard mask layer 64 may then be subjected to an etch-back operation to remove portions of the hardmask layer 64 between adjacent ground select line hard mask patterns 60g , between adjacent row select line hardmask patterns 60s and upper surfaces of the sacrificial mask layer 62 , as in 5C is shown. After the etch-back operation, remaining portions of the second hard mask layer remain 64 can thus have about the thickness F ₁ . More specifically, after the etch back process, remaining portions of the second hard mask layer may be left 64 a second hard mask pattern 70 on the sacrificial mask layer 62 define. The second hard mask pattern 70 can be a dummy word line pattern 70d between the ground selection line pattern 60g and the first odd word line pattern 60w as well as straight word line pattern 70w between adjacent odd word line patterns 60w and between the last odd word line pattern 60w and the row selection line pattern 60s contain.

Exposed sections of the sacrificial mask layer 62 can then be removed (eg by dry etching) as in 5D is shown for exposing portions of the etching target layer 52 not from the first and / or second hardmask patterns 60 and or 70 are covered. exposed Portions of the etch target layer 52 can then be removed (eg, by dry etching) using the first and second hardmask patterns 60 and 70 are used as an etching mask, and the first and second hardmask patterns 60 and 70 can then be removed to provide the structure from the 2A -B.

3A Fig. 10 is a plan view of a nonvolatile memory device 30 (such as a flash memory device) according to some embodiments of the present invention, and 3B is a cross-sectional view along the section line II-II 'from 3A , The flash memory device 30 may include a plurality of parallel active regions ACT in a semiconductor substrate SUB separated by device isolation layers. In addition, _{ground select lines} GSL _0-2 , _{row select lines} SSL _0-2 , dummy word lines WL _d, and memory cell word lines WL _1-2n (where n is an integer) may cross the active areas ACT. More specifically, a respective charge storage _gate may be provided between each memory cell word line WL _1-2n and each active area ACT for providing a respective memory cell at each intersection of a memory cell word line WL _1-2n with an active area ACT. Similarly, a charge storage gate may be provided between each dummy word line WL _d and the active area ACT, so that the structures of the dummy word lines WL _d and the memory cell word lines WL _{1-2n are} the same.

An even number of memory cell word lines WL _1-2n along an active area ACT between a _{ground select} line GSL and a _{row select} line SSL (eg, between GSL ₁ and SSL ₁ ) may define a memory cell array having an even number of memory cells. As further in the 3A -B adjacent memory cell rows may be separated by two ground select lines GSL (eg GSL ₀ and GSL ₁ ) or by two row select lines SSL (eg SSL ₁ and SSL ₂ ). More specifically can 2 ^k (where k is a positive integer) memory cell word lines WL _1-2n define a memory cell row with 2 ^k used for storing data memory cells. However, the dummy word line WL _d is not used for storing data.

In addition, an array of memory cell word lines WL _1-2n and a dummy word line WL _d of adjacent memory cell rows may have mirror symmetry. For example, an arrangement of memory cell word lines WL _1-2n and a dummy word line WL _d between _{ground select line} GLS ₀ and _{row select line} SSL _{0 may} mirror symmetry relative to an array of memory cell word lines WL _1-2n and a dummy word line WL _d the ground selection line GSL ₁ and the row selection line SSL ₁ have. Similarly, an arrangement of memory cell word lines WL _1-2n and a dummy word line WL _d between _{ground select line} GSL ₁ and _{row select line} SSL _{1 may} mirror symmetry relative to an array of memory cell word lines WL _1-2n and a dummy word line WL _d the ground selection line GLS ₂ and the row selection line SSL ₂ have.

By providing a dummy word line WL _d between a ground select line GSL and a first memory cell word line WL _{1 of} a memory cell row, a ground-induced leakage current and / or an erase fault on the first memory cell word line WL _{1 can be} reduced. In addition, a controller of the nonvolatile memory device may be connected to the ground select lines, the row select lines, the memory cell word lines, and the dummy word lines. During an erase operation, the controller z. B. may be configured to allow the ground selection line GSL ₁ to float an erase voltage Ver of about 20V to a p-well of the substrate SUB and to _apply 0V to the memory cell word lines WL _1-2n become. In addition, the controller may be configured such that a bias voltage Vb is applied to the dummy word line WL _d , where the bias voltage Vb is between a supply voltage Vcc and a continuity voltage Vpass (ie, Vcc <Vb <Vpass), thereby canceling the erase first memory cell word line WL ₁ and / or at respective charge storage layers.

During a write (or program) operation, the controller may be configured to apply the supply voltage Vcc to the ground select line GSL _1, apply 0 V to a p-well of the substrate SUB to apply a pass voltage Vpass to the unselected word lines is applied, and that it applies a programming voltage Vpgm to the selected word line. In addition, the controller may be configured to apply a bias voltage Vb to the dummy word line WL _d , where the bias voltage Vb is between the supply voltage Vcc and the through voltage Vpass (ie, Vcc <Vb <Vpass), thereby indicating the ground-induced leakage current of the ground select line adjacent to the dummy word line.

As in the 3A 3B, the dummy word lines WL _d and each of the memory cell word lines WL ₁ to WL _{2n may be} approximately equal in width F ₁ . In addition, about an equal width / distance W, a dummy word line WL _d and an adjacent first one may be used Memory cell word line WL ₁ separate, and can about the same width / the same distance W ₁ adjacent memory cells / word lines WL _x and WL _{x + 1} separate. Moreover, the widths F ₁ and W _{1 may be} approximately equal, and in particular, each of the widths F ₁ and W _{1 may be} about one quarter (1/4) of a period P ₁ caused by adjacent even memory cell word lines WL _even and WL _{even +2} (ie, the even memory cells / wordlines that are only separated by an odd memory cell wordline) or _{odd + 2} by adjacent odd memory cell wordlines WLungerade WL (ie, the odd memory cell wordlines that are driven only by even memory cells Word line are separated) is defined.

As further in the 3A - B, adjacent ground select lines GSL ₀ and SL _{1 may be} separated by approximately one width W ₂ , and adjacent row select lines SSL ₀ and SSL _{1 may be} separated by the same width W ₂ . In addition, the second width / the second distance W _{2 may be} at least about three times greater than the distance W ₁ . For example, the second distance W _{2 may be} between about three and four times greater than the first distance W ₁ , and more specifically the second distance W _{2 may be} more than three times greater than the first distance W _1, and more specifically more than four times greater than the first distance W ₂ Be distance W ₁ . In addition, a width W _{3 may separate} a gate select line GSL and an adjacent dummy word line WL _d , and may have about the same width / spacing W ₃ a last memory cell word line WL _2n and an adjacent row select line SSL separate. The width / the distance W ₃ can be greater than the width / the distance W ₁ and less than two times of W ₁ (ie, W ₁ <W ₃ <2 × W _1), and more specifically, the width / the distance W _{3 is} greater than 1.5 times the width W ₁ and less than twice W ₁ (ie, 1.5 x W ₁ <W ₃ <2 x W ₁ ).

Each memory cell word line WL ₁ to WL _2n may thus have a respective non-volatile memory cell (eg, a flash memory cell) control gate of a memory cell array on a same active area ACT between a ground select line (eg, GLS ₁ ) and a row select line (eg, SSL ₁ ). Each non-volatile memory cell may further include a charge storage layer between the respective memory cell word line and the active region, a tunnel insulating layer between the active region and the charge storage layer, and a barrier insulating layer between the memory cell word line and the charge storage layer.

Each dummy word line WL _d may have a similar structure as discussed above with respect to the memory cell word lines (having a tunnel insulating layer, a charge storage layer, and a barrier insulating layer between each dummy word line and respective active regions). However, the dummy cell wordlines and the corresponding tunneling insulating layers, charge storage layers and barrier insulating layers do not store data, but instead are designed to reduce the ground induced leakage current on the adjacent ground select line during programming operations and / or to reduce the erase bias on the adjacent memory cell during erase operations ,

The pattern of ground select lines GSL, dummy word lines WL _d , memory cell word lines WL ₁ to WL _2n, and row select lines SSL may be formed using self-aligned dual pattern as described in more detail below. For example, the ground select lines GSL, the row select lines SSL, the dummy word lines WL _d and the even memory cell word lines (WL ₂ , WL ₄ , WL ₆ ... WL _2n ) may be formed according to a pattern of a photolithography mask, and may be the odd memory cells Word lines (WL ₁ , WL ₃ , WL ₅ ... WL _2n-1 ) are formed using the self-aligned double pattern.

According to some embodiments of the present invention, which are incorporated in the 3A 1B, a first memory cell row on an active area ACT may include a first plurality of word lines WL ₁ to WL _2n crossing the active area ACT between a first ground select line GSL ₁ and a first row select line SSL ₁ , and may be approximately a same first distance W _{1 may be provided} between adjacent ones of the first plurality of word lines WL ₁ to WL _2n . A second memory cell row on the active area ACT may include a second plurality of word lines WL ₁ to WL _2n crossing the active area ACT between a second ground select line GSL ₀ and a second row select line SSL ₀ , and about the same first distance W ₁ may be provided between adjacent ones of the second plurality of word lines WL ₁ to WL _2n . The first ground select line GSL ₁ may be between the second ground select line GSL ₀ and the first plurality of word lines, and the second ground select line GSL ₀ may be between the first ground select line GSL ₁ and the second plurality of word lines. In addition, sections of the active area ACT between the first and second ground selection lines GSL ₁ and GSL _{0 are} free of word lines, and a second distance W ₂ between the first and second ground selection lines GSL ₁ and GSL _{0 may be} at least about three times larger than the first distance W ₁ . For example, the second distance W _{2 may be} between about three and four times greater than the first distance W ₁ , and more specifically, the second distance W _{2 may be} more than three times greater than the first distance W ₁ and, more specifically, more than four times greater than the first distance W ₂ Be distance W ₁ .

In addition, the first plurality of word lines WL ₁ to WL _2n may include an even number of memory cell word lines, and a dummy word line WL _{d may be provided} between a first one of the memory cell word lines WL ₁ to WL _2n and the ground select line GSL ₁ . About the same first distance W ₁ may be provided between the dummy word line WL _d and the first one of the memory cell word lines WL ₁ to WL _2n . In addition, a third distance W _{3 may be provided} between the ground selection line GSL ₁ and the dummy word line WL _d , and the third distance W _{3 may be} greater than the first distance W ₁ and not greater than twice the first distance W ₁ ( ie W ₁ <W ₃ <2 × W ₁ ).

The 6A D are cross-sectional views illustrating the operations of forming nonvolatile memory structures from the 3A B using self-aligned dual pattern according to some embodiments of the present invention. As in 6A a substrate can be shown 150 an etching target layer 152 contained on it, and can the etching target layer 152 Layers of materials included for forming the memory cells, word lines, select transistors, and select lines 3A -B be used.

More specifically, the etching target layer 152 a tunnel insulating layer (such as a layer of silicon oxide), a charge storage gate layer (such as a layer of polysilicon or silicon nitride), a barrier insulating layer (such as a layer of silicon oxide or another layer different from the charge storage gate layer) -electric material), as well as a conductive layer (such as a layer of polysilicon and / or metal). The charge storage layer may be between the conductive layer and the substrate, wherein the tunnel insulating layer separates the charge storage layer and the substrate, and wherein the barrier insulating layer separates the charge storage layer and the conductive layer. In addition, a first hard mask layer 155 on the etching target layer 152 may be formed, and may be the first hard mask layer 155 a silicon nitride layer 156 on a pad oxide layer 154 contain.

A photoresist layer on the first hardmask layer 155 can using the photomask 200 patterned to provide the photoresist pattern 158 with dummy word line photoresist patterns 158d , straight word line photoresist patterns 158W , Earth selection line photoresist patterns 158g and row selection photoresist patterns 158s , More precisely, the photomask 200 a photomask pattern 204 on a transparent substrate 202 contain. The photomask pattern 204 may be dummy wordline photomask pattern 204d patterning the dummy word line photoresist patterns 158d correspond to, just word line photomask patterns 204w , the straight word line photoresist patterns 158W Corresponds to ground selection photo-mask pattern 204g , the earth selection line photoresist patterns 158g correspond as well as row select line photomask patterns 204s , the row selection line photoresist patterns 158s correspond, included.

As in further 6A may show adjacent even wordline photomask patterns 204w may be spaced apart by a width W ₁₁ , and may include adjacent even word line photoresist patterns 158W be spaced by about the width / distance W ₁₁ . A first one of the even wordline photomask patterns 204w may be from an adjacent dummy wordline photomask pattern 204d be spaced apart by about the width W ₁₁ and a first one of the even word line photoresist patterns 158W may be from an adjacent dummy wordline photoresist pattern 158d be spaced by about the width / distance W ₁₁ . A dummy word line photomask pattern 204d may be from an adjacent ground select line photomask pattern 204d by a distance W ₃ , and a last one of the even word line photoresist patterns 204w may be from an adjacent row select line photomask pattern 204s be spaced by about the width / the distance W ₃ . Likewise, a dummy wordline photoresist pattern may be used 158d from an adjacent ground select line photoresist pattern 158g ₃ be spaced by about the width / the distance W, and may be a last word line of the straight photomask pattern 158W from an adjacent row select line photomask pattern 158s be spaced by about the width / the distance W ₃ .

In addition, each of the even word line photomask patterns 204w and each of the even wordline photoresist patterns 158W have a width of about F ₁ , and the width / distance W _{3 may be} in the range of at least about the width F ₁ to not greater than about twice the width F ₁ (F ₁ ≦ W ₃ ≦ 2 × F ₁ ) be. In addition, adjacent ones of the even word line photomask patterns may be used 204w and adjacent to the even word line photoresist patterns 158W define a period P ₁ , and the period P _{1 may be} about four times the width F ₁ . The width F ₁ may be a minimum feature size available for the photolithography technique used. Neighboring ground selection line photomask patterns 204g adjacent row select line photomask patterns 204s , neighboring ground selection line photoresist patterns 158g and adjacent row select line photoresist patterns 158s may be separated by a width W ₂ , and the width W ₂ may be greater than three times the width F ₁ . For example, the second distance W _{2 may be} between about three and four times greater than the first distance W ₁ , or the second distance W _{2 may be} more than three times greater than the first distance W ₁ , and more particularly more than four times greater than the first distance W ₂ Be distance W ₁ .

More specifically, a continuous photoresist layer may pass through the photomask 200 selectively exposed and then developed to provide the photoresist pattern 158 out 6A , Accordingly, an arrangement of the resist pattern becomes 158 by an arrangement of the photomask pattern 204 Are defined. In addition, the photoresist pattern corresponds 158 a pattern of gate select lines, row select lines, and even word lines described above with reference to FIGS 3A -B were discussed.

Sections of the first hard mask layer 155 (with the silicon nitride layer 156 and the pad oxide layer 154 ) passing through the photoresist pattern 158 can be selectively removed (eg, by dry etch) to form a first hard mask pattern 160 (with ground selection hardmask patterns 160g , Row selection line hard mask patterns 160s , Dummy wordline hardmask patterns 160d and even wordline hardmask patterns 160w ) as in 6B to provide shown. When the first hard mask layer 155 separate layers 154 and 156 Also, any element of the first hardmask pattern may contain 160 separate layers 154 and 156 contain. Approximately an equal distance / an equal width W ₁₁ may be provided between a dummy word line hard mask pattern 160d and a first straight wordline hardmask pattern 160w , as well as between adjacent even wordline hardmask patterns 160w , Approximately the same distance / width W ₃ may be provided between a ground select line hard mask pattern 160g and a dummy wordline hardmask pattern 160d and between a last even wordline hardmask pattern 160w and a row select line hard mask pattern 160s , Each element of the first hardmask pattern 160 may contain a layer of silicon nitride and / or silicon oxide. After selectively removing portions of the first hardmask layer, the photoresist pattern may 158 be removed.

As in further 6B can show a sacrificial mask layer 162 on the first hardmask pattern 160 and on portions of the etch target layer 152 passing through the first hard mask pattern 160 are exposed, and the sacrificial mask layer 162 and the first hard mask pattern 160 can include different materials. For example, upper layers can 156 of the first hard mask pattern 160 may be a layer of silicon nitride, and may be the sacrificial mask layer 152 be a layer of polysilicon. In addition, a thickness of the sacrificial mask layer 162 be provided so that: between sections of the sacrificial mask layer 162 on sidewalls of adjacent ones of the even wordline hardmask patterns 160w Gaps remain; between sections of the victim mask layer 162 on sidewalls of adjacent ground select line hard mask patterns 160g Gaps remain; between sections of the victim mask layer 162 on sidewalls of adjacent row select line hardmask patterns 160s Gaps remain; and between sections of the victim mask layer 162 on sidewalls of adjacent dummy wordline hardmask patterns 160d and first straight wordline hardmask patterns 160w Gaps remain. However, the sacrificial mask layer 162 Gaps between ground select line hard mask patterns 160g and dummy wordline hardmask patterns 160d fill, and may be the sacrificial layer 162 Gaps between a last one of the even wordline hardmask patterns 160w and an adjacent row select line hard mask pattern 160s to fill.

A thickness of the sacrificial mask layer 162 on sidewalls of the first hard mask patterns 160d . 160w . 160g and 160s can be approximately equal to the width / distance W ₁ between adjacent word lines WL _x and WL _{x + 1} , which in the 3A -B are shown. A distance / a distance between sections of the sacrificial mask layer 162 on adjacent even wordline mask patterns 160w remaining gap may be approximately equal to a width F _{1 of} an odd word line WL ₁ , WL ₃ , ... WL _2n-1 shown in Figs.

After the pictures of the sacrificial mask layer 162 may be a second hardmask layer 164 on the sacrificial mask layer 162 be formed, as further in 6B is shown. In addition, the second hard mask layer 164 may be a layer of silicon oxide, and may be the second hardmask layer 164 have a thickness that is at least half of the width F ₁ , thereby leaving gaps in the sacrificial mask layer 162 between odd wordline hardmask patterns 160w to fill. Because wider gaps between the adjacent ground line Hartmaskenmustern 160g and between adjacent row select line hardmask patterns 160s intended but there are gaps 168 in the second hardmask layer 164 remain. When a thickness of the second hard mask layer 164 is about the width F _{1 of} a word line, adjacent ground select line patterns 160g and adjacent row selection line patterns 160s separated by a distance / distance of more than four times F ₁ .

The second hard mask layer 164 can then be etched back to remove portions of the hardmask layer 164 between adjacent ground select line hard mask patterns 160g , between adjacent row select line hardmask patterns 160s and upper surfaces of the sacrificial mask layer 162 , as in 6C is shown. After etching back remaining portions of the second hard mask layer 164 can therefore have about the thickness F ₁ . More specifically, portions of the second hardmask layer 164 remaining after etching back, a second hard mask pattern 170 on the sacrificial mask layer 162 define. The second hard mask pattern 170 may have odd word line patterns 170w between adjacent even wordline patterns 160w and between the last odd word line pattern 160w and the row selection line pattern 160s contain.

Exposed sections of the sacrificial mask layer 162 can then be removed (eg by dry etching) as in 6D is shown for exposing portions of the etching target layer 152 not from the first and / or the second hardmask pattern 160 and or 170 are covered. Exposed portions of the etching target layer 152 can then be removed (eg, by dry etching) using the first and second hardmask patterns 160 and 170 as an etch mask, and the first and second hardmask patterns 160 and 170 can then be removed to remove the structure from the 3A -B provide.

4A Fig. 10 is a plan view of a non-volatile memory device 40 (such as a flash memory device) according to some embodiments of the present invention, and 4B is a cross-sectional view along section line IV-IV 'from 4A , The flash memory device 40 may include a plurality of parallel active regions ACT in a semiconductor substrate SUB separated by device isolation layers. In addition, _{ground select lines} GSL _0-2 , _{row select lines} SSL _0-2, and memory cell word lines WL _1-2n (where n is an integer) may cross the active areas ACT. More specifically, a respective charge storage _gate may be provided between each memory cell word line WL _1-2n and each active area ACT for providing a respective memory cell at each intersection of a memory cell word line WL _1-2n with an active area ACT. The structure of the 4A -B is equal to the one from the 2A -B, with the dummy word lines omitted.

An even number of memory cell word lines WL _1-2n along an active area ACT between a _{ground select} line GSL and a _{row select} line SSL (eg, between GSL ₁ and SSL ₁ ) may define a memory cell array having an even number of memory cells. As further in the 4A - B, adjacent memory cell rows may be separated by two ground select lines GSL (eg GSL ₀ and GSL ₁ ) or by two row select lines SSL (eg SSL ₁ and SSL ₂ ). In particular, 2 ^k (where k is a positive integer) memory cell word lines WL _1-2n define a memory cell row with 2 ^k used for storing data memory cells.

In addition, an array of memory cell word lines WL _1-2n of adjacent memory cell rows may have mirror symmetry. For example, an array of memory cell word lines WL _1-2n between _{ground select line} GSL ₀ and _{row select line} SSL _{0 may have} mirror symmetry relative to an array of memory cell word lines WL _1-2n between _{ground select line} GSL ₁ and _{row select line} SSL ₁ . Similarly, an array of memory cell word lines WL _1-2n between _{ground select line} GSL ₁ and _{row select line} SSL _{1 may have} mirror symmetry relative to an array of memory cell word lines WL _1-2n between _{ground select line} GSL ₂ and _{row select line} SSL ₂ . By providing a sufficient distance / width WL ₄ between a ground select line GSL and a first memory cell word line WL _{1 of} a memory cell row, a ground-induced leakage current and / or an erase fault on the first memory cell word line WL _{1 can be} reduced.

A controller of the non-volatile memory device may be connected to the ground select lines, the row select lines, and the memory cell word lines. During an erase operation, the controller z. B. configured to allow the ground select line GSL ₁ to float to apply an erase voltage vers of about 20 volts to a p-well of the substrate SUB and to _apply 0 volts to the memory cell word lines WL _1-2n , During a write (or program) operation, the controller may be configured to apply the supply voltage Vcc to the ground select line GSL ₁ , to apply 0 volts to a p-well of the substrate SUB, and to have a Passing voltage Vpass applied to the non-selected word lines, and applies a programming voltage Vpgm to the selected word lines.

As in the 4A -B, each of the memory cell word lines WL ₁ to WL _{2n may have} about a same width F ₁ , and a width / a distance W _{5 may be} a gate select line GSL and an adjacent first memory cell word line WL _{1 of} an associated memory cell. Separate row. Approximately the same width / spacing W ₁ can separate adjacent memory cell word lines WL _x and WL _{x + 1} , and approximately the same width / spacing W ₁ can separate a last memory cell word line WL _2n and an adjacent row select line SSL. Moreover, the widths F ₁ and W _{1 may be} approximately equal, and more specifically, each of the widths F ₁ and W _{1 may} each be about one quarter (1/4) of a period P _i that is _even and adjacent to adjacent even memory cell word lines WL WL _{straight + 2} (ie even memory cell word lines, which are separated by only an odd memory cell word line) is defined, or the _odd through adjacent odd memory cell word lines WL and WL _{odd + 2} (ie, odd memory cell word lines by only an even memory cell word line are separated). As further in the 4A - B, adjacent ground select lines GSL ₀ and GSL _{1 may be} separated by approximately one width W ₂ , and adjacent row select lines SSL ₀ and SSL ₁ may be separated by approximately the same width / distance W ₂ . The distance / width W ₂ may be at least about three times greater than the distance / width W ₁ . Moreover, the distance / width W _{5 may be} greater than about three times the distance / width W ₁ (ie, W ₅ > 3 × W ₁ ). For example, the second and / or the fifth distance W ₂ and / or W _{5 may be} between about three and four times greater than the first distance W ₁ , or may be the second and / or the fifth distance W ₂ and / or W ₅ more than three times greater than the first distance W ₁ , and more particularly more than four times greater than the first distance W ₁ be.

Each memory cell word line WL ₁ to WL _2n may thus have a respective non-volatile memory cell (eg, flash memory cell) control gate of a memory cell row on a same active area ACT between a ground select line (eg, GSL ₁ ) and a row select line (eg, SSL ₁ ). Each non-volatile memory cell may further include a charge storage layer between the respective memory cell word line and the active region, a tunnel insulating layer between the active region and the charge storage layer, and a barrier insulating layer between the memory cell word line and the charge storage layer.

The pattern of the ground select lines GSL, the memory cell word lines WL ₁ to WL _2n, and the row select lines SSL may be formed by self-aligned double patterns, as discussed in more detail below. For example, the ground select lines GSL, the row select lines SSL and the odd memory cell word lines (WL ₁ , WL ₃ , WL ₅ , ... WL _2n-1 ) may be formed according to a pattern of a photolithography mask, and may be even memory cell word lines WL ₂ , WL ₄ , WL ₆ , ... WL _2n are formed using self-aligned double patterning.

According to some embodiments of the present invention, which are incorporated in the 4A -B, a first memory cell row on the active area ACT may include a first plurality of memory cell word lines WL ₁ to WL _2n crossing the active area ACT between the first ground select line GSL ₁ and the first row select line SSL ₁ , and approximately a same first distance W ₁ can be provided between adjacent ones of the first plurality of word lines.

In addition, a second memory cell row on the active area ACT may include a second plurality of word lines WL ₁ to WL _2n crossing the active area ACT between a second ground select line GSL ₀ and a second row select line SSL ₀ , and about the same first distance W ₁ may be provided between adjacent ones of the second plurality of word lines. Specifically, the first ground select line GSL _{1 may be} between the second ground select line GSL ₀ and the first plurality of word lines, and may be the second ground select line GSL ₀ between the first ground select line GSL ₁ and the second plurality of word lines. Moreover, portions of the active region ACT between the first and second ground selection lines GSL ₁ and GSL _{0 may be} free of word lines, and the second distance W ₂ between the first and second ground selection lines GSL ₁ and GSL ₀ may be at least about three times larger than that be first distance W ₁ . For example, the second distance W _{2 may be} between about three and four times greater than the first distance W ₁ , and more specifically, the second distance W _{2 may be} more precisely about three times greater than the first distance W ₁ . As further in the 4A -B, the first plurality of word lines WL ₁ to WL _2n may include an even number of memory cell word lines, and a pitch W ₅ greater than three times the first distance W _{1 may be} between the Mass selection line GSL ₁ and the first memory cell word line WL _{1 of} the respective memory cell row. In addition, about the first distance / the first width W ₁ between the last memory cell word line WL _{2n of} the respective Memory cell row and the row selection line SSL _{1 be} provided, and portions of the active area ACT between the ground selection line GSL ₁ and the first memory cell word line WL ₁ may be free of word lines.

The 7A D are cross-sectional views illustrating the operations of forming nonvolatile memory devices from FIGS 4A B using self-aligned double pattern according to some embodiments of the present invention. As in 7A can be a substrate 350 an etching target layer 352 and the etch target layer 352 may include layers of materials for forming memory cell wordlines, select transistors, and select lines 4A -B included.

Specifically, the target layer may be a tunnel insulating layer (such as a layer of silicon oxide), a charge storage gate layer (such as a layer of polysilicon or silicon nitride), a barrier insulating layer (such as a layer of silicon oxide or another of the one of FIG Charge storage gate layer of different dielectric material) as well as a conductive layer (such as a layer of polysilicon and / or metal). The charge storage layer may be between the conductive layer and the substrate, wherein the tunnel insulating layer separates the charge storage layer and the substrate, and wherein the barrier insulating layer separates the charge storage layer and the conductive layer. In addition, a first hard mask layer 355 on the etching target layer 352 are formed, and the first hard mask layer 355 may be a silicon nitride layer 356 on a pad oxide layer 354 contain.

A photoresist layer on the first hardmask layer 355 can using the photomask 300 be patterned such that the photoresist pattern 358 with odd word line photoresist patterns 358w , Earth selection line photoresist patterns 358g and row selection line photoresist patterns 358s provided. In particular, the photomask 300 a photomask pattern 304 on a transparent substrate 302 contain. The photomask pattern 304 can odd wordline photoresist patterns 358b corresponding odd word line photomask patterns 304W , Earth selection line photoresist patterns 358g corresponding ground select line photomask patterns 304g and row select line photoresist patterns 304s corresponding row selection photomask patterns 158s contain.

As in further 7A can show odd wordline photomask patterns 304W may be separated by about one width W ₁₁ , and may have adjacent odd word line photoresist patterns 358w be spaced by about the width / distance W ₁₁ . A first of the odd wordline photomask patterns 304W may be from an adjacent ground select line photomask pattern 304g be separated by about a width W ₅ and a last one of the odd word line photomask patterns 304W may be from an adjacent row select line photomask pattern 304s be spaced by about the width / distance W ₁₁ . Likewise, a first of the odd word line photoresist patterns may be used 358w from an adjacent ground select line photoresist pattern 358g may be spaced by about the width / spacing W ₅ , and may be a last one of the odd wordline photomask patterns 358w from an adjacent row selection photomask pattern 358s be spaced by about the width / distance W ₁₁ .

In addition, each of the odd word line photomask patterns 304W and each of the odd wordline photoresist patterns 358w have a width of about F ₁ , and the width / distance W ₁₁ may be about three times the width F ₁ . In addition, adjacent ones of the odd word line photomask patterns may be used 304W and adjacent the odd word line photoresist patterns 358w define a period P ₁ , and the period P ₁ may be about four times the width F ₁ . The width F ₁ may be a minimum feature size available for the lithography technique used. Neighboring ground selection line photomask patterns 304g adjacent row select line photomask patterns 304s , neighboring ground selection line photoresist patterns 358g , as well as adjacent row select line photoresist patterns 358s may be separated by a width W ₂ , and the width W ₂ may be greater than three times the width F ₁ . For example, the second distance W _{2 may be} between about three and four times greater than the first distance W ₁ , or the second distance W ₂ may be more than three times greater than the first distance W ₁ , and more specifically more than four times greater than the first distance W ₂ Be distance W ₁ .

In addition, a distance W ₅ between a first odd word line photomask pattern 304W and an adjacent ground select line photomask pattern 304g , as well as between a first odd wordline photoresist pattern 358w and an adjacent ground select line photoresist pattern 358g greater than W ₁₁ (eg greater than three times the width F ₁ ). For example, the distance / width W _{5 may be} greater than four times F ₁ .

In particular, a continuous photoresist layer can pass through the photomask 300 selectively exposed to radiation and then developed to provide the photoresist pattern 358 out 7A , Accordingly, an arrangement of the resist pattern becomes 358 by an arrangement of the photomask pattern 304 Are defined. In addition, the photoresist pattern corresponds 358 a pattern of gate select lines, row select lines, and odd word lines described above with respect to FIGS 4A -B were discussed.

Sections of the first hard mask layer 355 (with silicon nitride layer 356 and pad oxide layer 354 ) passing through the photoresist pattern 358 can be selectively removed (eg, by dry etching) to provide a hard mask pattern 360 (with ground selection hardmask patterns 360g , Row selection line hard mask patterns 360s and odd wordline hardmask patterns 360w ), as in 7B is shown. When the first hard mask layer 355 separate layers 354 and 356 can contain any element of the first hardmask pattern 360 also separate layers 354 and 356 contain. Approximately the same distance / width W ₅ (greater than W ₁₁ ) may exist between a ground select line hard mask pattern 360g and a first odd wordline hardmask pattern 360w be provided. Approximately the same distance / width W ₁₁ may exist between adjacent odd wordline hardmask patterns 360w and between a last odd word line hard mask pattern 360w , and a row select line hard mask pattern 360s be provided. Each element of the first hardmask pattern 360 may contain a layer of silicon nitride and / or silicon oxide. After selectively removing portions of the first hardmask layer, the photoresist pattern may 358 be removed.

As in further 7B can show a sacrificial mask layer 362 on the first hardmask pattern 360 and on portions of the etch target layer 352 formed by the first hard mask pattern 360 exposed, and the sacrificial mask layer 362 and the first hard mask pattern 360 can include different materials.

For example, upper layers can 356 of the first hard mask pattern 360 be a layer of silicon nitride, and can the sacrificial mask layers 362 be a layer of polysilicon. In addition, a thickness of the sacrificial mask layer 362 be provided such that: gaps between portions of the sacrificial mask layer 362 on sidewalls of adjacent ones of the odd word line hardmask patterns 360w stay; Gaps between sections of the victim mask layer 362 on sidewalls of adjacent ground select line hard mask patterns 360g stay; Gaps between sections of the victim mask layer 362 on sidewalls of adjacent row select line hardmask patterns 360s stay; Gaps between sections of the victim mask layer 362 on sidewalls of adjacent row-line hardmask patterns 360g and first odd wordline hardmask patterns 360w stay; and gaps between sections of the victim mask layer 362 on sidewalls of adjacent select line hardmask patterns 360s and last odd word line hard mask patterns 360w stay.

A thickness of the sacrificial mask layer 362 on sidewalls of the first hard mask patterns 360w . 360d and 360s can be approximately equal to the width / distance W ₁ between adjacent word lines WL _x and WL _{x + 1} , which in the 4A -B are shown. A width of a gap between sections of the sacrificial mask layer 362 on adjacent odd wordline mask patterns 360w can remain approximately equal to a width F _{1 of} a straight word line WL ₂ , WL ₄ , WL ₆ , ... WL _2n be in the 4A -B are shown.

After forming the sacrificial mask layer 362 may be a second hardmask layer 364 on the sacrificial mask layer 362 be formed, as further in 7B is shown. In addition, the second hard mask layer 364 may be a layer of silicon oxide, and may be the second hardmask layer 364 have a thickness which is at least half of the width F ₁ , thereby leaving gaps in the sacrificial mask layer 362 between odd wordline hardmask patterns 360w to fill. Because wider gaps between adjacent ground select line hard mask patterns 360g , between adjacent row select line hardmask patterns 360s , as well as between ground select line hard mask patterns 360g and adjacent first odd word line hardmask patterns 360w However, there are gaps 368 in the second hardmask layer 364 remain. When a thickness of a second hard mask layer 364 is approximately equal to the width F _{1 of} a wordline, adjacent ground select line patterns 360g , adjacent select line patterns 360s , as well as mass selection hardmask pattern 360g and adjacent first odd wordline hardmask patterns 360w be separated by a distance greater than four times F ₁ .

The second hard mask layer 364 may then be subjected to an etch back process to remove portions of the hardmask layer 364 between adjacent ground select line hard mask patterns 360g , between adjacent row select line hardmask patterns 360s , between mass selection hardmask patterns 360g and adjacent first odd word line hardmask patterns 360w , as well as upper surfaces of the sacrificial mask layer 362 , as in 7C is shown. Sections of the second hard mask layer 364 , which remain after the Rückätzvorgang, thus may have about the thickness F ₁ . More specifically, portions of the second hardmask layer 364 remaining after the etch back process, a second hard mask pattern 370 on the sacrificial mask layer 362 define. The second hard mask pattern 370 can just word line pattern 370w between adjacent odd word line patterns 360w , as well as between the last odd word line patterns 360w and the adjacent row selection line pattern 360s contain.

Exposed sections of the sacrificial mask layer 362 can then be removed (eg by dry etching) as in 7D is shown for exposing portions of the etching target layer 352 not from the first and / or the second hardmask layer 360 and or 370 are covered. Exposed sections of the etching target layer 352 can then be removed (eg, by dry etching) using the first and second hardmask patterns 360 and 370 as an etch mask, and the first and second hardmask patterns 360 and 370 can then be removed to provide the structure from the 4A -B.

According to embodiments of the present invention, non-volatile NAND-type memory devices may be provided with structures having dimensions smaller than dimensions that may be available using a photolithographic exposure followed by etching. Accordingly, NAND type nonvolatile memory devices may be provided with relatively fine line and space patterns (such as patterns of word lines), and increased integration density and / or increased performance may result.

Claims (31)

A non-volatile memory device comprising: a semiconductor substrate (SUB) having an active region (ACT) on a surface thereof; a first ground select line (GSL ₁ ) crossing the active area (ACT); a first row select line (SSL ₁ ) crossing the active area (ACT) and spaced from the first ground select line (GSL ₁ ); a plurality of memory cell word lines crossing the active area (ACT) between the first ground select line (GSL ₁ ) and the first row select line (SSL ₁ ), with about a same first distance (W ₁ ) between adjacent ones of the plurality of memory cell word lines (WL), wherein a second distance (W ₃ ) between a last of the plurality of memory cell word lines (WL _2n ) and the first row selection line (SSL ₁ ) is provided, and wherein the second distance (W ₃ ) is greater than that first distance (W ₁ ) and not greater than twice the first distance (W ₁ ); and a dummy word line (WL _d ) between a first of the plurality of memory cell word lines (WL) and the first ground select line (GSL ₁ ), wherein approximately the first distance (W ₁ ) between the dummy word line (WL _d ) and the first of the plurality of memory cell word lines (WL ₁ ), wherein a third distance (W ₃ ) is provided between the ground select line (GSL ₁ ) and the dummy word line (WL _d ), and wherein the third distance (W ₃ ) greater than the first distance (W ₁ ) and not greater than twice the first distance (W ₁ ). The non-volatile memory device according to claim 1, wherein the third distance (W ₃ ) is in the range of about 1.5 times the first distance (W ₁ ) to about twice the first distance (W ₁ ). The non-volatile memory device of claim 1, wherein the plurality of memory cell word lines (WL) comprises a first plurality of memory cell word lines, the non-volatile memory device further comprising: a second ground select line (GSL ₀ ) representing the active area (ACT ), wherein the first ground select line (GSL ₁ ) is between the second ground select line (GSL ₀ ) and the first plurality of memory cell word lines (WL); a second row select line (SSL ₀ ) crossing the active area (ACT) and spaced from the second ground select line (GSL ₀ ), the second ground select line (GSL ₀ ) between the second row select line (SSL ₀ ) and the first ground select line (GSL ₁ ) is; and a second plurality of memory cell word lines (WL) crossing the active area (ACT) between the second ground select line (GSL ₀ ) and the second row select line (SSL ₀ ); wherein portions of the active region (ACT) between the first and second ground select lines (GSL ₀ , GSL ₁ ) are free of word lines (WL), and wherein a fourth distance (W ₂ ) between the first and second ground select lines (GSL ₀ , GSL ₁ ) is at least about three times larger than the first distance (W ₁ ). A non-volatile memory device according to claim 3, wherein said fourth distance (W ₂ ) is in the range of about 3-4 times larger than said first distance (W ₁ ). A non-volatile memory device according to claim 3, wherein the fourth distance (W ₂ ) is more than three times larger than the first distance (W ₁ ). A non-volatile memory device according to claim 3, wherein the fourth distance (W ₂ ) is at least about four times larger than the first distance (W ₁ ). A non-volatile memory device according to claim 1, further comprising: a plurality of charge storage layers (CSG), wherein respective ones of the charge storage layers (CSG) are between each of the plurality of memory cell word lines (WL) and the active area (ACT); and a plurality of barrier insulating layers (BIL), wherein respective ones of the barrier insulating layers (BIL) are between each of the plurality of memory cell word lines (WL) and the charge storage layers (CSG). A non-volatile memory device according to claim 1, wherein said plurality of memory cell word lines (WL) comprises an even number of memory cell word lines (WL). A non-volatile memory device comprising: a semiconductor substrate (SUB) having an active region (ACT) on a surface thereof; a first ground select line (GSL ₁ ) crossing the active area (ACT); a first row select line (SSL ₁ ) crossing the active area (ACT) and spaced from the first ground select line (GSL ₁ ); a plurality of memory cell word lines (WL) crossing the active area (ACT) between the first ground select line (GSL ₁ ) and the first row select line (SSL ₁ ), with about a same first distance (W ₁ ) between adjacent ones of the plurality of Memory cell word lines (WL) and between a last of the plurality of memory cell word lines (WL _2n ) and the first row selection line (SSL) is provided, wherein a second distance (W ₅ ) between the first ground selection line (GSL ₁ ) and a first of the A plurality of memory cell word lines (WL ₁ ), wherein the second distance (W ₅ ) is at least three times greater than the first distance (W ₁ ), and wherein portions of the active area (ACT) between the first ground select line (GSL ₁ ) and the first of the plurality of memory cell word lines (WL ₁ ) are free of word lines (WL). A non-volatile memory device according to claim 9, wherein the second distance (W ₅ ) is about three times larger than the first distance (W ₁ ). A non-volatile memory device according to claim 9, wherein the second distance (W ₅ ) is not more than four times the first distance (W ₁ ). The non-volatile memory device of claim 9, wherein the plurality of memory cell word lines (WL) comprises a first plurality of memory cell word lines, the non-volatile memory device further comprising: a second ground select line (GSL ₀ ) representing the active area (ACT ), wherein the first ground select line (GSL ₁ ) is between the second ground select line (GSL ₀ ) and the first plurality of memory cell word lines; a second row select line (SSL ₀ ) crossing the active area (ACT) and spaced from the second ground select line (GSL ₀ ), the second ground select line (GSL ₀ ) between the second row select line (SSL ₀ ) and the first ground select line (GSL ₁ ) is; a second plurality of memory cell word lines crossing the active area (ACT) between the second ground select line (GSL ₀ ) and the second row select line (SSL ₀ ); wherein portions of the active region (ACT) between the first and second ground select lines (GSL ₀ , GSL ₁ ) are free of memory cell word lines (WL), and wherein a third distance (W ₂ ) between the first and second ground select lines (GSL ₀ , GSL ₁ ) is at least about three times larger than the first distance (W ₁ ). A non-volatile memory device according to claim 12, wherein said third distance (W ₂ ) is in the range of three to about four times greater than said first distance (W ₁ ). A non-volatile memory device according to claim 12, wherein said third distance (W ₂ ) is about three times larger than said first distance (W ₁ ). A non-volatile memory device according to claim 12, wherein the third distance (W ₂ ) is at least about four times larger than the first distance (W ₁ ). A non-volatile memory device according to claim 9, further comprising: a plurality of charge storage layers (CSG), wherein respective ones of the charge storage layers (CSG) are between each of the plurality of memory cell word lines (WL) and the active area (ACT); and a plurality of barrier insulating layers (BIL), wherein respective ones of the barrier insulating layers (BIL) are between each of the plurality of memory cell word lines (WL) and the charge storage layers (CSG). A non-volatile memory device according to claim 9, wherein said plurality of memory cell word lines (WL) comprises an even number of memory cell word lines (WL ₁ , WL ₂ , ... WL _2n ). A method of forming a nonvolatile semiconductor device, the method comprising: Forming an etching target layer ( 52 ) on a substrate ( 50 ); Forming first hard mask patterns ( 60 ) having a plurality of odd word line patterns ( 60w ) between first and second selection line patterns ( 60g . 60s ), wherein approximately an equal distance (W ₁ ) between the first selection line pattern ( 60g ) and a first odd word line pattern ( 60w ), between adjacent odd wordline patterns ( 60w ) and between a last odd word line pattern ( 60w ) and the second selection line pattern ( 60s ), wherein the first hard mask pattern ( 60 ) comprises a first material; Forming a victim mask layer ( 62 ) on the first hard mask pattern ( 60 ), leaving gaps ( 68 ) between sections of the victim mask layer ( 62 ) on sidewalls of adjacent odd word line patterns ( 60w ), the sacrificial mask layer ( 62 ) comprises a second material, and wherein the first and second materials have different compositions; Forming second hardmask patterns ( 70 ) on the sacrificial mask layer, with the second shark hard mask patterns ( 70 ) a dummy word line pattern ( 70d ) between the first selection line pattern ( 60g ) and the first odd wordline pattern ( 60w ) as well as word line patterns ( 70w ) between adjacent odd wordline patterns ( 60w ) and between the last odd word line pattern ( 60w ) and the second selection line pattern ( 60s ), wherein the second hardmask pattern ( 70 ) comprises a third material, and wherein the second and third materials have different compositions; Removing sections of the victim mask layer ( 62 ) between the first and second hardmask patterns ( 60 . 70 ), so that portions of the etching target layer ( 52 ) between the first and second hardmask patterns ( 60 . 70 ) are exposed; and etching portions of the etching target layer ( 52 ) between the first and second hardmask patterns ( 60 . 70 ) are exposed. The method of claim 18, wherein the distance between the first select line pattern ( 60g ) and the first odd wordline pattern ( 60w ) is provided, approximately 3 times a width (F ₁ ) of the first odd word line pattern ( 60w ). The method of claim 18, wherein the first hardmask patterns ( 60 ) Silicon nitride, wherein the sacrificial mask layer ( 62 ) Comprises polysilicon, and wherein the second hard mask patterns ( 70 ) Comprise silica. The method of claim 18, wherein the odd word line patterns ( 60w ) have approximately the same width (F ₁ ) and wherein the distance between adjacent ones of the plurality of odd word line patterns ( 60w ) greater than the width (F ₁ ) of the odd word line patterns ( 60w ). The method of claim 18, wherein said forming the etch target layer ( 52 ) comprises forming a charge storage layer on the substrate, forming a barrier insulating layer on the charge storage layer, and forming a control gate layer on the barrier insulating layer. A method of forming a nonvolatile memory device, the method comprising: forming an etch target layer ( 152 ) on a substrate ( 150 ); Forming first hard mask patterns ( 160 ) on the substrate ( 150 ), the first hard mask patterns ( 160 ) a plurality of even word line patterns ( 160w ) between first and second selection line patterns ( 160g . 160s ) and a dummy word line pattern ( 160d ) between the first selection line pattern ( 160g ) and a first straight word line pattern ( 160w ), wherein approximately a same first distance (P ₁ ) between the dummy word line pattern ( 160d ) and the first straight word line pattern ( 160w ), as well as between adjacent even word line patterns ( 160w ), and wherein a second distance (W ₃ ) between the first selection line pattern ( 160g ) and the dummy word line pattern ( 160d ) and between a last straight word line pattern ( 160w ) and the second selection line pattern ( 160s ), wherein the second distance (W ₃ ) is less than the first distance (P ₁ ), and wherein the first hard mask patterns ( 160 ) comprise a first material; Forming a victim mask layer ( 162 ) on the first hardmask patterns ( 160 ), leaving gaps ( 168 ) between sections of the victim mask layer ( 162 ) on sidewalls of adjacent ones of the even word line patterns ( 160w ), as well as between the dummy word line pattern ( 160d ) and the first straight word line pattern ( 160w ), the sacrificial mask layer ( 162 ) comprises a second material, and wherein the first and second materials have different compositions; Forming second hardmask patterns ( 170 ) in the gaps on the victim mask layer ( 162 ), the second hard mask patterns ( 170 ) odd word line pattern ( 170w ) between adjacent even word line patterns ( 160w ) and between the dummy word line pattern ( 160d ) and the first straight word line pattern ( 160w ), wherein the second hard mask patterns ( 170 ) comprise a third material, the second and third materials having different compositions; Removing sections of the victim mask layer ( 162 ) between the first and second hardmask patterns ( 160 . 170 ), so that portions of the etching target layer ( 152 ) between the first and second hardmask patterns ( 160 . 170 ), wherein a space between the dummy word line pattern ( 160d ) and the first selection line pattern ( 160g ) free from each of the second hardmask patterns ( 170 ); and etching portions of the etching target layer ( 152 ) between the first and second hardmask patterns ( 160 . 170 ) are exposed. The method of claim 23, wherein the between the dummy word line pattern ( 160d ) and a first straight word line pattern ( 160w ), as well as between adjacent even word line patterns ( 160w ) provided first distance (P ₁ ) about 3 times a width (F ₁ ) of the first straight word line pattern ( 160w ). The method of claim 24, wherein the second distance (W ₃ ) is greater than a width (F ₁ ) of the first straight word line pattern ( 160w ) and not larger than 2 times the width (F ₁ ) of the first straight word line pattern ( 160w ). The method of claim 23, wherein the second distance (W ₃ ) is in the range of about 1.5 times the width (F ₁ ) of the first straight word line pattern ( 160w ) up to about twice the width (F ₁ ) of the first straight word line pattern ( 160w ). The method of claim 23, wherein said even word line patterns ( 160w ) have approximately the same width (F ₁ ), and wherein the distance (P ₁ ) between adjacent ones of the plurality of straight word line patterns ( 160w ) greater than the width (F ₁ ) of the even word line patterns ( 160w ). The method of claim 23, wherein forming the etch target layer (16). 152 ) comprises: forming a charge storage layer on the substrate; Forming a barrier insulating layer on the charge storage layer; and forming a control gate layer on the barrier insulating layer. A method of forming a nonvolatile memory device, the method comprising: forming an etch target layer ( 352 ) on a substrate ( 350 ); Forming first hard mask patterns ( 360 ) on the substrate ( 350 ), the first hard mask patterns ( 360 ) a plurality of odd word line patterns ( 360w ) between the first and second selection line patterns ( 360g . 360s ), wherein approximately a same first distance (P ₁ ) between adjacent odd word line patterns ( 360w ), as well as between a last odd word line pattern ( 360w ) and the second selection line pattern ( 360s ), and wherein a second distance (W ₅ ) between the first selection line pattern ( 360g ) and a first odd word line pattern ( 360w ), wherein the second distance (W ₅ ) is greater than the first distance (P ₁ ), and wherein the first hard mask patterns ( 360 ) comprise a first material; Forming a victim mask layer ( 362 ) on the first hardmask patterns ( 360 ), leaving gaps ( 368 ) between sections of the victim mask layer ( 362 ) on sidewalls of the adjacent first hardmask patterns ( 360 ), the sacrificial mask layer ( 362 ) comprises a second material, and wherein the first and second materials have different compositions; Forming second hardmask patterns ( 370 ) on the victim mask layer ( 362 ), the second hard mask patterns ( 370 ) straight word line pattern ( 370w ) between adjacent odd wordline patterns ( 360w ) and between the last odd word line pattern ( 360w ) and the second selection line pattern ( 360g ), wherein a space between the first selection line pattern ( 360g ) and the first odd wordline pattern ( 360w ) free from each of the second hardmask patterns ( 370 ), the second hard mask patterns ( 370 ) comprise a third material, and wherein the second and third materials have different compositions; Removing sections of the victim mask layer ( 362 ) between the first and second hardmask patterns ( 360 . 370 ), so that portions of the etching target layer ( 352 ) between the first and second hardmask patterns ( 360 . 370 ) are exposed; and etching portions of the etching target layer ( 352 ) between the first and second hardmask patterns ( 360 . 370 ) were uncovered. The method of claim 29, wherein the first distance (P ₁ ) is about 3 times a width (F ₁ ) of the first odd word line pattern ( 360w ). The method of claim 29, wherein forming the etch target layer (16). 352 ) comprises forming a charge storage layer on the substrate, forming a barrier insulating layer on the charge storage layer, and forming a control gate layer on the barrier insulating layer.

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