DE102007026784A1 - Electronic switch unit's capacitance-voltage-characteristic curve determining method, involves determining inter electrode capacitance-current intensity by difference of static inter electrode current intensity and dynamic current intensity - Google Patents

Abstract

The method involves determining an output capacitance-current intensity by the use of the difference of a static output current intensity and a dynamic measured current intensity during a controlled state of an electronic switch unit, where the static output current intensity is determinable from an output characteristic curve of the electronic switch unit. An inter electrode capacitance-current intensity is determined by the use of the difference of a static inter electrode current intensity and a dynamic measured current intensity during a passive state of the electronic switch unit.

Description

Method for determining capacitance-voltage characteristics of electronic switching elements, characterized in that in controlled electronic switching elements (three contacts) the dependence of the input, feedback and output capacitance of the associated residual stresses or in passive electronic switching elements (two contacts) the dependence the interelectrode capacitance of interelectrode voltage is determined as a differential or large signal capacitance from application-typical commutation by the discrete-time measurement data input, Rückwirkungs- and output voltage and the input and output current and in passive electronic switching elements, the time-discrete measurement data of the interelectrode voltage and the Interelektrodenstromstärke application-typical Kommutierungsvorgängen be included; that the measured time-dependent voltages at controlled electronic switching elements by the input and output current strength or passive electronic switching elements by the voltage caused by the interelectrode current drops across the acting resistors between the measuring points and the chip as well as controlled electronic switching elements by the input and output current increase or in the case of passive electronic switching elements Interelektrodenstromanstieg caused voltage drops over the acting inductance between the measuring points and the chip can be corrected according to the second Kirchhoff's theorem to chip voltages; wherein in controlled electronic switching elements, the output capacitance current strength by difference of the static output current intensity and the dynamically measured current from the output characteristic field of the electronic switching element for each measurement time or in passive electronic switching elements, the Interelektrodenkapazitätsstromstärke by difference of the Interelektrodenkennlinie of the electronic switching element for each measurement time detectable static Interelektrodenstromstärke and the dynamically measured interelectrode current intensity is determined; This results in controlled electronic switching elements by numerical integration of the input current intensity and the output capacitance current or passive switching elements by integration of Interelektrodenstromstärke after offset corrections, which satisfy the condition that the charge of the capacitances at the time zero Coulomb, to which the residual stress of the capacitance is zero, the time-dependent input, feedback and output or Interelektrodenladungsverläufe from which the differential capacitances (C _diff = dQ (t) / dV (t)) and the large signal capacitances (C _LS = Q (t) / V (t)) of the electronic switching elements can be determined.

It follows a detailed discussion on the embodiment: MOSFET

2. Switching behavior

2.1. Trench gate MOSFETs

Trench gate MOSFETs differ from planar MOSFETs in that they have a new gate structure that allows the channel in the p-well to travel vertically. From the Spatial Structure of the MOSFET Cell with Trench Gate ( 1 ) result in accordance with the planar MOSFETs in the 2 represented, parasitic elements without consideration of parasitic connection inductances.

By enlarging the active silicon area, in the trench structure, an improved control of the channel cross-section is made possible and a smaller channel resistance is effected. Further advantages are that higher current densities, lower forward and switching losses, higher breakdown voltages and a higher latch-up-strength can be achieved or the cell area can be reduced compared to corresponding planar MOSFETs. The disadvantages are a poorer short circuit resistance, a higher gate capacitance C _GS and a more complex production process compared to [1].

in the All work on a half bridge is part of this work performed with trench gate MOSFETs in insulated package [2].

2.2. Switching behavior of MOSFETs during hard switching

2.2.1. Influence of the freewheeling diode

Many switching tasks for MOSFETs are characterized by "hard" switching on and off of ohmic-inductive loads in which the load current I _L never drops to zero (non-kicking operation) The load time constant L _L / R _L is much greater than the period T _s = 1 / f _{S of} the switching frequency, which requires one Free-wheeling diode, which prevents tearing off the load current I _L by the load inductance L _L when turning off the MOSFET. The switching behavior of MOSFETs will be clarified below using a buck converter circuit ( 3 ).

The way in which the two semiconductors separate in the current and voltage direction is significantly influenced by the diode and its characteristic ( 4 ).

Thus, when the transistor is turned on, the diode can only switch off or take over blocking voltage if the current is completely commutated by the freewheeling diode onto the transistor, ie the drain current I _D must reach the level of the load current before the drain-source voltage V _DS can sink to their pass value. The current commutation takes place before the voltage commutation.

Accordingly, when the transistor is turned off, the diode can not turn on until the voltage is fully commutated by the MOSFET to the diode, ie, the drain-source voltage V _DS must have increased at least to the level of the intermediate _{circuit voltage} V _DClink the drain current I _D can drop to the value of the residual current. The current commutation takes place after the voltage commutation.

In addition to the effects described, the reverse recovery behavior of the freewheeling diode directly affects the drain current. During the transition from the conducting to the blocking state, the charge stored in the diode is dissipated by a current flow in the reverse direction of the diode. Since the load current I _{L of} the node equation I D = I L - I diode (2.1) Due to the ratio of the load time constant and the period of the switching frequency is almost constant, the drain current must increase by the reverse current peak beyond the load current during the reverse current peak of the diode.

2.2.2 Influence of commutation inductance and capacity

The 5 shows the commutation circuit with structure-related internal capacitances, internal resistances and connection resistances, as well as internal and parasitic connection inductances. They influence the switching behavior, in particular the switching speed and the switching losses.

The commutation _inductance L _K results from the sum of L _DClink , L _{K_CP} , L _{A_CP} , L _{D_CP} and L _{S_CP} . As soon as an alternating current flows through an inductance, a voltage V _{L is} induced in it, the direction of which depends on the current increase:

When the consumer _{counting system is used} , the current rise through the MOSFET and the inductances L _DClink , L _{D_PC} and L _{S_PC is} positively defined during active activation of the MOSFET and negatively defined by the diode and the inductances L _{K_P} C and L _{A_PC} . The positively defined drain and diode current and thus the corresponding current increases are, however, directed opposite. Due to the load current injection, although different currents flow through the diode and the transistor during the commutation, the current increases are the same. Thus, the voltage drop across the inductors from the beginning of Stromkommutierung to the beginning of the Rückstromabrisses reduces the voltage V _DS and so the turn-on of the transistor.

consequently it comes with the reverse current break and active switching off the MOSFETs due to high current change rates through the commutation inductance to overvoltages to transistor and diode. Therefore, the turn-off losses increase and the voltage stress of the power semiconductors.

The minimum value of the commutation capacitance C _K is composed of C _GS , C _GD and C _DS . If the voltage changes over a capacitance, a current flow occurs, the direction of which depends on the voltage increase:

Accordingly, C _{K in} principle acts ausschaltentlastend, since a part of the current through the power semiconductor commutated to the parallel capacitances. However, additional losses occur during active switching on due to the transfer of the commutation capacities. Contrary to the ideal conception of powerless voltage control via the MOSFET gate, the reloading currents of the internal capacitances required during switching are the cause of a switching frequency-dependent demand for drive power. In addition, the circuit and transistor-internal capacities can stimulate unwanted vibrations together with the parasitic inductances.

2.3. dI _D / dt and dV _DS / dt - feedback

2.3.1. dI _D / dt - feedback of the source inductance

Out 5 It will be seen that the portion L _{S_PC1 of} the source inductance lies in both the power and drive circuits. When changing the drain current, a voltage is induced via it, which acts as a negative feedback in the control circuit. For example, when the MOSFET is turned on, it slows down charging and, when turned off, discharges the gate-source capacitance. This increases the switching times and the switching losses.

2.3.2. dV _DS / dt - feedback of the drain-gate capacitance

The influence of the parasitic drain-gate capacitance C _DG is called the Miller effect. C _DG , also called Miller Capacity, causes a dV _DS / dt negative feedback on the gate. To clarify this effect, the operations on the transistor during switching on and off are considered in more detail below. 6 schematically illustrates passing through the output characteristic field of a MOSFET (n-channel enhancement type) during switching.

Turn on the MOSFET

zu fließen, der zunächst hauptsächlich die Gatekapazität C_GS auflädt. V_GS steigt an. Bis die Schwellenspannung V_GS(th) erreicht wird, bleiben die Drain-Source-Spannung und der Drainstrom unbeeinflusst, d. h. V_DS ≈ V_DClink und I_D entspricht weiterhin dem Reststrom (vgl. Übertragungskennlinie in 7). Erst mit dem Erreichen der Schwellenspannung ^VGS(th) schaltet sich der Transistor ein und I_D beginnt zu fließen. Während der Drainstrom kommutiert, durchläuft der Transistor den Aktiven Kennlinienbereich bei annähernd konstanter Drain-Source-Spannung. V_GS steigt dabei an und ist über die Steilheit g_fs mit dem Drainstrom gekoppelt: dID = gfs·dVGS. (2.5) With the switching on of the control voltage V _Dr starts a positive gate current

initially mainly charging the gate capacitance C _GS . V _GS increases. Until the threshold voltage V _{GS (th) is} reached, the drain-source voltage and the drain current remain uninfluenced, ie V _{DS ≈V DClink} and I _D continue to correspond to the residual current (see transfer characteristic in _FIG 7 ). Only when the threshold voltage ^V GS (th) is reached, the transistor turns on and I _D starts to flow. While the drain current is commutating, the transistor passes through the active characteristic region at approximately constant drain-source voltage. V _GS increases and is coupled to the drain current via the transconductance g _fs : dI D = g fs * dV GS , (2.5)

und verursacht so den negativen Drain-Source-Spannungsanstieg [3]

After current commutation, the drain-source voltage may drop to V _{DS (on)} . I _D and V _GS are still coupled via g _fs , so V _GS remains constant at the value necessary according to the transfer characteristic to maintain I _D = I _L. The result is the Miller Plateau. As V _DS decreases, the entire gate current overcharges the highly voltage-dependent drain-gate capacitance:

causing the negative drain-source voltage rise [3]

Since the Miller capacitance is strongly voltage-dependent and rises sharply at low and negative drain-gate voltages, the entire gate current is also converted to - even if dV _DS / dt decreases in magnitude load from C _DG consumed. Only when the drain-source voltage has dropped so far that the required Umladestrom the Miller capacitance is smaller than the gate current provided, the gate-source voltage continues to increase. The transistor is then already in the ohmic region of the output characteristic field, ie V _GS is no longer coupled to I _D via g _fs . The gate-source voltage rises to the control voltage. The final value of V _GS affects the R _{DS (on)} and thus the drain-source voltage V DS (on) = I D · R DS (on) , (2.0)

The total amount of charge required Q _Gtot is greater and the charging time is longer, the larger V _DS , because it applies:

Taking into account the reverse-recovery behavior of the diode, the drain current increases over I _L to I _D = I _L + I _rr , whereby V _{GS increases} beyond the Miller voltage (cf. 6 ). During the reverse current cut, V _GS drops very fast to the Miller voltage, causing a current from C _GS through C _DG and the current channel that is additional to the gate current. This additional current causes a comparatively steep drop in voltage of V _DG and V _DS during the reverse current cutoff.

Turn off the MOSFET

When switching off, the processes described proceed in the reverse order. A negative gate current leads to the charge quantity Q _Gtot from the gate. So first the gate-source voltage decreases exponentially. While I _D still remains unchanged, V _{DS (on)} = I _D * R _{DS (on)} starts to increase slightly. From leaving the Ohm and the subsequent passage through the active characteristic range until reaching VDS (off) ≈ V _DClink , the Miller _plateau is formed again. After that, the current commutation can take place and the gate-source voltage continues to decrease exponentially. When V _{GS (th)} is reached, the transistor is turned off.

Reloading the Miller Capacity on and off slows down the charging and discharging of the gate-source capacitance. By a larger gate resistance R _G , the switching is slowed down.

2.3.3. Feedback in the MOSFET bridge branch with inverse diode

The described feedback effects can cause a further effect under certain conditions by the Miller capacitance and the source inductance, if the buck converter circuit is realized by a bridge circuit of MOSFETs with integrated inverse diodes ( 8th ).

At the beginning of the viewing, the top switch T1 and the bottom switch T2 are turned off and the load current flows through the diode D2. Now, if transistor T1 is actively turned on, the steep positive increase of the drain-source voltage dV _DS2 / dt at the time of the reverse current break of its parallel inverse diode D2 causes a shift current i _v through the Miller capacitance. The displacement current causes a negative voltage drop V _RG across the resistor R _G. At the same time, due to the negative current increase during the reverse current _breakdown, a voltage V _{LS_PC1 arises} across the source inductance L _{S_PC1} . Both feedbacks may control the MOSFET T2 during the reverse current cut-off to the active region if the sum of the voltages V _RG and V _{LS_PC1 becomes} greater than the threshold voltage V _{th of} the MOSFET. This leads to a cross current in the bridge and additional losses in the transistors T1 and T2 [1].

Despite these negative consequences, the application of a negative gate-drain voltage in the off state is not recommended for the control of power MOSFETs, since MOSFETs have only a limited dV / dt or the internal inverse diodes only a limited dI / dt strength. In addition to the explained switching on of the MOSFET due to the voltage drop across the gate resistance caused by the displacement current, the voltage increase can also cause the switching on of the parasitic bipolar transistor [4]. However, it is essential to prevent parasitic turn-on of the bipolar transistor by keeping the potential of the parasitic base as close as possible to the source potential. Therefore, the body lead (p-type substrate) is connected to the n-type region (source). As a result, the base-emitter path of the parasitic npn bipolar transistor is short-circuited. The base-collector diode corresponds to the inverse diode ( 2 ). The body-source short circuit is very effective to prevent a static turn on the bipolar transistor. However, especially in MOSFET bridge legs with integrated inverse diodes, in rapid turn-off operations, the bipolar type can be turned on ransistors come. The equivalent circuit diagram of the power MOSFET ( 2 ) illustrates that the increase of the drain-source voltage causes a shift current through the drain-source capacitance CD and the base-emitter resistor R _{W of} the parasitic NPN bipolar transistor. If the resulting voltage drop across the lateral p-well resistor R _{W reaches} the level of the threshold voltage, the bipolar transistor is triggered. It creates a very high power loss and the transistor can not be turned off via the base, as this is not accessible. This can lead to loss-performance-related destruction of the MOSFET. The parasitic control of the MOSFET channel, however, the current and voltage increase is limited and weakens the dangerous effect of the bipolar Aufsteuerns. [1]

2.4. Current and voltage curves when switching on and off

The effects described are for the buck converter - without the consideration of possible vibrations - in 9 turning it on and on 10 switching off qualitatively and summarized.

3. Determination of capacities using transient analysis

3.1. analysis types

The intention of this work is to determine the voltage-dependent switch capacities during switching operations. The switch capacities can be examined by means of various types of analysis. In order to decide which analysis is suitable for determining the capacities, the basic types of analysis are briefly explained and compared in the following table. of analysis purpose stimuli Results system of equations DC analysis (DC) working point calculation DC voltages / currents U ₀ , I ₀ - algebraic - nonlinear - real valued AC analysis Small signal analysis Sinusoidal alternating voltages / currents U (ω), I (ω) - algebraic - linear - complex valued Transient analysis Investigation of transient behavior (large signal) any time-varying voltages / currents u (t), i (t) - Differential equation system - nonlinear

The DC analysis is used to determine a DC working point. The circuit will work with all nonlinearities, but considered without time dependencies. For example Inductors due to a short circuit and capacitances through an infinite resistance (interruption) modeled. This type of analysis can therefore not be used to identify the switch capacities are used.

The AC analysis is used to calculate the small-signal behavior the circuit. The behavior is examined with small deflections from a DC operating point with sinusoidal alternating quantities as Stimuli. All nonlinearities are characterized by linear functions shown in the working point. This type of analysis is suitable for determination the switch capacities, if one for a Determined variety of working points, which then during to undergo the commutation. It is an algebraic, linear, solve complex system of equations.

The Transient analysis is the most general case. As stimuli can be any time-dependent quantities occur. All nonlinearities are preserved. The transient analysis forms the temporal course of the variable present circuit after. Thus, the large signal analysis proves as particularly practicable for determining the capacities during the commutation. It has to be a non-linear, real-valued one Algebro differential equation system can be solved. In these are ordinary differential equations and algebraic ones Coupled with ancillary conditions.

3.2. Nonlinear capacity - large signal and small signal capacity

ausgedrückt werden. Der Strom durch die Kapazität ergibt sich aus

die spannungsabhängige differentielle Kapazität ist. Gleichung (3.2) ist allgemein gültig, wenn die Abhängigkeit der differentiellen Kapazität von der angelegten Spannung berücksichtigt wird [5]. Die differentielle Kapazität C_diff(v) ist keine Kleinsignalkapazität. Kleinsignalkapazitäten beziehen sich immer auf einen Arbeitspunkt. Eine nichtlineare differentielle Kapazität bei der Spannung v₀ kann durch eine Tangente im Punkt P(v₀; q(v₀)) dargestellt werden (11).The electrical capacity represents the ability of a body to store electrical charges. The stored charge q (t) is a function of the instantaneous voltage across the capacitance. The charge-voltage characteristic can therefore be determined by the equation

be expressed. The current through the capacity results

is the voltage-dependent differential capacitance. Equation (3.2) is generally valid if the dependence of the differential capacitance on the applied voltage is considered [5]. The differential capacitance C _diff (v) is not a small signal capacitance. Small signal capacitances always refer to one operating point. A nonlinear differential capacitance at the voltage v ₀ can be represented by a tangent at point P (v ₀ ; q (v ₀ )) ( 11 ).

bzw. die Veränderung der Ladung gegenüber der Ladung bei v₀ in die Taylorreihe

umgeformt werden. Die Ableitungen der Ladung nach der Spannung an der Stelle v₀ sind zeitlich unabhängig. Damit ergibt sich für Strom mit v(t) – v₀ = Δv

Taylor series are used in analysis to represent functions in the vicinity of certain points by power series. Thus, complicated analytic expressions can be approximated well by a Taylor series broken off after a few terms. The Taylor series of a function in a point (development point) is the power series evolution of the function at that point [6]. So also the equation (3.1) with the evolution point v ₀ into the Taylor series

or the change of charge compared to the charge at v ₀ in the Taylor series

be transformed. The derivatives of the charge after the voltage at the point v ₀ are independent in time. This results in current with v (t) - v ₀ = Δv

die Kleinsignalkapazität im Spannungsarbeitspunkt v₀ ist. Offensichtlich ist C₁(v₀) eine Linearisierung im Arbeitspunkt und lediglich eine Funktion der Spannung, bei der die Kapazität betrieben wird. Eine Gegenüberstellung der Gleichungen (3.3) und (3.8) zeigt, dass die Kleinsignalkapazität gleich der differentiellen Kapazität im Spannungsarbeitspunkt ist. Dieser Umstand könnte bei der Ermittlung von Parameter für die Simulation genutzt werden, da eine Kleinsignalkapazität relativ einfach messbar ist (vgl. Abschnitt 3.3. – Datenblattangaben zu Schalterkapazitäten).For small deflections from v ₀ or small Δv, the Taylor series (3.6) can be reduced to the first term with good nutrition. One speaks of a linearization in the current working point with a _DC component I _DC = 0 A. It follows

the small signal capacitance at the voltage operating point is v ₀ . Obviously, C ₁ (v ₀ ) is a linearization at the operating point and only a function of the voltage at which the capacitance is operated. A comparison of equations (3.3) and (3.8) shows that the small signal capacitance is equal to the differential capacitance at the voltage operating point. This circumstance could be used in the determination of parameters for the simulation, since a small-signal capacity can be measured relatively easily (see Section 3.3 - Datasheet details on switch capacities).

A large signal capacity can be defined as

The current through this large signal capacity is calculated by applying the product rule by

ergibt.The equations (3.10) and (3.2) are different at first glance. However, they are both based on the fact that the current is characterized by the capacity

results.

und damit aus Gleichung (3.10), (3.11) und (3.9)

By substituting Equation (3.9) into Equation (3.10), it is once again made clear that Equations (3.10) and (3.2) produce the same result. This could be interesting for the simulation of the capacitance current. It turns out. from equation (3.9) using the quotient rule

and thus from equations (3.10), (3.11), and (3.9)

Which equation is used to determine the capacitance current is thus a question of the capacity definition [5]. The metrological determination of the differential capacitance C (v (t)) or the large signal capacitance C ₂ (v (t)) could provide the user and developer of transistors important information about how the switch capacitances change during switching, and so Influence on the switching behavior by means of calculation of the displacement currents through the capacitors better. show.

3.3. Datasheet information on switch capacities

In data sheets, the small-signal capacitance characteristics of the input capacitance C _iss , the output capacitance C _oss and the feedback _capacitance C _{rss are} usually dependent on the drain-source voltage V _DS at a frequency f = 1 MHz and a gate-source voltage V _GS = 0V shown. The capacitances C _iss , C _oss and C _rss are _dependent both on the drain-source voltage V _DS and on the gate-source voltage V _GS . They can be mapped as surfaces in a Cartesian coordinate system with the dimensions V _DS , V _GS and C _xss (V _GS ; V _DS ). However, because a gate-to-source voltage of V _GS = 0 V is specified for the data sheet information, the charts in the datasheet are only a section through these areas that may not even include the maximum and minimum values of the voltage-dependent switch capacitances. Thus, the information in the data sheets is not meaningful for how the capacitances change during switching or how the areas C _iss (V _GS , V _DS ), Coss (V _GS , V _DS ) and C _rss (V _GS , V _DS ). However, since the small-signal capacitances correspond to the differential capacitances at the operating point, they are then briefly defined and a possible measuring circuit for each of them is shown in order to explain the connection to the interelectrode capacitances. To what extent these relationships can then be transferred to the differential capacities still needs to be investigated.

The input capacitance C _iss is defined as the capacitance between the gate and source terminals in the event of an ac short between the drain-source path. The capacitance between the drain and the source terminal is accordingly understood to mean the capacitance between the output capacitance C _oss and the gate-source terminals short-circuited for alternating voltage. The _effective capacitance C _rss is the capacitance measured between the drain and the gate when the drain-source path is short-circuited for alternating current. The measuring scarf specified by the German Institute for Standardization with the appropriate requirements, precautionary measures and instructions for performing the measurement are in the withdrawn standard DIN IEC 747 Part 8 and will not be further explained in this work. Instead, the shows 13 other measuring circuits for determining C _iss , C _oss and C _rss and the associated equivalent circuit diagrams for determining the interelectrode capacitances C _GS , C _DS , C _DG ( 11 ) satisfying the above-mentioned small-signal capacitance definitions [7].

The input capacitance C _iss will be in accordance with the circuit structure 13a ) is calculated using equation (3.13):

The capacitor connected in parallel with the output short-circuits the capacitance across the output terminals for the alternating current. Accordingly, the two capacitors C _DG and C _{GS are} parallel. The following applies:

From the measured variables in circuit b), the output capacitance determined

From the equivalent circuit diagram results: C oss = C DG + C DS , (3.16)

From the measuring circuits c) and the associated equivalent circuit diagram results

In this case, the measuring circuits b) and c) match. In the circuit c), however, the current i ₁ is measured by the input and not the current i ₂ through the output terminals. For positive drain-source voltages, however, only a portion of the reaction capacitance or the drain-gate capacitance can be determined. Although the determinable values would correspond to the previously explained definition, negative drain gate voltages occur during the switching, for which the reaction capacitance can not be determined with this method.

If you wanted now with the help of the measuring circuit after 13 determine the small signal capacitances during switching, so you would first for an operating condition (characterized by _{DC link voltage} V _DClink , load current I _L , gate resistance R _G and temperature T _J ) record the switching characteristics for switching on and off of the transistors. It would then be necessary to determine characteristic voltage points (V _DS , V _GS ) from the switching characteristics and to set them in the measuring circuit in order finally to determine the small-signal capacities from the measured data. This complex process would have to be _repeated for different intermediate _{circuit voltages} V _DClink , load currents I _L , gate resistors R _G and temperatures T _{J in} order to be able to make statements about possible dependencies. Therefore, in the context of this thesis, the switch capacities according to the definition equations (3.3) and (3.9) - the large signal capacitance and the differential capacitance - are determined directly from the on and off measurement data for different operating points. It should be noted, however, that the differential capacitance thus determined does not correspond to the small-signal short-circuit capacities. The measurement data is used to evaluate data generated in a buck converter, so that the equations (3.14), (3.16) and (3.18) are of limited use.

The principal measuring circuit is in 14 shown. The drain-source voltage was measured between P2 and P4 or P3 and P4, the gate-source voltage between P5 and P4 and P1 and P2 and the gate current between the drivers and P1 and P5. Due to the existing measurement setup, the drain current could only be determined by the lower switch with a coaxial shunt integrated in the measuring board. Therefore, almost all data has been generated at the bottom switch. For the diode measurement, the load was clamped to -V _DClink and for the MOSFET measurement to + V _DClink .

For the measurements are the working points set by a double pulse Service. About the duration of the first pulse and through the Choice of the load inductance, the load current was set and its falling edge, or the rising edge of the second Pulses were used to measure the switch-off and switch-on characteristics. The Data was not recorded in continuous operation. Such Procedure has the advantage that when pulsed occurring power loss the thermal impedance of the DUT (Device Under Test) prevents the set junction temperature from changing.

3.4. Data smoothing

The processing of the measurement data for the evaluation of the CV characteristics is of particular importance, since the determination of the characteristic curves takes place numerically. Especially in numerical differentiation, the noisy measurement data are problematic, which is why the measurement data are smoothed several times with a numerical PT1 element. A PT1 element is a low-pass filter, ie a filter that lets signal components with frequencies below the cut-off frequency pass through almost unattenuated and attenuates signal components of higher frequencies. In the time domain, the proportional element with first order lag can be defined with the proportional coefficient K _P = 1 by the following differential equation [8].

These can be discretized approximately as follows become

In order to surrendered

By the filter creates a phase shift. However, as for all related voltage and current measurement series are the same Sampling time and time constant are used, this is for all measurement series identical and thus owns the evaluation no further relevance. In addition, the flanks lose in steepness and amplitude. When setting the time constant T had therefore an optimum between the elimination of noise and conservation the characteristic switching curves are found.

Legend

• x (t)

  continuous time controlled variable

  y (t)

  continuous time manipulated variable

  T

  Time constant of the Proportional element with delay

  T ₀

  sampling

  x _k

  discrete-time controlled variable

  y _k

  discrete-time manipulated variable

3.5. Feedback capacitance crss

3.5.1. Determination of the reaction capacity

Both the differential feedback capacitance and the large-signal feedback capacitance are first determined for the turn-off _profiles at a load current of I _L = 150 A, an intermediate _{circuit voltage} of V _DClink = 30 V, a gate resistor R _G = 10 Ω and a junction temperature of T _J = 25 ° C. , In the driven state, the drive voltage V _Dr = 12 V.

The determination of the large-signal reaction capacity takes place according to equation (3.9)

bestimmt werden. Dabei sollte i unter Beachtung der Messpunktdichte möglichst klein gewählt werden, um die Genauigkeit der numerischen Differentiation zu erhöhen. Aufgrund des Messrauschens ist es jedoch mitunter notwendig, i > 1 zu wählen, um numerische Probleme (beispielsweise die Division durch Null) zu verringern.The differential feedback capacity can be approximated on the basis of equations (3.3)

be determined. In this case, i should be chosen as small as possible, taking into account the measuring point density, in order to increase the accuracy of the numerical differentiation. However, due to the measurement noise, it is sometimes necessary to choose i> 1 to reduce numerical problems (for example, division by zero).

The equations show that, for the sake of simplification, it is assumed that the Miller capacitance depends only on the drain-gate voltage. Between the drain and gate, equations (3.22) and (3.23) can then be used to determine the capacitive effect of the entire measurement circuit between the two switch electrodes during switching. The drain-gate voltage is determined according to the mesh rule for each measurement point: V DGmess (t n ) = V DSmess (t n ) - V GSmess (t n ) (3.24)

To estimate the charge Q _r (t) in the reaction capacity, the charge change between two measurement points was first estimated. It was important to note that capacities are passive devices and therefore the consumer arrow system should be used. However, since V _DG and i _G are oppositely defined, the negated gate current is used. The charge increments are thus calculated as follows:

The total charge Q _{G which has} flowed into the gate up to the time t _n is then obtained by numerical integration from the summation function

Under the condition that at time t _v applies V DG (t V ) = 0 V ↔ Q r (t v ) = 0 C, (3.27) are determined, the charge Q _r in the feedback capacitance at the time t _n with Q r (t n ) = Q gtot (t n ) - Q gtot (t v ). (3.28)

In the 15 . 16 . 17 and 18 the first results of the evaluation from the measured switch-off characteristics (R _G = 10 Ω, I _L = 150 A, V _DClink = 30 V and T _J = 25 ° C) are shown and summarized.

• 1. Betrachtet man die 15 und 16, so stellt sich die Frage nach der Ursache für die Zunahme der Kapazität nach einer Änderung der Treiberspannung.
• 2. Bei der Ermittlung der Großsignalkapazität entstehen durch Anwendung der Gleichung (3.22) im Spannungsnulldurchgang numerische Probleme, die mitunter durch eine höhere Datenpunktdichte verringert, aber nicht vollständig beseitigt werden können.
• 3. Die spannungsabhängigen Schalterkapazitäten scheinen nicht nur von der Spannung über der Kapazität abhängig zu sein, sondern auch davon, wie das Ausgangskennlinienfeld während der Kommutierung durchlaufen wird. Damit sind die Schalterkapazitäten abhängig von: • dem Gatewiderstand R_G, der die Schaltgeschwindigkeit beeinflusst, • dem Drainstrom I_D, • der Drain-Source-Spannung V_DS bzw. der Zwischenkreisspannung V_DClink und • der Gate-Source-Spannung V_GS bzw. der Treiberspannung V_Dr. Diese Feststellung muss bei den weiteren Untersuchungen beachtet werden, da je nach dem, wie stark diese Abhängigkeit ausgeprägt ist, bei der Anwendung der Gleichungen (3.3) und (3.9) ein mehr oder weniger großer Fehler gemacht wird. Diese gehen im übertragenden Sinne davon aus, dass die nichtlineare Rückwirkungskapazität ausschließlich von der Drain-Gate-Spannung abhängig ist. Deshalb muss bei der weiteren Auswertung abgeschätzt werden, ob diese Modellvorstellung (Eine Schalterkapazität wird ausschließlich der Spannung über ihren Anschlüssen beeinflusst.) für den vorliegenden Trench Gate MOSFET ausreichend genau ist.

Although the measurement data, as in section 3.4. - Data smoothing - have been described, smoothed, the remaining noise affects so much on the quality of the differential capacitance curve that must be estimated in the further evaluation, whether the direct determination of this characteristic from the measured data with reasonable effort is possible. It becomes clear that the determination, processing and smoothing of the measured data should be given great importance if numerical differentiation is required. In the different representations of the capacity characteristics ( 15 . 16 . 17 . 18 ) reveal further problems:

• 1. Looking at the 15 and 16 , the question arises as to the cause of the increase in capacity after a change in the drive voltage.
• 2. In the determination of the large signal capacitance, the application of Equation (3.22) at zero voltage causes numerical problems, which can sometimes be reduced by a higher data point density, but can not be completely eliminated.
• 3. The voltage-dependent switch capacitances appear not only to depend on the voltage across the capacitance, but also on how the output characteristic field is traversed during commutation. Thus, the switch capacitances are dependent on: • the gate resistance R _G , which influences the switching speed, • the drain current I _D , • the drain-source voltage V _DS or the intermediate _circuit voltage V _DClink and • the gate-source voltage V _GS or the driver voltage V _Dr. This finding must be taken into account in the further investigations, since, depending on how strongly this dependence is pronounced, a more or less large error is made in applying equations (3.3) and (3.9). In the transferring sense, these assume that the nonlinear reaction capacitance depends exclusively on the drain-gate voltage. For this reason, it must be estimated in the further evaluation whether this model concept (a switch capacitance is influenced exclusively by the voltage across its terminals) is sufficiently accurate for the present trench gate MOSFET.

in the following section will be the large signal capacity analyzed separately from the differential capacity, To make the representations as clear as possible to be able to.

3.5.2. Dependence of the reaction capacity from the switching speed

3.5.2.1. Large signal reaction capacity Crss _LS (R _G )

The 19 shows the determined large signal reaction capacity Crss _LS from Ausschaltverläufen (I _L = 150 A, T _j = 25 ° C and V _{DC link} = 30 V) at different gate resistors R _G. It is noticeable that while the curves for R _G = 180 Ω and R _G = 330 Ω are almost identical, the CV curve with R _G = 10 Ω deviates relatively strongly from the other curves. To analyze the causes of these deviations show 20 and 21 the time courses of the two reaction capacities with R _G = 180 Ω and R _G = 330 Ω. The comparison of these figures with the 15 suggests that the direct evaluation of the measured variables can not lead to a match, since the voltages across the internal switch inductances and resistances as well as the connection inductances and resistances are contained in the measured voltages V _DS and V _GS . In order to determine the voltage applied to the chip and thus also to the reaction capacitance, the voltages across the parasitic elements must be calculated accordingly. How the voltages across the resistors and inductors are defined, shows 22 , Taking equation (3.24) into account, the result for the chip voltage U _DGchip , according to the set of sets, is as _follows : U DGchip = V DGmess + V RGint + V LG - V RD - V LD , (3.29)

Thus, the voltage drops across the parasitic elements, depending on the current direction and sign of the current increase relative to the measuring voltage, lead to a greater or lesser voltage on the chip. A sense of the magnitude of the voltages V _{R - G} , V _{L - G} , V _{R - D} and V _{L - D} and the influence of the capacitance and charge _curves by these voltages 23 (Influence of R _Gint ), 24 and 25 (Influence of L _G ), 26 (Influence of R _D ) as well 27 and 28 (Influence of L _D ). They represent the influence of the individual parasitic elements on the originally determined characteristic curves for a turn-off characteristic (R _G = 10 Ω, I _L = 150 A, V _{DC link} = 30 V and T _J = 25 ° C) as a function of the drain gate Tension.

Thus, for the curves Crss _{LS_RG} and Qr _RG in 23 an internal gate resistance R _Gint = 1.4 Ω is set. The data sheets usually do not provide information about the internal gate resistance. The comparison of the time course of the capacity and gate current in 15 . 20 and 21 However, it can be assumed that the increase in capacitance when the drive voltage is reset to V _Dr = 0 V due to the current through the internal gate resistance and the resulting voltage V _RGint and thus has an influence on the entire C-characteristic. On the basis of this assumption, R _{Gint was adjusted} so that the C characteristic curve drops so far that no change in the driver _voltage results in an increase in capacity. This evaluation thus provides information about the magnitude of the internal gate resistance R _Gint .

The influence of the gate inductance L _G is relatively small and is limited only to the region of the characteristic curve where the gate current has steep edges (cf. 24 and 25 ). The gate inductance was calculated as L _G = 25 nH. How the estimation was based on the design drawing of the MOSFET used is described in Section 4.2.2.2. - Determination of the inductors and resistors - explained in more detail.

For the magnitude of the internal drain resistance and the connection resistance, neither metrological information nor data sheet information is available. The curve in 26 shows the influence on the characteristic curves, if the sum of these resistances amounts to 2 mΩ. A better estimate may be found in section 3.5.6. - Dependence of the reaction capacity on the load current - take place where the capacitance characteristics for different load currents are compared with each other.

The drain inductance influences the characteristics relatively weakly in the regions where the drain current has steep edges (cf. 27 and 28 ). The drain inductance was calculated as L _D = 3.5 nH. How the estimation was done is described in Section 4.2.2.2. - Determination of the inductors and resistors - explained in more detail.

29 and 30 show the simultaneous action of the parasitic elements.

The corrected evaluation was also performed for the Crss _LS characteristic curves with R _G = 180 Ω or R _G = 330 Ω. The results are in 31 and 32 summarized. It is noticeable that the influence of the parasitic elements is dependent on the switching speed or gate resistance. The comparison of the Crss _LS characteristics for different gate resistors after the improved evaluation in 33 shows that the characteristics, apart from numerical problems, are identical in large areas. This is an indication that the estimation of the parasitic elements is very accurate. The only obvious difference is in the area of the overvoltage, since different voltage peaks are reached depending on the switching speed and vibrations are pronounced differently.

Of the Comparison also makes it clear that it makes sense to use the C characteristic from switching characteristics with the highest possible gate resistances to determine, in particular, if no information about the parasitic elements are present.

3.5.2.2. Differential reaction capacity Crss _diff (R _G )

Using the findings of the previous section, a detailed analysis of the dependence of the differential capacitance on the gate resistance R _{G can be} omitted in this section. The 33 shows that the charge curves Qr (V _DG ) for determining the large signal capacitance - taking into account the voltage drops across the parasitic resistors and inductors for the different gate resistances - must be almost identical, except for the range of the overvoltage. Due to the resulting differences in the area of the DC link voltage, the switching speed of the fitting must be taken into account when determining the capacitance characteristics. Therefore, the determination of the differential reaction capacity for a fast (R _G = 10 Ω) and a very slow (R _G = 330 Ω) Ausschaltverlauf is explained in more detail. 15 . 16 . 17 and 18 make it clear, however, that the direct determination of this capacitance characteristic from the measurement data can be qualitatively unsatisfactory for large areas. The poor quality of the characteristic curve is caused by the numerical differentiation of the noisy characteristic Qr (V _DG ). Direct fitting in section 3.5.1. - Determination of the reaction capacity - determined C _diff (V _DG ) characteristic does not lead to a meaningful result. Therefore, two variants are explained below, how to determine the differential capacitance Crss _diff from the previous results, and compared with each other using the example of the C characteristic curves for the mentioned gate resistors.

version 1

It is obvious that the fitting of the characteristic Qr (V _DG ) would solve the numerical problems in the determination of the differential capacity. The method also allows the assumption that the fitted charge characteristic Qr (V _DG ) also improves the quality of the large signal capacity. A disadvantage is the fact that sometimes there is no one-to-one correspondence depending on the switching speed in the area of the overvoltage. The faster the switching process, the stronger this effect will be. Thus, in the fit in these areas, a meaningful nutrition must be made.

Variant 2

Section 3.2 - Nonlinear Capacitance - Large Signal and Small Signal Capacitance - explains the basics for determining large-signal capacity and differential capacitance. Thus, after equating the current equations (3.2) and (3.10) and corresponding transformations, we obtain:

Using this relationship, the differential capacitance can be determined. However, the same numerical problems would occur in the direct differentiation of the charge curve, if the conversion would take place on the basis of the determined Crss _LS (V _DG ) characteristic curve. Therefore, the Crss _LS (V _DG ) characteristic must also be fitted. Advantage of this approach is that the relationship between the large signal capacity and the differential capacity is clarified. However, fitting the Crss _LS (V _DG ) characteristic gives the same problems as fitting the Qr (V _DG ) characteristic.

mit Hilfe von TableCurve 2D ermittelt, wobei die Abszisse x der Drain-Gate-Spannung und die Ordinate y der Großsignalkapazität Crss_LS bzw. der Ladung Qr entspricht.In principle, the two variants are equivalent. However, deviations are to be expected when comparing the determined characteristic curves, which result from the fact that the characteristic curves can be simulated differently well by polynomial approximation. When fitting the Crss _LS (V _DG ) or the Qr (V _DG ) characteristic, the values of the polynomial coefficients of the polynomial become

with the aid of TableCurve 2D, where the abscissa x corresponds to the drain-gate voltage and the ordinate y corresponds to the large-signal capacitance Crss _LS or the charge Qr.

Subsequently, the differential capacitance is first determined at a gate resistance of 330 Ω. 34 compares the characteristic curve Crss _{diff_1} (V _DG ) determined according to Variant 1 with the Crss _diff (V _DG ) characteristic curve, which results from the measured data taking into account the parasitic elements, and shows how the Qr (V _DG ) was fitted.

The application of equations (3.3) and (3.23) makes it clear that in the case of fit, the absolute values of the Qr characteristic are not so important, but it is much more important that the corresponding increases over wide ranges of characteristics are reproduced as much as possible , When passing through the Qr characteristic during turn-off Qr increases steadily and thus has a positive increase dQr / dt even in the area where it can no longer be said that there is a one-to-one correspondence. The differentiation of in 34 shown characteristic curve Qr _fit (V _DG ) results in the Ausschaltverläufen, but where the drain-gate voltage drops briefly, a negative differential capacitance , since Qr decreases, however, to -V _DG . However, since this area has a comparatively minor importance, it is neglected in the approximation. However, the ranges of the characteristic curve Qr, which result in a positive differential capacitance, are approximated in such a way that, although the absolute values of the characteristic in the region of the intermediate circuit voltage are not exact, the increase dQr / dV _DG does.

In 35 the time characteristic of the characteristic curves is shown. Both figures also make it clear that the charge curve can not be reproduced correctly, even for very slow switching characteristics through the polynomial after reaching the overvoltage.

Indeed the approximations made have little influence on the differential capacity. Only the area the capacity history in which the capacity is short-term is going back, is buggy.

36 shows that the use of the polynomial to determine the large signal capacitance results in a pole at V _DG = 0V. Thus, the fitted Qr (V _DG ) characteristic is not suitable for determining the large signal capacity. In addition, the approximation in the area of the intermediate circuit voltage has an influence on the large signal capacity and falsifies it correspondingly more.

37 shows results of the evaluation according to variant 2 for two different polynomials for Crss _LS . It is noticeable that the Crss _diff (V _DG ) characteristic is very sensitive to the fit of the large signal capacitance. Therefore, the selection of coefficients should be done very carefully. The differential capacitance depends, in particular, on how the approximation function continues beyond the measuring points (see FIG 38 (Fit A for Crss _LS ) and 39 (Fit B for Crss _LS )). In addition, according to equation (3.30), both the value Crss _LS and the increase dCrss _LS / dV _{DG of} the characteristic curve are included in the calculation of the differential capacitance. However, if one compares the results of the two variants, it becomes clear that, as expected, they lead to similar results (cf. 40 ).

While the determination of the Crss _{diff characteristic} curve for slow turn-off profiles seems relatively straightforward, the fitting of the fast turn-off characteristics due to the voltage oscillations is only possible for certain areas. In the following, the two determination variants of the capacitance Crss _diff are again compared with one another for a fast switch-off process (R _G = 10 Ω).

version 1

41 shows first the polynomial, which was determined by TableCurve 2D from the measured data (V _DG (t); Qr (t)), and the corresponding differential capacitance. At first glance, the polynomial seems to be justified, as it effectively forms an average of the measurement points in the area where there is no one-to-one correspondence. With the aid of this polynomial, the correct final value of the charge is achieved, and in the quasi-stationary state, the differential capacitance has a value close to zero. However, taking into account the physical relationships and consideration of the function to be adopted, it becomes clear that this polynomial can not be used. The charge in the reaction capacity increases continuously. If, on the other hand, the determined polynomial is used, this would mean that the current would flow alternately into and out of the capacitor until it reaches the intermediate circuit voltage, until it reaches the voltage peak from the capacitance and then to the stationary final state. However, taking into account the temporal relationships, the increase in the charge curve is consistently positive and tends to decrease after the voltage peak reaches steady state. Since it is not possible to fit the Qr (V _DG ) characteristic correctly, it is recommended to approximate the characteristic curve up to the maximum voltage for the fast switch-off characteristics and to determine the differential capacitance from this function. The applicator must then be aware of the fact that the characteristic applies to the voltage peak and the value of the differential capacitance thereafter tends to be smaller than the value which is indicated at the corresponding voltage in the characteristic curve. 42 shows the determined characteristic.

A closer look at the Crss _diff (V _DG ) curve reveals something that justifies the previously recommended procedure. For clarity shows 43 a "zoom in" 42 , As bad as the quality of the Crss _diff characteristic may be in some areas, this figure confirms the previous statements and allows a further statement about the differential capacitance after the overvoltage. Thus, the differential capacitance after the overvoltage peak during fast switching operations during the positive voltage increases is much smaller than before. The recommended modeling of the characteristic curve up to the overvoltage peak thus takes into account the influence of the retroaction capacity very well, then too large capacitance values are applied, which makes the calculated or simulated switching characteristics in this range too slow. During the negative drain-source voltage increases, the differential capacitance is negative. With this knowledge, the characteristic curve can also be shown as an amount:

By this measure, the lower part of the characteristic is mirrored upward (see. 44 ). The task of an application engineer would then be to consider this relationship if necessary.

• • Crss_diff(V_DG) kann für die lokalen Hoch- und Tiefpunkte der Drain-Gate-Spannung numerisch nicht bestimmt werden, da dort die Gleichungen (3.27) und (3.28) nicht anwendbar ist (Die Division durch Null ist nicht möglich).
• • Die differentielle Kapazität bricht bei schnellen Schaltverläufen nach der Spannungsspitze betragsmäßig zusammen. Dabei liegt während des Schwingens der Spannung das Minimum der differentiellen Kapazität bei V_DClink. Bei höheren und niedrigeren Drain-Gate-Spannungen erhöht sich die differentielle Kapazität.
• • Je kleiner die Amplitude der schwingenden Drain-Gate-Spannung wird, umso tiefer liegt das Minimum bis die differentielle Rückwirkungskapazität schließlich im stationären Zustand 0 nF beträgt.

From the 43 and 44 the following further statements can be derived:

• • Crss _diff (V _DG ) can not be determined numerically for the local high and low points of the drain-gate voltage, since the equations (3.27) and (3.28) are not applicable there (the division by zero is not possible).
• • The differential capacity collapses according to the peak voltage in the case of fast switching processes. During the swing of the voltage, the minimum of the differential capacitance _lies at V _DClink . At higher and lower drain-gate voltages, the differential capacitance increases.
• • The smaller the amplitude of the oscillating drain-gate voltage, the lower the minimum until the differential reaction capacitance finally reaches 0 nF in the stationary state.

Variant 2

The knowledge gained from the fit of the charge curve is transferred accordingly to this evaluation variant. Thus, the Crss _{LS characteristic is} fitted to the maximum drain-gate voltage. 45 represents two different fit functions Crss _{LS_fitA} and Crss _{LS_fitB} and the differential capacitances Crss _{diff_A} and Crss _{diff_B} determined therefrom and again shows how sensitive the differential capacitance reacts to the fit functions.

46 compares methods 1 and 2 with each other and makes clear that both methods are also equivalent for fast turn-off characteristics. In this case, the indices "1" and "2" stand for the variant used to determine the differential capacitance, and "A" and "B" for the fit function itself.

47 forms the ascertained curves of the differential capacitances for three different gate resistors stand off. It is noticeable that the Crss _diff characteristics are also the same over large areas. Only at larger drain-gate voltages, the characteristics rise again depending on the gate resistance. 48 shows in addition to 47 still the time course over the drain-gate voltage during switching. For the 10 Ω curve, the characteristic is only shown until the overvoltage is reached. The diagram suggests that these time functions are scalable in certain areas. Further investigation may perhaps derive a function Crss _diff , which takes into account the increase of the C-characteristic as a function of the gate resistance R _G.

In addition to the described variants 1 and 2, another attempt to determine the differential capacitance with R _G = 10 Ω was performed. If the time constant of the PT1 element is increased, the measured data are smoothed out more. However, this also means that the edge steepness is lost and the amplitudes fall (cf. 49 ). All the more surprising is the Crss _{diff characteristic} curve, which is determined from these curves. 50 corresponds to 41 , Qr and Crss _diff result from the strongly smoothed measurement data. For reference, the fit of the Qr characteristic, which was determined from the original, much weaker smoothened measurement data, and the resulting Crss _diffB characteristic is shown in the figure. The figure illustrates that this evaluation leads to comparable results, only the effect of breaking down the differential capacitance after the voltage spike is lost. However, this effect can not be taken into account in a simple simulator anyway. Thus, this procedure provides a lot of information necessary for the parameterization of the simulator and is therefore equivalent and less expensive.

3.5.2.3. Summary Section 3.5.2.

• The large signal feedback capacity is relatively independent of the gate resistance R _G.
• • The switching speed affects the range the characteristic relatively strong, where by different strong increases the drain current overvoltages pronounced different degrees become.
• • The influence of parasitic resistances and inductances on the characteristic curves determined from measured data the smaller, the greater the gate resistance.
• • There is a method for metrological determination of the internal gate resistance.
• • The large signal feedback capacity can only operate at low gate resistances up to the maximum of the drain-gate voltage be approximated by a polynomial.
• • The large signal feedback capacity can be used for very large gate resistances good approximation can be modeled by a polynomial.
• • The question remains, by which (physical) Effect on slow switching operations, the increase in capacitance characteristics after the voltage commutation and the breakdown of the differential capacitance with small gate resistances after reaching the voltage peak is caused.
• • In order to determine a high-quality differential reaction capacity, either the charge curve Qr (V _DG ) or the large-signal reaction capacity as a function of the switching speed must be sensibly approximated by a polynomial.
• • The differential feedback capacity can be derived from the large signal reaction capacity derived.
• • The differential feedback capacitance is also relatively independent of the gate resistance R _G , but the influence of the switching speed on the characteristic in the area of the DC link voltage is very high.
• • Due to increased smoothing The measurement data may be relative to the differential capacitance be determined easily and accurately.

3.5.3. Parallels between feedback capacity and MOS capacity

• • Die Großsignalrückwirkungskapazität vergrößert sich beim langsamen Ausschalten im Zeitverlauf ab einer bestimmten, vom Gatewiderstand abhängigen positiven Drain-Gate-Spannung (33).
• • Auch bei schnellen Ausschaltverläufen steigt die Großsignalrückwirkungskapazität nach der Überspannungsspitze zunächst an, fällt und steigt dann jedoch mit dem Spannungsschwingen und erreicht denselben Endwert wie die Kapazitätswerte, die aus den langsamen Verläufen ermittelt wurden (33).
• • Beim Ausschalten steigen die differentiellen Kapazitäten bei positiven Drain-Gate-Spannungen in Abhängigkeit vom Gatewiderstand bei verschiedenen Drain-Gate-Spannungen wieder an.
• • Bei schnellen Ausschaltvorgängen vergrößert sich die differentielle Kapazität Crss_diff nach der Überspannung nicht weiter, sondern liegt während des Einschwingens auf die Zwischenkreisspannung unter der Kennlinie, die bis zur Überspannung ermittelt wurde.
• • Dagegen steigt bei langsamen Ausschaltvorgängen die differentielle Kapazität Crss_diff nach dem Übergang in den waagerechten Bereich ab einer vom verwendeten Gatewiderstand abhängigen positiven Drain-Gate-Spannung wieder an.

The consideration of the feedback capacitance as a function of the switching speed has shown that the capacitances behave differently for large positive drain-gate voltages depending on the gate resistance used:

• • The large signal feedback capacity increases with the slow turn-off over time from a certain, dependent on the gate resistance positive drain-gate voltage ( 33 ).
• • Even with fast turn-off characteristics, the large-signal feedback capacitance initially rises after the overvoltage peak, but then drops and then rises with the voltage swing and reaches the same final value as the capacitance values obtained from the slow-running waveforms ( 33 ).
• • On turn-off, the differential capacitances increase at positive drain-to-gate voltages as a function of gate resistance at different drain-to-gate voltages.
• • In the case of fast switch-off processes, the differential capacitance Crss _diff does not increase further after the overvoltage, but lies below the characteristic that was determined up to the overvoltage during the transient to the intermediate circuit voltage.
• • On the other hand, with slow turn-off operations, the differential capacitance Crss _{diff increases} after the overshoot transition in the horizontal range from a dependent of the used gate resistance positive drain-gate voltage again.

So far was considered in this work on a semiconductor-physical view the reaction capacity and an explanation, which structure causes the capacitive behavior, waived. However, the question arises, causing the strong Voltage dependence of the reaction capacity caused will and how the effects described above come about.

The feedback capacitance is determined during the switching between gate and drain. Comparing the MOSFET Cell with Trench Gate ( 51 ) with a MOS capacitor ( 52 ) it becomes clear that the reaction capacitance essentially represents a capacitor with the layer structure metal oxide semiconductor. Thus, there is a relationship between the differential feedback capacitance, which is determined from the dynamic measurements, and the small-signal capacity of MOS structures or the behavior of these capacitances should have parallels. Subsequently, states on the semiconductor surface of an ideal MOS capacitor become simplified explained, resulting in accordance with the applied gate voltage. A more detailed explanation, including the fundamentals of semiconductor physics, can be found in the numerous available literature on this topic.

If a voltage is present at the gate contact, the gate electrode is occupied by the charge Q _G. The semiconductor reacts to this with a counter charge, which can be described by the bending of the energy band model at the semiconductor surface, because particles (holes and electrons) tend to preferentially occupy positions with minimal energy. Based on an n-type semiconductor, the following states are distinguished depending on the applied voltage. The corresponding energy curves in the band model for the n-type semiconductor are in the 53 (with a) accumulation; b) depletion; c) inversion and E _C - lower energy edge of the conduction band, E _F - Fermi level, E _i - intrinsic energy and E _v - upper energy edge of the valence band).

1. Enrichment (accumulation)

If a positive voltage is applied to the gate, electrons in the semiconductor are attracted towards the gate and accumulate there. The amount of charge depends on the oxide capacity and the applied voltage. The oxide capacity, which is formed by the sequence of layers of metal-oxide-semiconductor, corresponds to a plate capacitor and is voltage-independent:

In the enrichment state, the n-doped semiconductor has a hole surplus on the metal-oxide interface and an excess of electrons on the semiconductor surface. Both charge layers are very thin. Almost the entire voltage drops over the insulation layer. The voltage drop across the charged layers in the metal and on the semiconductor surface can be neglected [10]. The acting capacity in the enrichment state can thus be represented very well by two thin charge layers with the intervening insulator and thus corresponds to the oxide capacity C _ox .

2. depletion

die über die Breite d_d von der Spannung V_d über der Raumladungszone bzw. der Verarmungszone abhängt [11]. Es kann also nicht mehr davon ausgegangen werden, dass die gesamte Spannung am Isolator abfällt. Die gesamte MOS-Kapazität setzt sich somit aus der Reihenschaltung der Raumladekapazität und der Oxidkapazität zusammen

If the gate voltage is negative, the electrons are forced away from the boundary layer into the semiconductor. The counter charge is formed by the ionized donor atoms. This creates a depletion zone at the insulator-semiconductor interface. However, the charge carrier density is substantially lower than in the enrichment zone, since the doping atoms are stationary. The field lines beginning at the gate electrode terminate at the stationary donor impurities of the near-surface silicon. This results in the surface of the originally neutral semiconductor surface becoming depleted near the surface with a voltage-dependent width d _d . This space charge zone of the semiconductor has the capacity

which depends on the width d _d on the voltage V _d over the space charge zone or the depletion zone [11]. It can therefore no longer be assumed that the entire voltage across the insulator drops. The total MOS capacitance is thus composed of the series connection of the space charge capacity and the oxide capacity

3. Inversion (inversion)

If the gate voltage continues to fall, the depletion zone continues to expand and the space charge capacity and thus also the MOS capacitance decrease. At higher negative gate voltages, the ionized donor atoms can not alone apply the gate counter charge. Therefore, floating holes, the minority carriers of the n-type semiconductor, are pulled to the surface to compensate for the gate charge. The number of minority carriers can become so large that their number becomes larger than that of the majority carriers. Then one speaks of inversion, since the surface layer of the semiconductor is inverted and thus becomes p-type. In the band model, this is illustrated by the fact that the Fermi level in this area is below the band center E _i . Inversion, especially in strong inversion, now has a similar case to enrichment because the charge carrier density is again relatively high. The capacity of the depletion zone in the inversion region increases sharply by the minority charge carriers, so that in the steady state again corresponds to the oxide capacity of the entire MOS capacity. (When large negative voltages are suddenly applied, this inversion layer can not be instantaneous, due to the relatively slow supply of minority carriers (holes), so the state of deep depletion first appears on the surface.)

The characterization of a MOS capacitor is usually done by a C / V measurement. In this case, the profile of the small-signal capacitance at different excitation frequencies over the applied DC voltage is recorded on the MOS structure. 55 outlines the corresponding characteristic field, which results at a voltage ramp superimposed with an alternating voltage ( 54 ).

• Niederfrequenz (< 100 Hz): Die Löcher in der Inversionsschicht können dem Verlauf der Wechselspannung folgen. Die Kleinsignalkapazität steigt wie im Anreicherungszustand auf den Wert von Cox an.
• Hochfrequenz (>> 100 Hz): Die Anzahl der Löcher in der Inversionsschicht kann sich nicht schnell genug ändern, die gemessene MOS-Kapazität bleibt auf ihrem Minimalwert. Die MOS-Kapazitätskurve und damit der elektronische Zustand der Halbleiteroberfläche hängen beim realen Kondensator stark von weiteren Einflüssen ab: – Ladungen, die sich in der Umgebung der Isolator-Halbleitergrenzfläche befinden und – der Metall-Halbleiter-Austrittsarbeit.

High positive biases attract majority carriers to the boundary layer. The charged layers are thin and close to the insulator. This results in a small signal capacity close to the value C _ox . We have C _MOS ≈ C _ox (since C _d >> C _ox ). The majority charge carriers are the only charge carriers that move here. They can reduce space charge disturbances within a few multiples of the dielectric relaxation time τ (charge time constant / characteristic return time to equilibrium / charge carrier lifetime), are predominantly involved in the charge change in the enrichment and depletion region, and respond rapidly to excitation frequencies of up to several MHz. For this reason, the high and low frequency curves in this area are close to each other. As the DC voltage becomes more negative, the capacitor slowly enters inversion and a depletion zone is formed. As long as the number of minority carriers at the interface is negligible (ie depletion), the change in the stored charge depends only on the expansion and contraction of the depletion zone as a result of the applied small signal AC voltage. The MOS capacitor in this range consists of the oxide capacity C _ox in series with the capacity of the depletion zone C _d (see Equation 3.30). C _ox is constant, but C _d changes with the potential applied to the depletion zone (C _d ≤ C _ox ). With decreasing gate voltage, C _d and thus also C _{MOS become} smaller since the depletion zone expands until an inversion layer forms. With strong inversion, the width of the depletion zone and the voltage V _d dropping across it remain almost constant for different gate bias voltages. For high-frequency or low-frequency excitations, different capacity curves are obtained in this area, since mainly the minority charge carriers determine the charge budget. In order to achieve equilibration, they take much more time than the majority carriers because many processes, such as volume generation and depletion and enhancement regions, may be responsible for the minority charge change. Only if the set time (change of voltage and frequency) is sufficient for the respective attainment of the equilibrium values does the inversion capacity assume calculable values. [12] However, if the voltage change is too fast compared to the set time, the minorities do not reach their equilibrium values. They are only partly or not involved in the transhipment. The inversion capacity thus becomes frequency-dependent:

• Low frequency (<100 Hz): The holes in the inversion layer can follow the course of the AC voltage. The small-signal capacity increases to the value of Cox as in the enrichment state.
• High frequency (>> 100 Hz): The number of holes in the inversion layer can not change fast enough, the measured MOS capacitance remains at its minimum value. The MOS capacitance curve and thus the electronic state of the semiconductor surface are strongly dependent on further influences in the real capacitor From: - charges that are in the vicinity of the insulator-semiconductor interface and - the metal-semiconductor work function.

These influences lead to a shift of the CV characteristic with respect to the ideal value at V _G = 0 and thus to the existence of a band bending in the de-energized state. [11] However, they can also cause electrical instabilities in the MOS structure, which are essentially in the form of hystereses of the CV history. Of course, the ratios of the MOS capacitor can not be directly transferred to the feedback capacitance of the present trench gate MOSFET. On the one hand, each MOSFET has a plurality of semiconductor layers of different doping, which adjoin the oxide layer and thus contribute to the gate counter charge, and, on the other hand, there is insufficient information about the component used, for example about the geometric chip structure. It can be assumed that, in addition to the pure MOS capacitance, other capacities also influence the retroaction capacity. However, a more detailed analysis is omitted here, since the aim of this work is not the consideration of semiconductor physics. Even without further investigation, the described states of the MOS capacitance can be transferred to the observed turn-off behavior of the capacitance between the drain and the gate contact during the switching.

In section 3.2. - Nonlinear capacitance - Large signal and small signal capacitance - It has been shown that the small signal capacitances and the differential capacitances at the operating point are equal under otherwise identical conditions. This conditionality is not given due to the different measurement methods. Nevertheless, taking into account the properties of the real MOS capacitor, a similar behavior can be observed when the C / V curves in 54 with the characteristics given in Section 3.5.2.2. - Differential reaction capacity Crss _diff (R _G ) - are shown, compares. It should be noted that the determined characteristics are shown above the drain-gate voltage. This voltage corresponds to the negative gate voltage of the MOS structure.

The characteristic curves of the differential reaction capacity clearly show the depletion region. Since in this area mainly the majority charge carriers compensate for electrical imbalances, according to the previously explained theory no dependence on the switching speed is to be expected and also not established (cf. 47 ). The characteristics are almost identical. The determined characteristic curves have been determined from transient processes and thus time-dependent and not frequency-dependent. However, the frequency-dependent behavior of the capacitance can also make the measured time courses plausible. Thus, the transition to the shallow region at approximately V _DG = 5V indicates inversion at the semiconductor surface. First of all, the transients during the voltage commutation are so large for all switching operations that the minority charge carriers can not react fast enough and the characteristic curves therefore initially remain at the minimum value. The size of the gate resistance used influences, via the gate current intensity, how fast the output characteristic field is traversed during the current commutation or which voltages drop across the commutation inductances and thus finally how high the voltage rise across the switched-off switch is after reaching the intermediate circuit voltage. 56 (Switch-off characteristic with modeled Crss _diff characteristic: V _DClink = 30V, I _L = 150A, R _G = 10Ω and T _J = 25 ° C) and 57 (Switch-off characteristic with modeled Crss _diff characteristic: V _DClink = 30 V, I _L = 150 A, R _G = 330Ω and T _J = 25 ° C) illustrate that the minimum capacitance value is maintained as long as the drain gate Voltage has a sufficiently large increase. If this is lower, the minority carriers can also follow the voltage changes and the capacitance increases according to the theory. This behavior can be observed in all investigated switching curves. The corresponding characteristic fits also reflect this behavior very well. In general terms, it can be stated that the fit functions of the C characteristic curves until the overvoltage is reached well simulate the real behavior during slow and fast switching operations. During the switch-off processes, the inaccuracies in the differential characteristic of the feedback capacitance Crss _diff begin, as far as time is concerned, after reaching the voltage peak.

In further investigations it was to be determined whether a function can be determined which, depending on the voltage increase, increases the increase of the differential reaction capacity in the In version range and can be integrated into the present simulator. Frequency-dependent characteristics are not suitable for the exact simulation of switching operations, since the time-dependent characteristic curves contain a multiplicity of frequencies. By Laplace transformation from the time-dependent characteristic, a broad spectrum of frequency-dependent characteristics can be determined. For this reason, it should also be checked in further work whether the functions derived from the time measurement and converted into frequency-dependent characteristic curves by laplace transformation correspond to a good approximation to the frequency-dependent small-signal characteristics. If so, an investigation could be made which provides a general analytic context, depending on the pulse period and duty cycle, that allows conversion from the frequency domain to the time domain. The resulting investigation effort can be justified by the fact that the small signal capacity determination with the corresponding measuring devices is much faster than the complex evaluation of the measured data to determine the capacitance characteristics.

3.5.4. Comparison of the reaction capacity when switching on and off

When a switch is turned on and off, the output characteristics field will vary due to the effects described in Chapter 2. (The corresponding schematic representation shows 6 in section 2.3.2. - dV _DS / dt - feedback through the drain-gate capacitance is described.) To what extent this "path" through the output characteristic field has an influence on the feedback capacitance characteristic will be examined in this section, in Section 3.5.2 - Dependency of the Reaction Capacitance of switching speed - it has been found that it is advantageous to obtain the characteristic curve from the measured data obtained from dynamic measurements with high gate resistances, since the vibrations which make the evaluation more difficult are therefore largely dampened Evaluation of the measured data for switching operations with a gate resistor of 180 Ω.

58 compares the large signal feedback capacitance characteristics of a switch-on with that of a corresponding switch-off. The result is surprising insofar as the two voltage-corrected capacitance characteristics do not meet at the same points in the stationary state. Alone for the off state, this seems almost the case. Consider the corresponding charge curves Qr _on and Qr _off in 58 , it is noticeable that they too diverge.

In order to investigate this phenomenon, further measurement curves were recorded, which were published in 59 (Time course of the variables I _D , V _DS , V _GS and the arithmetic variable V _DG during switching on and off of the switch with R _G = 180 ohms, V _DClink = 30 V, T _j = 25 ° C and I _L = 150 A) and 60 (Time course of the variables I _D , V _DS , V _GS and the arithmetic variable V _DG during switching off, on and off of the switch with R _G = 180 ohms, V _DClink = 30 V, T _j = 25 ° C and I _L = 150 A), and determines the associated charge curves. The latter will be in 61 and 62 presents. The offset Q _Gtot (t _v ) in equation (3.28) was chosen so that in the first drain-gate voltage zero crossing the charge Qr is equal to zero. At this point in the work, the principle of measurement has to be pointed out again: The current working point is determined by the duration of the first drive pulse in addition to the suitable selection of the load inductance. Therefore, the illustrated or examined measurement series start with a switch-off process.

A possible interpretation of 61 (Course of the charge Qr (V _DGchip ) during switching on and off of the switch with R _G = 180 ohms, V _DClink = 30 V, T _j = 25 ° C and I _L = 150 A) and 62 (Course of the charge Qr (V _DGchip ) during switching off, on and off of the switch R _G = 180 ohms, V _DClink = 30 V, T _j = 25 ° C and I _L = 150 A) is that to turn off a larger amount of charge is necessary than to turn on. However, before this thesis is examined more closely, it must be ruled out that this effect was caused by measurement errors in the Gatestrommessung. The determination of the gate current is problematic because both the Pearson probe and the oscilloscope leads to an offset of the gate current in the measurement. Added to this is the measurement noise. It is practically impossible to measure a 0A or 0V line.

Therefore, the same switching characteristics were re-examined and the measurement data modified so that the gate current was set to zero in certain areas. The results and the associated measured data with gate current are shown in the figures 63 : Time course of the measured variables I _D , V _DS , V _GS ; I _G and the arithmetic variable V _DG during turning off and on of the switch (R _G = 180 ohms, V _DClink = 30 V, T _j = 25 ° C and I _L = 150 A); 64 : Modified charge Qr (V _DGchip ) during switching off and on of the switch (R _G = 180 ohms, V _DClink = 30 V, T _j = 25 ° C and I _L = 150 A); 65 : Time course of the measured variables I _D , V _DS , V _GS ; I _G and the arithmetic variable V _DG while switching the switch off and on again (R _G = 180 ohms, V _DClink = 30 V, T _j = 25 ° C and I _L = 150 A) and 66 : Modified charge Qr (V _DGchip ) during switch off, on and off (R _G = 180 ohms, V _DClink = _30V , T _j = 25 ° C and I _L = 150 A). There is an approximation of the on and off characteristics, but there is still a difference in the amount of charge for switching on and off. It remains to be investigated whether a shift of the gate current along the ordinate can influence the result. If, for simplification, one assumes identical resistances in the gate circuit in the switched on and off state, the current peaks would have to have the same amounts. However, the gate current peak when turning off is slightly higher than that at power up. In addition, the gate current in the stationary states is slightly negative. The cause of the identified increased charge demand when switching off could therefore well be due to the measurement technique, which causes a shift in the measured quantities in the data acquisition. That is why the pictures document 67 . 68 . 69 and 70 the results of an offset correction of the gate current. It was decided not to set the gate current in the corresponding areas to zero.

The results obtained after the offset correction of the gate current I _G suggest that the observation to turn on less gate charge than turn it off is most likely due to measurement errors. It must be documented at this point that the offset correction of the two switching characteristics is different. So was for the in 67 (Time course of the measured variables I _D , V _DS , V _GS , I _{G_offset} and the _arithmetic variable V _DG during switching the switch on and off (R _G = 180 ohms, V _DClink = 30 V, T _j = 25 ° C and I _L = 150 A)), an offset correction of the gate current of 0.25 mA and for the in 69 (Time course of the measured variables I _D , V _DS , V _GS , I _{G_offset} and the _arithmetic variable V _DG during switching off, on and off of the switch (R _G = 180 ohms, V _DClink = 30 V, T _j = 25 ° C and I _L = 150 A)), an offset correction of 0.4 mA is made. Further investigations in this regard would be interesting because of the possible predictability of the systematic error. In order not to go beyond the scope of the present work, this is omitted here.

In the diagrams 68 (Modified charge current Qr (V _DGchip ) during switch off and on after offset correction of I _G (R _G = 180 ohms, V _DClink = 30 V, T _j = 25 ° C and I _L = 150 A)) and 70 (Modified variation of the charge Qr (V _DGchip ) during switching off, on and off of the switch after offset correction of I _G (R _G = 180 ohms, V _DClink = 30 V, T _j = 25 ° C and I _L = 150) A)), two areas are visible in which the charge curves differ from switching on and off. The differences in the higher drain-gate voltages are due to the different characteristics of the output characteristic field. To what extent the switching on and off behavior of the internal inverse diodes has an influence on the deviations should be estimated in further investigations. The following picture 71 represents a section 68 The curve can certainly as a charge hysteresis and suggests that the charge curve Qr determined using equations (3.27) and (3.28) does not accurately reflect reality. It is to be assumed that the charge amount in the feedback capacitance is zero zero Coulomb neither during turn-on nor turn-off at V _DG = 0V. This hysteresis is known in the relevant literature and is referred to as a charge trapping effect. It is caused by the fact that when the transistor is turned on, some of the charge carriers in the channel are drawn into the gate dielectric due to the electric field which arises when a gate voltage is applied. This accumulation of charge carriers in the gate dielectric results in a shift of the threshold voltage and a reduction of the drain current [14]. Remarkable or new 68 . 70 and 71 is that this effect can apparently be examined by evaluating dynamic measurements. Various measurement methods such as DC V _GS -I _D or high-frequency CV measurements are used to detect the phenomenon. The gate voltage is ramped up and down while the drain current or gate capacitance is being measured. The fact that charge trapping and detrapping depend on the measuring time has given rise to a large number of scientific papers dealing with the quantification of the "trapped charge", the development of appropriate measuring methods and their advantages and disadvantages Charge trapping can also be investigated by means of dynamic measurement data, which could play a role in this discussion, can not be estimated in this work.The importance of charge trapping - especially with regard to high κ gate dielectrics - is not negligible physically: it influences the stability of the threshold voltage [18], [19], [20], [21], the charge-carrier mobility in the channel [15], [16], [17] and the lifetime of the transistor [22], [23], [24], [25] The phenomenon of charge trapping also has an impact on switch capacity and losses, is understandable Influence of the losses is omitted in this work. The. However, capacitance characteristics are again determined from the measured data with the corrected gate current profile. It must be noted that this correction is only in the context of the evaluation of the dependence of Characteristic was made by switching on and off , In the following sections, which deal with the dependence on the temperature, the load current and the intermediate circuit voltage, no offset correction of the gate current has been made, so that the large signal capacities shown when switching on and off sometimes differ in the stationary states. However, this has a negligible influence on the effect of the operating conditions on the characteristic and the derived statements.

• • Die Großsignalrückwirkungskapazitätskennlinien unterscheiden sich beim Ein- und Ausschalten voneinander.
• • In den stationären Endpunkten entsprechen die Großsignalkapazitäten beim Ein- und Ausschalten einander.
• • Die Ausschaltkennlinie liegt während des Schaltvorganges bei negativen Drain-Gate-Spannungen über und bei hohen positiven Drain-Gate-Spannungen unter der Einschaltkennlinie.
• • Je nachdem, wofür die Kapazitätskennlinie verwendet werden soll, muss abgeschätzt werden, ob eventuell ein Mittelwert zwischen den Ein- und Ausschaltkennlinien gebildet werden kann oder sowohl die Ein- als auch die Ausschaltkennlinie benötigt wird. Denkbar ist auch, dass beispielsweise die Verwendung der Ausschaltkennlinie eine ausreichende Genauigkeit bei der simulativen Abschätzung der Schaltverluste liefert. Durch simulative Untersuchungen können Antworten auf diese Fragen gefunden werden. Sie werden ansatzweise in Abschnitt 4.3. – Untersuchungen der Kapazitätskennlinien in einem Arbeitspunkt – durchgeführt.

Based on the improved evaluation in 72 (Comparison of the on and off characteristics Crss _LS (V _DGchip ) after offset correction of I _G during switching off and on (I _L = 150 A, V _DClink = 30 V, T _j = 25 ° C and R _G = 180 ohms) ) and 73 (Comparison of the on and off characteristics Crss _LS (V _DGchip ) after offset correction of I _G during off, on and off switching (I _L = 150 A, V _DClink = 30 V, T _j = 25 ° C and R _G = 180 ohms)), the following statements can be summarized:

• • The large signal feedback capacity characteristics are different when turned on and off.
• • In the stationary endpoints, the large signal capacities on switching on and off correspond to each other.
• • The switch-off characteristic is at negative drain-gate voltages during the switching process and below the switch-on characteristic at high positive drain-gate voltages.
• • Depending on what the capacitance characteristic is to be used for, it must be estimated whether an average value may be formed between the switch-on and switch-off characteristics or whether both the switch-on and switch-off characteristics are required. It is also conceivable that, for example, the use of the switch-off characteristic provides sufficient accuracy in the simulative estimation of the switching losses. Through simulative investigations, answers to these questions can be found. They are gradually used in section 4.3. - Examinations of the capacity curves at one operating point - carried out.

The curves of the charge curve Qr and the capacitance characteristics Crss _LS , which result after the offset correction of the gate current, illustrate that the differential capacitances differ during switching on and off. The differential capacitance is more suitable for the simulation due to the simplified associated current equation. Nevertheless, at this point, the determination of this characteristic for switching on and off is initially dispensed with. However, the determination will be made in Section 4.3. - Examinations of the capacity curves at one operating point - made up for the selected operating point.

3.5.5. Dependence of the reaction capacity from the temperature

Characteristics of semiconductors are known to be temperature dependent. Since the switching losses are heavily influenced by the capacitance Crss, compares 74 _{Feedback capacitance characteristics} determined at T _j = 25 ° C and T _j = 125 ° C from turn-on operations (V _DClink = _30V , R _G = _180Ω and I _L = _150A ). A correction of the measuring voltage with respect to the voltage drops across the parasitic elements was not initially made. The representation suggests a relatively strong dependence of the capacity on the junction temperature. However, since more concrete statements should only be made if the influence of the parasitic elements is taken into account 75 and 76 the large signal feedback capacitance characteristics, which were determined from on and off operations, taking into account the necessary voltage modifications. The parasitic elements have the same values as in Section 3.5.2. - Dependence of the reaction capacity on the switching speed - been used.

• • Die Rückwirkungskapazitätskennlinie ist beim Ein- und beim Ausschalten abhängig von der Junktiontemperatur T_j. So liegt die Rückwirkungskapazitätskennlinie von höheren Temperaturen beim Ein- und Ausschalten über der entsprechenden Kennlinie bei niedrigeren Temperaturen. Die Schaltverluste des MOSFET steigen demnach mit der Temperatur.
• • Der Abstand der Kennlinien ist nicht konstant. So sind die Abweichungen der Kennlinien für negative und kleine positive Drain-Gate-Spannungen am stärksten. Bei höheren Drain-Gate-Spannungen nähern sich die Kapazitätskennlinien einander an.
• • Die charakteristische Form der Kennlinie wird durch die Temperatur jedoch nicht verändert.
• • Die Abbildung 76 bestätigt auch, dass die Stromkommutierungsgeschwindigkeit und die Millerspannung beim Ausschalten durch die Temperatur beeinflusst werden, da sich die „Drain-Gate-Überspannungsspitzen" für die beiden Kurven um einige Volt unterscheiden.

The following summary can be found in the pictures 75 and 76 to be pulled:

• • The reaction capacity characteristic curve depends on the junction temperature T _j when switching on and off. Thus, the reaction capacity characteristic curve of higher temperatures during switching on and off is above the corresponding characteristic curve at lower temperatures. The switching losses of the MOSFET accordingly increase with the temperature.
• • The distance of the characteristic curves is not constant. The deviations of the characteristic curves are the strongest for negative and small positive drain-gate voltages. At higher drain-gate voltages, the capacitance characteristics approximate each other.
• • The characteristic shape of the characteristic is not changed by the temperature.
• • The illustration 76 also confirms that the current commutation rate and miller voltage are affected by the temperature when turned off, as the "drain-gate overvoltage tips "for the two curves differ by a few volts.

The pictures 77 ( _Tj = 25 ° C) and 78 (T _j = 125 ° C) show the time courses to the two large signal feedback capacity characteristics. The pictures 79 ( _Tj = 25 ° C) and 80 (T _j = 125 ° C) present, for documentation and information reasons, the time characteristics of the switch-on characteristics. A closer look at the four figures shows that the Miller plateau is formed at lower junction-to-source voltages both at turn-on and turn-off at higher junction temperatures. The width of the overvoltage peak in the Ausschaltverläufen also illustrates that the current commutation is completed faster at low temperatures.

Summarizing the findings in Guidelines for Measuring Reaction Capacitance, it should be noted that the characteristic should be determined from dynamic temperature measurements typical of switch application circuitry. Despite the differences that occur, however, it must be noted that the deviations of the characteristic curves for a wide temperature spectrum are relatively small. The extent to which they play a role from the point of view of losses as well as current and voltage transients should be checked simulatively in further investigations if necessary. The dependence of the large signal reaction capacity on the temperature implies that the capacitance Crss _{diff also} depends on the temperature. Since the switch model used does not take temperature changes into account, the determination of differential capacitances for different temperatures is dispensed with. All parameters of the model should be determined at the temperature to be subsequently simulated. The determination of the differential capacitance may be carried out according to the methods described in Section 3.5.2.2. - Different reaction capacity Crss _diff (R _G ) - methods presented.

3.5.6. Dependence of the reaction capacity from the load current

• • Die Großsignalrückwirkungskapazitätskennlinie ist sowohl beim Ein- als auch beim Ausschalten relativ unabhängig von der Lastromstärke I_L.

How and where the output characteristic field is traversed during switching depends on the load current I _L. Since it can therefore be assumed that the reaction capacitance characteristic curves of different load current intensities are absolute, the behavior of the characteristic curves as a function of the load current is examined in this section. It is assumed that slow switching curves with a gate resistance R _G = 180 Ω, because then the evaluation aggravating vibrations between the parasitic elements are largely damped. 81 compares three large signal feedback capacitance curves, which were determined from switch-on operations of different load currents. A correction of the measuring voltage with respect to the voltage drops across the parasitic elements has not been made. The representation suggests a non-negligible dependence of the capacity on the current. However, since concrete statements can only be made if the influence of the parasitic elements is taken into account 82 and 83 three Großsignalrückwirkungskapazitätskennlinien is that were determined from on and off operations of different load currents, taking into account the necessary voltage modifications. The same values for the parasitic elements as in Section 3.5.2. - Dependence of the reaction capacity on the switching speed - used. The following summary is shown in the figures 82 and 83 :

• • The large signal feedback capacity characteristic is relatively independent of the load current I _L both when switching on and off.

To the switch-on characteristics:

• • During power up the characteristic is traversed from right to left.
• • The corrected switch-on characteristics, in contrast to the non-corrected characteristic curves, show no tendency to reduce the capacitance values at lower load currents. Presumably, the deviations between the characteristics are due to statistical fluctuations or to numerical problems in the vicinity of V _DG = 0 V. Further investigations are always advisable in order to be able to make more precise statements.
• • At higher drain-gate voltages, however, it can be assumed that the voltage at which the characteristic curve increases depends on the load current. For example, the Crss _{LS_150A} characteristic increases at a lower drain-gate voltage than the Crss _{LA_10A} characteristic. This "break point" in the characteristic curves indicates the end of the current commutation and thus also a strong change in the rise of the drain-gate voltage, so that the rise of the drain-gate voltage during the current commutation is much lower than during the voltage commutation (cf. pictures 84 and 85 ). As described in section 3.5.3. - Parallelism between the feedback capacitance and the MOS capacitance - explained behavior of the MOS characteristic with high and low frequency measurements in the inversion range, explains also so the observed increase in the characteristic curve in this Point. However, if one evaluates the investigated current intensity range, it is questionable whether a deviation of the characteristic curves by 0.5 nF is negligible given the measuring accuracy.

To the switch-off characteristics:

• • During turn-off The characteristic is traversed from left to right.
• • The three characteristics are for wide ranges almost identical.
• • For negative drain-gate voltages, one is Tendency to reduce the capacitance values at higher currents to recognize. However, in this area can be a Approximation of the characteristics with reduction of the parasitic Determine drain resistance, without changing the distance of the characteristics changed in the other areas. Without continuing Investigations are so hard to estimate, whether here really there is a dependency or the parasitic Elements were not estimated accurately enough or merely Statistical deviations are observed.
• • This argument does not apply to high drain-gate voltages. Even when switching off different drain current gradients can be detected here at different load currents, which influence the characteristics accordingly. However, in terms of time compared to the switch-on shows an opposite effect. The drain-gate voltage transients remain at high currents due to the larger overvoltages during Stromkommutierung longer enough to delay an increase in the capacitance characteristic (see. 86 and 87 ).

• 1. Aus verlusttechnischer Sicht spielen die Ausschaltvorgänge eine größere Rolle. Da sich die Kennlinien beim Ein- und Ausschalten unterscheiden, sollten sie aus einem Ausschaltvorgang bestimmt werden.
• 2. Abhängigkeiten von der Laststromstärke ergeben sich vor allem im Bereich höherer Drain-Gate-Spannungen. Da die Spannungs- und Stromkommutierung beim Ausschalten im Wesentlichen mit Erreichen der Überspannungsspitze abgeschlossen ist, sollte die Kennlinie in diesem Bereich möglichst genau für den Nennstrom unter Berücksichtigung der parasitären Elemente bestimmt werden, da bei kleineren Strömen geringere Überspannungen erreicht werden.
• 3. Sind keine Information zu den parasitären Elementen vorhanden bzw. ableitbar, so empfiehlt sich die Ermittlung bei kleinen Stromstärken, da der Einfluss der im Leistungskreis liegenden parasitären Elemente geringer ist. Möglicherweise ist dann jedoch eine Abschätzung der Kennlinie bis zu einer maximal möglichen Überspannung notwendig.
• 4. Mit diesen Vereinfachungen genügt die Ermittlung der Kennlinie aus der Messing eines Betriebszustandes.

If the new findings are summarized in guidelines for the measurement of the reaction capacity, it can be stated:

• 1. From a loss point of view, the switch-off processes play a greater role. Since the characteristics differ when switching on and off, they should be determined from a switch-off process.
• 2. Dependencies on the load current intensity are especially in the range of higher drain-gate voltages. Since the voltage and current commutation when switching off is essentially completed when the overvoltage peak is reached, the characteristic in this range should be determined as accurately as possible for the rated current, taking into account the parasitic elements, since smaller overvoltages are achieved with smaller currents.
• 3. If no information on the parasitic elements is present or derivable, then the determination is recommended at low currents, since the influence of parasitic elements in the power circuit is lower. However, it may then be necessary to estimate the characteristic curve up to a maximum possible overvoltage.
• 4. With these simplifications, the determination of the characteristic curve from the brass of an operating state is sufficient.

The summary makes it clear that in the areas in which the determination of the large signal capacity is recommended, the differential capacitance is also almost constant. Therefore, a study of the differential capacitance is dispensed with, since it corresponds to the retroactivity, which at R _G = 180 Ω in Section 3.5.2.2. - Differential reaction capacity Crss _diff (R _G ) - was determined.

3.5.7. Dependence of the Rickwirkungskapazität from the DC link voltage

Since the drain-gate voltage in the switched-on state approximately corresponds to the _drive voltage V _{Dr (on)} and in the switched-off state of the intermediate _{circuit voltage} V _DClink , it can be assumed that the feedback _{capacitance characteristics} are influenced by the intermediate circuit voltage. Therefore, in this section, the behavior of the characteristic curves is examined in dependence on the voltage V _DClink , making numerous statements similar to those in the previous section. It should be assumed here again of slow switching curves with a gate resistor R _G = 180 Ω, because here the evaluation aggravating vibrations are largely damped. 88 compares three large-signal _{feedback capacitance} curves, which were determined from switch-on operations of different intermediate _{circuit voltages} V _DClink . An adjustment of the measuring voltage with respect to the voltage drops across the parasitic elements was not made. The illustration shows that the characteristic curves are almost identical in many areas. At positive drain-gate voltages, however, a significant dependence on the DC link voltage can be seen.

It can be assumed that the consideration of the parasitic elements has no significant influence on the distances between the characteristic curves, since the voltage drops across the internal inductances and resistances depend on the drain and gate current intensity and the speed of the current commutation. Whether the voltage VDClink might not influence the range of voltage commutation and there with on the characteristics, should nevertheless be examined. Therefore ask 89 and 90 three Großsignalrückwirkungskapazitätskennlinien is that were determined from on and off operations of various DC link voltages, taking into account the necessary voltage modifications. The same values for the parasitic elements as in Section 3.5.2. - Dependence of the reaction capacity on the switching speed - used.

• • Der Definitionsbereich der Kennlinie ist (natürlich) abhängig von der Zwischenkreisspannung. So hat die Großsignalrückwirkungskapazitätskennlinie neben unabhängigen Kennlinienabschnitten sowohl beim Ein- als auch beim Ausschalten Abschnitte, die durch die Zwischenkreisspannung VDClink – aufgrund des typischen nieder- und hochfrequenten Verhaltens von MOS-Kapazitäten – relativ stark beeinflusst werden.

The following summary is shown in the figures 89 and 90 :

• • The definition range of the characteristic curve is (of course) dependent on the DC link voltage. Thus, in addition to independent characteristic sections, the large-signal feedback capacitance characteristic has relatively strong influences both on and off switching due to the DC link voltage VDClink due to the typical low-frequency and high-frequency behavior of MOS capacitors.

To the switch-on characteristics:

• • During power up the characteristic is traversed from right to left.
• • The corrected switch-on characteristics are also for negative and small positive drain-gate voltages almost identical and thus independent of the DC link voltage.
• • At higher drain-gate voltages, the voltage at which the characteristic curve increases depends on the DC link voltage. For example, the characteristic Crss LS_20V _increases at a lower drain-gate voltage than the characteristic Crss _{LS_42V} . The characteristic curves clearly show two break points KP1 and KP2 (cf. 89 ). The first break point in the characteristic indicates the beginning of the current commutation. At this point, the increase in the drain-gate voltage changes over time. The second "break point" in the curves indicates the end of the current commutation, and thus also a large change in the drain-gate voltage increase, and over time, the drain-gate voltage increase during current commutation is much lower as during the voltage commutation (see. 91 and 92 ). As described in section 3.5.3. - Parallelism between the feedback capacitance and the MOS capacitance - explained behavior of the MOS characteristic in high- and low-frequency measurements in the inversion range, which also explains the observed increase in the characteristic curve at these points.

To because switch-off characteristics:

• • During turn-off the characteristic is traversed from right to left.
• • Compared to the switch-on characteristics, the characteristic curves for a larger drain-gate voltage range are almost identical. They are virtually in line with the drain-gate overvoltage _peak V _DGmax .
• • For high drain-gate voltages, the characteristic of the different characteristic curves differs from V _DGmax . Depending on the increase in the drain-gate voltage, the characteristic curve increases again. The drain-gate voltage rise logically remains high enough at higher DC link voltages up to high drain-gate voltages to delay an increase in the capacitance characteristic (cf. 93 and 94 ).

Holds the findings in guidelines for measuring the reaction capacity together, so can analogously to the considerations to Determine load current dependency:

• 1. From a loss perspective play the Turn-off a greater role. Since the characteristics differ when switching on and off, should they be determined from a shutdown process.
• 2. Dependencies of the DC link voltage result in the range of higher drain-gate voltages. Since the voltage and Stromkommutierung when you turn off substantially with reaching the overvoltage peak is complete, the characteristic should be in this area as accurately as possible for high DC link voltages taking into account the parasitic elements be determined. Thus, the characteristic can also be large Gate resistors are determined without the drain-gate voltage already due to the switching speed at too low voltage values increases (see Section 3.5.2 - Dependency the reaction capacity of the switching speed).
• 3. With these simplifications, it is sufficient to include the characteristic curve to determine a DC link voltage.

The summary of the dependence of the characteristic on the intermediate circuit voltage makes it clear that in the areas in which the determination of the large signal capacity is recommended, the differential capacitance is almost constant. Therefore, a study of the differential capacitance is omitted since it corresponds to the retroactivity capacitance, which for R _G = 180 Ω in subsection 3.5.2.2. - Differential reaction capacity Crss _diff (R _G ) - was determined.

3.6. Input capacity Ciss

3.6.1. Determination of input capacity

Also At this point the work must be noted that the present work was created by iterative processes and some findings only after several evaluation and examination cycles were won. Because of the facts that the parameter extraction only exemplarily carried out for a switch and verification for other low voltage MOSFETs is still outstanding, it is not for efficiency and time reasons meaningful, all considerations repeatedly after the to carry out the latest state of knowledge. the goal is it, the knowledge acquired and targeted rules for investigation to summarize the capacity curves to make a check the results using the methods set out on more To enable components.

The determination of the input capacitance can be carried out according to the determination of the feedback capacity as a differential and as a large signal capacity. In the first investigations, however, both the feedback capacitance and the input capacitance were determined only as large signal capacitance without consideration of the parasitic elements for a variety of operating points. The strong influence of the switching characteristics due to the high voltage-dependent feedback capacity and the fact that the simulative conversion of the differential capacitance is relatively simple due to the corresponding current equation (3.2) has necessitated a detailed consideration of the differential feedback capacity taking into account the new findings. In the input capacity is waived. For the switch-off conditions V _DClink = 30 V, I _L = 150 A, R _G = 180 Ω and T _J = 25 ° C, the originally determined large-signal characteristic is compared with the large-signal characteristic taking into account the influence of the parasitic elements and the differential capacitance characteristic certainly. In section 3.6.2. - Working point dependence of the input capacitance - then the operating point dependence is shown with the originally determined characteristics, from which then based on the findings from this section can derive statements, but this is largely dispensed with. In the case of continuing work, the more precise analyzes should then be carried out on different components as far as possible and a corresponding characteristic comparison for the various operating parameters should be carried out.

Since the influence of the parasitic elements is lower and existing vibrations are more attenuated, the analyzes mentioned for a slow turn-off with V _DClink = 30 V, I _L = 150 A, R _G = 180 Ω and T _j = 25 ° C realized. The determination of the large signal input capacitance takes place according to equation (3.9)

bestimmt werden. Dabei sollte i unter Beachtung der Messpunktdichte möglichst klein gewählt werden, um die Genauigkeit der numerischen Differentiation zu erhöhen. Aufgrund des Messrauschens ist es jedoch mitunter notwendig, i > 1 zu wählen, um numerische Probleme (beispielsweise die Division durch Null) zu vermeiden.The differential input capacitance can be approximated by equation (3.3)

be determined. In this case, i should be chosen as small as possible, taking into account the measuring point density, in order to increase the accuracy of the numerical differentiation. However, due to the measurement noise, it is sometimes necessary to select i> 1 to avoid numerical problems (for example, division by zero).

The equations show that, for the sake of simplification, it is assumed that the input capacitance depends only on the gate-source voltage. Between the gate and the source, the capacitive effect of the entire measuring circuit between the two switch electrodes during switching can then be determined by equations (3.36) and (3.37). To estimate the charge Q _i (t) in the input capacitance, as in the case of the retroactivity capacitance, the charge change between two measurement points was first estimated and the charge increments calculated according to equation (3.25). The total charge Q _{Gtot which has} flowed into the gate up to the time t _n results according to the summation equation (3.26). Under the condition that at time t _vi applies V GSmess (t vi ) = 0 V ↔ Q i (t vi ) = 0 C, (3.38) For example, the charge Q _i in the input capacitance at time t _n can be determined with Q i (t n ) = Q gtot (t n ) - Q gtot (t vi ). (3:39)

95 shows the determined large signal capacity characteristic of the turn-off I _L = 150 A, R _G = 180 Ω, V _{DC link} = 30 V and T _J = 25 ° C, which was determined from the evaluation of the measured data. When looking at the characteristic curve for the first time, it is noticeable that numerical problems occur near V _GS = 0 V, similar to the reaction capacitance. The characteristic jump in the input capacitance function occurs during the Millerplateaus or voltage commutation by the highly voltage-dependent drain-gate capacitance. To the left and to the right of this voltage jump, the capacity seems to be decreasing almost linearly.

However, the characteristic differs from the characteristic that would result directly on the chip. 21 represents the voltage definitions across the parasitic elements of the switch. The result is the chip voltage according to the mesh equation U GSchip = V GSmess - V RGint - V LG - V RS - V LS (3:40)

The pictures 96 . 97 . 98 . 99 and 100 show the influence of the parasitic elements on the capacitance characteristic Ciss (V _GSmess ), first individually and then considered together. The internal and the connection resistances as well as the internal and the connection inductances are assigned the same values as in the determination of the reaction capacitance. In the lower switch, the source inductance has the same value as the drain inductance (see subsection 4.2.2.2 - Determination of Inductances and Resistors).

96 indicates that there is a shift in the miller voltage across the chip when turned on and off due to the voltage drop across the internal gate resistor. When switched off, the voltage on the chip increases with respect to the measuring voltage. When switched on, it reduces accordingly depending on the switching speed or the gate resistor. For small gate resistors, this effect increases due to the voltage sharing between the internal gate resistor and the gate resistor.

The influence of the gate inductance is negligible in slow switching processes ( 97 ). For faster switching operations, the capacitance characteristic is changed when switching off in the vicinity of V _GS = V _{Dr (on)} and at power-up by V _GS = V _{Dr (off)} . When turning off, it is expected to reduce the input capacitance and increase the input capacitance at power up, since the chip voltage V _GSchip (see equation (3.40)) is used instead of V _GSmess in equation (3.36). The influence of the internal and terminal source _resistance R _S is significant ( 98 ). The voltage drop causes a reduced Miller voltage and larger capacitance values between the threshold voltage and the drive voltage due to the current flow through the switch as a function of the instantaneous current.

The source inductance influences the characteristic during current commutation ( 99 ). When switching off and when switching on, the capacitance values in this range of the capacitance function increase. Due to the influence of the switching speed by the gate resistor this effect is different for different gate resistances.

100 shows the capacitance characteristic taking into account all the parasitic elements for the turn-off I _L = 150 A, R _G = 180 Ω, VDClink = 30 V and T _J = 25 ° C. A direct evaluation of the corrected measurement data to determine the differential capacitance leads to no evaluable result, such as 101 shows.

For this reason, the results of the switch-off process I _L = 150 A, R _G = 180 Ω, V _DClink = 30 V and T _J = 25 ° C are used to document the results, which are obtained in subsection 3.5.2.2. - Differential reaction capacity Crss _diff (R _G ) - Variant 1 described used for determining the differential capacitance. To get an impression of how sensitive the characteristic curve reacts to the parasitic elements or to the measuring points used, the charge _curves Qi (V _GSmess ) and Qi (V _Gsechip ) are approximated and from this the characteristics Ciss _diff (V _GSmess ) and Ciss _diff ( V _GSchip ) and compared (cf. 102 (Determination of the first section of Ciss _diff from Qi (V _GSmess ) using TableCurve2D), 103 (Determination of the first section of ciss _diff from Qi (V _GSchip ) by means of TableCurve2D), 104 (Determination of the second section of Ciss _diff from Qi (V _GSmess ) using TableCurve2D) and 105 (Determination of the second section of Ciss _diff from Qi (V _GSchip ) using TableCurve2D)).

Under the simplifying assumption that the gate current does not flow into the input capacitance but into the reaction capacitance at the time of the voltage commutation, this region of the characteristic curve can be neglected. Therefore, the charge curve Qi (V _GS ) is fitted in two areas - before and after the Miller plateau - and the derivative is formed to calculate the differential capacitance. The results are in the pictures 102 to 105 shown. When considering the upper characteristic region, it is noticeable that the ciss _diff characteristic _{curves have} a qualitatively similar characteristic for the two voltages V _GSchip and V _GSmess . Significant differences, however, result for the lower characteristic range after exceeding the threshold voltage, since with the beginning of Stromkommutierung an increase in the charge curve Qi (V _GS ) is accompanied by the voltage drops across the parasitic elements in the power circuit. During the current commutation, the differential input capacitance of the chip is thus much lower than the capacitance that is obtained from the direct evaluation of the measured data. Further statements on input capacitance will be provided in the description of the model of the MOSFET in Section 3.8. - Model presentation of the switch capacities for the simulation - and in the simulative study of the capacitance characteristics at an operating point in Section 4.3. derived.

3.6.2. Bias dependence the input capacity

The figures explained below are used to document the operating point dependency of the large signal input capacitance Ciss _LS . Different operating conditions are compared, which can be supplemented as desired and do not claim to be complete. The evaluation of the characteristic curves is only possible to a limited extent, since the characteristic curves have been determined from the measured data. For more accurate statements, the data of the differential characteristics would have to be determined taking into account the parasitic elements and an offset correction of the gate current should be made.

• 1. Unter Berücksichtigung des internen Gatewiderstandes und des Anschlussgatewiderstandes vergrößert sich die Millerspannung beim Ausschalten, und sie verringert sich beim Einschalten gegenüber der aus Messdaten ermittelten Spannung aufgrund der Gatestromrichtung.
• 2. Beachtet man die interne Gateinduktivität und die Anschlussgateinduktivität, verringert sich die Großsignaleingangskapazität beim Ausschalten bei V_GS = V_Dr(on), und sie vergrößert sich beim Einschalten bei V_GS = V_Dr(off) gegenüber der ursprünglich ermittelten Kennlinie aufgrund des Vorzeichens des Gatestromanstiegs.
• 3. Die interne Sourceinduktivität und die Anschlusssourceinduktivität verursacht während der Stromkommutierung (zwischen Schwellen- und Millerspannung) aufgrund des Vorzeichens des Drainstromanstiegs dI_D/dt beim Ausschalten eine Verringerung der Kapazitätswerte und beim Einschalten eine Erhöhung der Kapazitätswerte gegenüber den Werten, die aus der Messspannung ermittelt wurden.
• 4. Der interne Sourcewiderstand und der Anschlusssourcewiderstand bewirken sowohl beim Ein- als auch beim Ausschalten eine Verringerung der Gate-Source-Spannung im Chip. Die tatsächlichen Großsignalkapazitätswerte liegen also für V_GS > V_GSth, über den Kapazitätswerten, die aus der Messspannung bestimmt wurden.

According to the findings of subchapter 3.6.1 - Determining the input capacitance - the following effects in the representations can be expected by considering the parasitic elements. The strength of the effects is strongly dependent on both the switching speed or the gate resistor and the resulting transients, as well as the load current. Sometimes they are negligible.

• 1. Taking into account the internal gate resistance and the terminal gate resistance, the Miller voltage increases at turn-off, and decreases at power-up compared to the measured-data voltage due to the gate current direction.
• 2. Considering the internal gate inductance and the terminal gate inductance, the large signal input capacitance at turn-off decreases at V _GS = V _{Dr (on)} , and increases at V _GS = V _{Dr (off)} with respect to the originally determined characteristic due to the sign when turned on of the gate increase.
• 3. The internal source inductance and the terminal source inductance cause a decrease in capacitance values during current commutation (between threshold and mill voltage) due to the sign of drain current rise dI _D / dt at power off and an increase in capacitance values at power-up compared to the values derived from the measurement voltage were.
• 4. The internal source resistance and the terminal source resistance cause a reduction of the gate-source voltage in the chip both on and off. The actual large signal capacity _values are thus for V _GS > V _GSth , over the capacitance _values , which were determined from the _measurement voltage.

• • Die ermittelte Großsignalkennlinie Ciss_LS(V_GSmess) des Ausschaltverlaufs liegt über der Kennlinie des Einschaltverlaufs. Auch die stationären Endpunkte der Großsignaleingangskapazitäten Ciss_LS(V_GSmess) unterscheiden sich. In Abschnitt 3.5.4. – Vergleich der Rückwirkungskapazität beim Ein- und Ausschalten – wurde dokumentiert, dass diese Abweichungen vermutlich auf Messfehler zurückzuführen sind. Eine entsprechende Untersuchung, die neben dem Offset des Gatestromes auch parasitäre Elemente berücksichtigt, wurde nachträglich für eine Betriebsbedingung durchgeführt und bestätigte diese Annahme auch für die Großsignaleingangskapazität. Sie ist im Unterkapitel 4.3. – Untersuchung der Kennlinie in einem Arbeitspunkt – aufgeführt.
• • Anders als beim Ausschalten, entstehen beim Einschalten Schwingungen durch die sprunghafte Änderung der Gate-Source-Spannung zum Zeitpunkt des Rückstromabrisses bzw. des Übergangs von der Strom- zur Spannungskommutierung. Diese sind bei einem Gatevorwiderstand von R_G = 180 Ω schon relativ stark gedämpft. Es ist zu vermuten, dass die Ciss_LS-Kennlinie bei kleinen, applikationstypischen Gatewiderständen aufgrund dieser Schwingungen nicht mehr auswertbar und das klassische Millerplateau durch die überlagerten Schwingungen nicht ersichtlich ist. Die Kennlinienauswertung sollte deshalb an möglichst langsamen Schaltvorgängen oder an den Ausschaltverläufen erfolgen.
• • Die Abbildung zeigt, dass die Millerspannung bei den Ausschaltverläufen kleiner ist als bei den Einschaltverläufen. Im vorherigen Unterkapitel wurde jedoch die Wirkung des internen Gatewiderstandes erläutert. Demnach verschiebt sich die Millerspannung beim Ausschalten nach links und beim Einschalten nach rechts. Es ist also zu erwarten, dass sich die Millerspannungen beim Ein- und Ausschalten einander annähern.
• • Eine Abhängigkeit der differentiellen Rückwirkungskapazität vom Schaltvorgang ist auch bei richtiger Kennlinienauswertung (Berücksichtigung des Gatestromoffsets und der parasitären Elemente) zu erwarten.

First, let us now discuss the resulting differences in the large signal input capacitance characteristic as a function of the switching operation. From the presentation 106 (Comparison of the input capacitance Ciss _LS when switching on and off at different DC link voltages with I _L = 150 A, R _G = 180 Ohm and Tj = 25 ° C) leads to the following conclusions:

• • The determined large signal characteristic Ciss _LS (V _GSmess ) of the switch-off characteristic is above the characteristic curve of the switch-on characteristic. The stationary endpoints of the large signal input capacitances Ciss _LS (V _GSmess ) also differ. In section 3.5.4. - Comparison of the reaction capacity on switching on and off - has been documented that these deviations are probably due to measurement errors. A corresponding investigation, which also considers parasitic elements in addition to the offset of the gate current, was subsequently carried out for an operating condition and confirmed this assumption also for the large signal input capacitance. It is in subchapter 4.3. - Examination of the characteristic in one operating point - listed.
• • Unlike when switched off, oscillations occur when switching on due to the sudden change in the gate-source voltage at the time of the reverse current cutoff or the transition from the current to the voltage commutation. These are already at a gate resistor of R _G = 180 Ω heavily dampened. It can be assumed that the Ciss _{LS characteristic} curve can no longer be evaluated for small, application-typical gate resistances due to these vibrations, and the classic Miller plateau due to the superimposed oscillations is not apparent. The characteristic evaluation should therefore be carried out on the slowest possible switching operations or on the Ausschaltverläufen.
• • The figure shows that the Miller voltage is lower in the case of the switch-off curves than in the switch-on curves. In the previous subchapter, however, the effect of the internal gate resistance was explained. Accordingly, the Miller voltage shifts to the left when switched off and to the right when switched on. It can therefore be expected that the mill voltage will approach each other when switching on and off.
• • A dependence of the differential reaction capacitance on the switching process is to be expected even with correct characteristic evaluation (consideration of the gate off-set and the parasitic elements).

• • Die Bereiche der Kennlinien vor und nach der Millerspannung sind bei sonst gleichen Bedingungen für verschiedene relativ große Gatevorwiderstände nahezu identisch.
• • Die gemessene Millerspannung ist für alle dargestellten Betriebsbedingungen gleich.
• • Mit der Schaltgeschwindigkeit nimmt der maximale Rückwärtsstrom in der Freilaufdiode zu (vgl. Abschnitt 4.4.3.2. – Einstellung der Diodenzeitkonstanten). Dieser Rückwärtsstrom fließt im Brückenzweig und addiert sich zum Drainstrom des MOSFETs. Dadurch kommt der MOSFET bei der Stromkommutierung während des Durchlaufens des Ausgangskennlinienfeldes beim Einschalten auf höhere Gatespannungen als bei geringeren Schaltgeschwindigkeiten (vgl. auch Abschnitt 2.3.2. – dV_DS/dt – Rückkopplung durch die Gatekapazität).
• • Im Rückstromabriss kommt es zu einer sprunghaften Veränderung der Gate-Source-Spannung. Die dadurch entstehenden Schwingungen werden durch größere Gatewiderstände stärker gedämpft.
• • Eine Abhängigkeit der differentiellen Eingangskapazität ist für den unteren und oberen Bereich der Kennlinie nicht zu erwarten.

Out 107 (Dependence of the input capacitance Ciss _LS on the switching speed at different DC link voltages with I _L = 150 A and T _j = 25 ° C at switch-on), the following statements regarding the dependence on the switching speed can be derived:

• • The ranges of the characteristic curves before and after the Miller voltage are almost identical under different conditions for different relatively large gate resistors.
• • The measured Miller voltage is the same for all operating conditions shown.
• • With the switching speed, the maximum reverse current in the freewheeling diode increases (see Section 4.4.3.2 - Setting the diode time constants). This reverse current flows in the bridge branch and adds to the drain current of the MOSFET. Thus, during current commutation, during current commutation, the MOSFET will experience higher gate voltages at power-up than at lower switching speeds (see also Section 2.3.2 - dV _DS / dt - Gate Capacitance Feedback).
• • In the reverse current break, there is a sudden change in the gate-source voltage. The resulting oscillations are more strongly damped by larger gate resistances.
• • A dependence of the differential input capacitance is not to be expected for the lower and upper range of the characteristic.

• • Die Millerspannung verringert sich bei höheren Temperaturen.
• • Der Kennlinienbereich vor der Millerspannung ist für alle dargestellten Schaltbedingungen nahezu identisch.
• • Nach der Millerspannung liegen die Kapazitätswerte bei höheren Temperaturen geringfügig über denen bei niedrigeren Temperaturen, wobei dieser Effekt bei der kleinsten Zwischenkreisspannung am stärksten ausgeprägt ist. Es muss jedoch anhand weiterer Messungen überprüft werden, ob es sich hierbei nicht um statistische Abweichungen handelt.
• • Eine starke Abhängigkeit der differentiellen Kapazität von der Temperatur in den relevanten Bereichen ist nicht zu erwarten.

108 (Dependence of the input capacitance Ciss _LS on the temperature at different DC link voltages with I _L = 150 A and R _G = 180 Ohms) represents the temperature dependence of the input capacitance. The following effects can be seen:

• Miller voltage decreases at higher temperatures.
• • The characteristic range before the Miller voltage is almost identical for all switching conditions shown.
• • After the Miller voltage, the capacitance values at higher temperatures are slightly higher than those at lower temperatures, this effect being most pronounced at the lowest DC link voltage. However, it must be checked on the basis of further measurements whether these are not statistical deviations.
• • A strong dependence of the differential capacity on the temperature in the relevant areas is not expected.

• • Die Millerspannung verringert sich bei kleineren Stromstärken, da das Ausgangskennlinienfeld während der Spannungskommutierung bei niedrigeren Gatespannungen durchlaufen wird.
• • Die Kapazitätswerte steigen während der Spannungskommutierung bei kleineren Stromstärken auf wesentlich höhere Werte an als bei größeren.
• • Inwiefern dies einen Einfluss auf diesen Bereich der differentiellen Eingangskapazität hat, muss in weiterführenden Analysen untersucht werden.

109 (Dependence of the input capacitance Ciss _LS on the load current intensity at different DC link voltages R _G = 180 ohms and T _j = 25 ° C) illustrates the dependence of the input capacitance on the load current intensity. The following statements can be derived from it:

• • Miller voltage decreases at lower currents because the output characteristics field is swept at lower gate voltages during voltage commutation.
• • The capacitance values increase to much higher values during the voltage commutation for lower currents than for larger ones.
• • To what extent this has an influence on this range of differential input capacitance needs to be investigated in further analysis.

• • Die Abbildungen lassen die Vermutung zu, dass bei niedrigen Temperaturen eine Abhängigkeit der Millerspannung von der Zwischenkreisspannung besteht. Es ist tendenziell eine Verringerung der Millerspannung bei größeren Zwischenkreisspannungen feststellbar. Allerdings muss diese These durch weitere Messungen bestätigt werden, da es sich durchaus auch um statische Schwankungen handeln könnte.
• • Im oberen Kennlinienbereich besteht eine offensichtliche Abhängigkeit der Großsignaleingangskapazität von der Zwischenkreisspannung: Je größer die zu kommutierende Spannung ist, desto höher sind die Großsignalkapazitätswerte rechts von der Millerspannung.
• • Wie stark der Einfluss dieser Abhängigkeit auf den entsprechenden Bereich der differentiellen Eingangskapazität ist, sollte in weiterführenden Analysen untersucht werden.

The pictures 106 . 107 . 108 and 109 All dependencies examined up to now also represent different DC link voltages. In summary:

• • The figures suggest that at low temperatures there is a dependence of the Miller voltage on the DC link voltage. There is a tendency to detect a reduction in the Miller voltage for larger DC link voltages. However, this thesis must be confirmed by further measurements, as it could well be static fluctuations.
• • In the upper characteristic range, there is an obvious dependence of the large signal input capacitance on the intermediate circuit voltage: the larger the voltage to be commutated, the higher are the large signal capacitance values to the right of the Miller voltage.
• • How strong the influence of this dependence is on the corresponding range of the differential input capacitance should be investigated in further analyzes.

Holds the statements derived from the illustrations explained together, it should be noted that one not insignificant Dependence of the input capacity curve on the selected operating conditions. The question the causes of the dependence on the intermediate circuit voltage and what is the relationship between the feedback capacity and the input capacity persists, stays first still open. More profound investigations - in particular like the determined capacities in a switch model conception can be united with each other - are for However, continuing work is indispensable.

3.6.3. Parallels between input capacity and MOS capacity

110 illustrates the structural design of a trench gate MOSFET cell. The input capacitances Ciss _diff and Ciss _LS , respectively, are determined during switching between the source and gate terminals using equations (3.36), (3.37), (3.38), and (3.39) certainly. There is also a type of MOS layer sequence between these terminals, which, however, does not correspond to the MOS capacitance structure between gate and drain due to the short circuit between source (n ⁺ ) and bulk (p ⁺ ) and the spatial structure of the trench gate MOSFET. Rather, it seems to be a parallel connection of a MOS structure with n-type semiconductor C _{GS_n +} and a MOS structure with p-type semiconductor C _{GS_p +} (cf. 110 ).

However, the different semiconductors are at a positive gate to source voltage, as explained in Section 3.5.3. - parallels between reaction capacity and MOS capacitance -, in different states (cf. 111 (CV curves of a MOS structure with n-type semiconductor) and 112 (CV curves of a p-type MOS structure)).

With the help of the assumed parallel connection of the two MOS structures, the typical course of the Ciss _{LS characteristic} curve can be explained, since the substitute capacity results from the addition of the two individual capacitances. With positive gate-source voltages, the MOS capacitance with the n-type semiconductor is in the enrichment and thus almost constant. For the MOS capacitance with the p-type semiconductor results in increasing gate voltage according to the states depletion and inversion. In this case, from the threshold voltage or inversion voltage, a dependence of the curve on the switching speed or of the frequency. Divide now the input capacity curve in the following three areas (see. 113 and 114 ), the resulting curve can be explained or understood, taking into account the behavior of the individual MOS capacitors.

1. Gate-source voltage between V _GS = 0 V and V _GS = V _{GS_millern}

In This area falls the determined large signal input capacitance characteristic Slight decrease with increasing gate voltage. This is possible reasoning that it is in the MOS structure with the p-type semiconductor with increasing gate voltage first to a depletion and then an inversion of majority carriers occurs. As the capacity of the MOS structure with the n-type semiconductor is almost constant in the enrichment state, results in the Sum a slightly falling curve. (The gate-source voltage rise is the largest in this area during switching, so that it can be assumed that the characteristic curve near the high-frequency characteristic.)

2. Gate-source voltage V _GS = V _{GS_millern}

During Millennium the capacity increases strongly. This can be explained as follows: Since the gate-source voltage does not change in this range, the capacitance values of the MOS structure with the p-type semiconductor approach the low-frequency characteristic. Since the capacitance of the MOS structure with the n-type semiconductor is constant in the enrichment state, greatly increasing capacitance values result in this region. This argument also provides an explanation for the dependency on the intermediate circuit voltage in this range, as documented in the previous section: the longer the voltage commutation or the Miller lasts, the closer the capacitance values of the low-frequency characteristic to each other. To clarify this issue, the illustrations 113 and 114 two switching curves with different DC link voltages opposite each other. It becomes clear that at higher DC link voltages the Voltage commutation takes longer and thus the gate voltage remains constant for a longer time.

3. Gate-source voltage between V _GS = V _{GS_millern} and V _GS = V _{Dr (on)}

In This area falls the determined large signal input capacitance characteristic slightly decreasing with increasing gate voltage. This reduction is likely due to the change in the gate-source voltage, that of a capacitance characteristic below the low-frequency characteristic equivalent.

The large signal input capacitance characteristic is certainly also dependent on the size of the contact surfaces of p ⁺ and n ⁺ with the oxide layer, furthermore on how the charge carriers are distributed as counter charge to the gate charge on the individual semiconductor layers, and finally on the mean path length between the two Connections gate and source through the p- and n-type semiconductor. However, these influences can not be investigated in this work. Completely disregarded in the argumentation is also the influence of the motion of charge carriers in these two semiconductor layers.

3.7. Output capacity Coss

Under the output capacity, this work understands the capacitive Effect between the drain and the source. Compared to the feedback and input capacitance their purpose more complicated. So when turning off the electricity, which flows past the channel from the drain to the source, be quantified. When switching it on it would be necessary to determine the current in addition to the drain current flowing through the channel. This is even more complicated as the current detection when switching off, because when switching on, due the reverse recovery behavior of the freewheeling diode, further current components added. The measurement of the current is with the given measurement setup not possible when switching on or off. Indeed For example, it is for hard-switching applications Of importance, the burdening or relieving effect on the channel current quantify when switching on or off.

component the output capacitance is in any case the drain-source capacitance. Parallel to this is a discharge when switching off or a load when turning on the drain-gate capacitance and the gate drive circuit conceivable. This is similar to the Definition of the small signal short-circuit output capacitance (see Section 3.3 - Datasheet details on switch capacities - Equation (3.16)). When studying the relevant literature falls on that the drain-source capacity in the modeling MOSFETs are often disregarded with the reasoning that they have no significant influence the switching curves have [3]. That would be correct if the drain-source capacity CDs much smaller would be called the drain-gate capacitance or one of theirs Effect also with the drain-gate capacitance model or could explain. Under this assumption would the determination of the output capacity is unnecessary. As appropriate investigations confirm this Assumption, however, still pending, in this chapter in principle as the initial capacity with given Estimated means of turn-off can, without this estimate concrete example of some Perform switching curves. That stays behind Working reserved, if there is a need - for example for accurate determination of interelectrode capacitances - This characteristic should give the enormous amount of work would justify. It then remains to be considered to what extent an evaluation is possible at all or whether the resulting capacity values are not are so small that they are lost in measurement noise.

The prerequisite for the determination of the output capacitance is an output characteristic curve field measured as accurately as possible with as small steps as possible in the gate voltage. From this a set of transfer characteristics I _Dn = f (V _GS , V _DS = V _{DSn) can be} obtained, wherein the drain-source voltages of the transfer characteristics should have reasonable distances, for example 0.5 V. The transfer characteristics for different drain Of course, source voltages can also be measured directly. Transfer characteristics are static characteristics. This means that although the voltage drops across the internal inductances and connection inductances are zero, but not over the internal resistances and connection resistances. Therefore, the voltages V _DSmess and V _GSmeas originated from dynamic measurements _need only be corrected for the inductances. Thus, a data triplet results from the drain current I _D (t) and the corrected _measurement voltages V _{DSmess '} (t) and V _GSmess' (t) for each instant of the switching process. If one now takes the times t _i from the measurement series in which V _DSmess' corresponds to the voltages V _{DS of} the transfer characteristics, one can compare the measured drain current I _D (t) with the channel _current I _Dchannel . The current through the output _capacitance I _{D_Coss} (t) then results in I DCoss (t) = I dmeas (t) - I D- CHANNEL (V GSmess' (T); V DSmess' (T)). (3:41)

By linear approximation between the thus determined current points, the point density can be increased again to the measured value density, and the output capacitance results according to the equations (3.3) and (3.9)

To estimate the charge Q _o (t) in the output capacitance, the charge change between two measurement points must first be estimated. The charge increments are calculated as follows:

The charge Q _o which has flowed into the output capacitance up to the instant t _n is then obtained by numerical integration from the summation function

As with the feedback and input capacitance, one would now have to assume that at time t _v V DS (t v ) = 0 V ↔ Q O (t v ) = 0 C, (3.46) the charge Q _o in the output capacitance at time t _n with Q O (t n ) = Q otot (t n ) - Q otot (t v ) (3.47) can determine. However, this is not the case because the time t _v does not exist in the dynamic switching process, since there is no ideal switch: When switched on, the drain-source voltage results from the voltage drop across the on-resistance: V DS (on) = I D · r ds (on) (3:48)

In order to be able to determine the output capacitance nevertheless, a simplifying assumption must be made: For example, in the steady state, one could assume that the output capacitance has been completely discharged by the on-resistance r _{ds (on)} . However, this is countered by the statement that the drain-gate capacitance is a component of the output capacitance, because above it, in the switched-on state, the driver voltage V _{Dr (on)} decreases, minus the forward voltage V _{DS (on)} . The charge in it must therefore be different from zero. Therefore, considering the current state of knowledge, only the differential output capacitance can be determined according to equation (3.42), since the absolute charge value Q _o does not play a role for them.

Finally to this problem should be pointed out again that only a current flows through a capacitor, when the voltage changes over her. This is actually only during the voltage commutation of the case. However, the commutation inductances cause during the current commutation by the voltage drops across itself a change in the chip voltage. That means, the current must be through the output capacitance for the entire switching process according to equation (3.42) can be determined.

3.8. Model presentation of the switch capacities for the simulation

In subchapters 3.5., 3.6. and 3.7. The understanding of the present work was explained by a feedback, input-output capacitance of a switch. These capacity definitions make clear that the said switch capacitors neither the Interelektrodenkapazitäten C _DG , C _GS and C _DS (see. 115 ) nor the replacement capacities of simple interelectrode capacitance parallel circuits of the equivalent equivalent circuit diagrams to the data sheet measurements (see Section 3.3. - Data Sheet Information on Switch Capacities).

Rather, these defined capacities appear to contain all the capabilities of the switch under consideration and the switch environment , Therefore, it is not possible to integrate both the feedback and the input capacitance characteristic in the switch model. The capacitances, in particular the drain-gate and the gate-source capacitance, would then be considered twice. In this subchapter, a simple model is presented, how the determined characteristic curves can be integrated into state-controlled switch models. The simulation results of the model are then presented in Chapter 4 - Verification of Capacitance Characteristics by Simulation.

In subchapter 3.7. - Output capacitance Coss - has already been suggested that the effect of the output capacitance can also be simulated via the feedback capacity. Therefore, the determination of a corresponding characteristic was omitted. Also the switch model ET3g does not model the output capacitance. However, both the gate capacitance C _GS and the miller capacitance C _{DG should} be parameterized in the simulation so that the simulation of the switching operations is as accurate as possible. The two Interelektrodenkapazitäten are not constant, but change depending on the voltages applied to the capacitors, since the capacitances are partially formed by voltage-dependent depletion zones. The largest change in capacitance during switching occurs in C _DG , since the voltage change across it is greater than over C _GS . For estimating switching characteristics, therefore, the gate capacitance is often assumed to be constant, whereas for the Miller capacitance two discrete values are simplified, which change at V _GS = V _DS . [3]

In this work, the modeling of the switch capacities is based on this simple model concept. The equivalent circuit diagram in 115 can be simplified in certain stages of the switching process: since transient analysis is the most general type of analysis, one could assume that it also includes the elements of the other types of analysis, provided that the same conditions are met. For simplicity, therefore, a capacitance as in DC analysis is considered to be an interrupt when the voltage across it is constant, because then no current can flow into that capacitance. Thus, when switching, for example during current and voltage commutation, certain simplifications arise which can be consciously utilized in the simulative implementation of the switch capacities (cf. 116 Model of a MOSFET in the stationary states a) on and b) off or during the c) current commutation and d) voltage commutation). To illustrate which capacitance values act during commutation, in 117 characterized in an idealized capacity curve, these areas.

From the point of view of the simulation, it is particularly important that the drain current and the drain source voltage waveform are simulated correctly in order, for example, to be able to estimate the switching losses. Therefore, the capacities for the current and voltage commutation should be properly modeled. The other phases play a less important role during the switching process. _When switched on, only the on-resistance r _{ds (on)} is effective. During the current commutation or as long as a current flows through the channel, it can be assumed that there is a parallel connection of the two capacitances C _GS and CDs from the point of view of the drive circuit (cf. 118 - replacement circuit during current commutation). On the other hand, if one analyzes the circuit between the drain and the gate, one can not speak of a parallel connection since there is no current path from the gate via the gate capacitance to the drain connection. Therefore, the capacities in this voltage range are also different from each other (cf. 119 ). During voltage commutation, only the drain-gate capacitance acts, so that the feedback capacitance determined during the voltage commutation corresponds to the drain-gate capacitance. When switched off, due to the large switch-off resistance r _{ds (off),} a very small reverse current flows through the switch. This is usually negligible.

119 (Possible relationship between input and feedback _{large-signal capacitance} (I _L = 150 A, R _G = _180Ω , T _j = 25 ° C, and V _DClink = _30V )) is the basis for further consideration. It represents the input capacitance Ciss _LS (V _GSmess ) in its usual form, but the feedback capacitance Crss _LS determined from measured data is not represented as usual above the drain-gate voltage but above the measuring voltage V _GS . The third characteristic represents a parallel shift of the feedback capacitance characteristic around C _const . The result is quite surprising and constitutes a legitimation for the fact that a constant gate capacitance C _GS = C _{const can be set} in the behavioral model and all nonlinearities can be inserted in the Miller capacitance.

On this way would be during current commutation, from the gate circuit, and during the voltage commutation the right capacitance values between the drain and gate Act. Thus, the correct capacity acts in this period fair the dV / dt coupling so that the voltage transients are relative can be simulated exactly. This also affects the Simulation accuracy of the switching losses.

119 Although it also makes it clear that faulty capacitance values outside the current commutation act in the gate circuit However, before further statements can be made in this regard, some switching characteristics must first be simulated and assessed. However, it is still to be expected that the simulation results are much more accurate than the resulting switching curves with the approximation explained by [3].

4. Verification of the capacity characteristics

4.1. Switch model with voltage-dependent Drain-source capacitance

The Simulation is one possibility the determined capacity characteristics to check their accuracy. The used one Low-voltage trench gate MOSFET bridge branch must therefore by a suitable switch model can be modeled. This will be done in the following sections the switch model used Et3g for low-voltage MOSFETs explained and documented.

4.1.1. Input and output variables of the switch model

• • das Ansteuersignal X und
• • die über dem Schaltermodell abfallende Knotenspannung v_k.

The switch model receives as input variables

• • the drive signal X and
• • the node voltage v _k falling over the switch model.

• • der Schalterstrom i_s,
• • der Kanal- bzw. Transistorstrom i_t,
• • der Diodenstrom i_d,
• • der Gatestrom i_rg,
• • die Schalterspannung u_s,
• • die Gatespannung u_gs,
• • die Spannung v_rls über der Schalterinduktivität L_s und dem Schalterwiderstand R_s,
• • die Millerkapazität Crss und
• • die Zustände des Schaltermodells str.

Output variables of the switch model are

• The switch current i _s ,
• The channel or transistor current i _t ,
• The diode current i _d ,
• The gate current i _rg ,
• The switch voltage u _s ,
• The gate voltage u _gs ,
• The voltage v _rls across the switch _inductance L _s and the switch _resistance R _s ,
• • the Miller capacity Crss and
• • the states of the switch model str.

The attentive reader will notice that the "u" and "v" symbols are used for the time-varying voltages. These two terms allow the user to distinguish between simulated switch voltage (u) and simulated measurement voltage (v). Thus, while "u" denotes pure chip voltages, "v" denotes voltages including switch inductances and resistances (see FIG. 120 ).

4.1.2. States and switching conditions of the switch model

• Zustand 0: Aus
• Zustand 1: MOSFET ein, Diode aus
• Zustand 2: MOSFET aus, Diode ein
• Zustand 3: Synchronbetrieb
• Zustand 4: Reverse Recovery der Diode
• Zustand 5: Reverse Recovery der Diode und MOSFET ein

The simulation model is organized as a state machine with the following states:

• State 0: Off
• State 1: MOSFET on, diode off
• State 2: MOSFET off, diode on
• State 3: Synchronous operation
• Condition 4: reverse recovery of the diode
• Condition 5: reverse recovery of the diode and MOSFET on

121 shows the Petri net of the switch model with the corresponding transition conditions. Although state 3 is mentioned here for the sake of completeness, it is not further documented. Synchronous operation is a reworking rudiment of earlier switch model generations. In the present model, the synchronous operation does not work and would have to both development of the switch model adapted to the present model version. The user can therefore not operate the model in synchronous mode.

• • die Schalterspannung u_s,
• • der Schalterstrom i_s,
• • der Diodenstrom i_d,
• • der Transistorstrom i_t,
• • die Spannung über der Schalterinduktivität v_ls und
• • die Spannung über der Schalterinduktivität und dem Schalterwiderstand v_rls,

In the individual structure states, the following variables are calculated according to the special features of these states:

• The switch voltage u _s ,
• The switch current i _s ,
• The diode current i _d ,
• The transistor current i _t ,
• • the voltage across the switch inductance v _ls and
• The voltage across the switch _inductance and the switch _resistance v _rls ,

A detailed description of the various calculations of these quantities in the individual states is omitted here. In states 1 and 5, the output characteristic field and in state 2 the diode characteristic is traversed. However, the simulation of the internal inverse diode can only be described as trivial. While the diode is simulated with the static diode characteristic in the on state with sufficient accuracy, the typical switch-on behavior of the diode is disregarded. During the transition of the diode into the conducting state, the voltage initially rises to the switch-on voltage peak V _FRM before it drops to the forward voltage V _F (cf. 122 [1]). The present model simply calculates the passage of the diode characteristic. The characteristic switch-off behavior (cf. 123 [1]) is simulated by specifying end values in states 4 and 5 as well as with the aid of the time constants Td and Trr, but these time constants of the switch model can not yet be substantiated physically and must be determined by a complex comparison of simulation and measurement for each individual operating point be made sense.

4.1.2. Output characteristic field (AKF) of the switch model

The basis of the modeling of the output characteristic field is the transfer characteristic (transfer function) of the transistor. Both the transfer characteristic and the output characteristics are static characteristics. With negligible internal resistances and connection resistances, the internal chip voltages correspond approximately to the measuring voltages: ν _DS ≈ u _DS and ν _GS ≈ u _GS

4.1.3.1. Modeling the transfer characteristic

The transfer characteristic describes the behavior of the drain current I _D as a function of the gate-source voltage V _GS at a fixed drain-source voltage V _DS : I D = f (v GS , V DS = const.). (4.1)

124 [27] shows a measured transfer characteristic of the low-voltage trench gate MOSFET at V _DS = 30 V and T _j = 125 ° C.

folgende Abhängigkeit von der Gate-Source-Spannung u_gs umgesetzt worden:

Transfer characteristics can be modeled by higher order polynomials that have no poles in the allowable range of operation. In the switch model is for the drain current of the transfer characteristic

following dependence on the gate-source voltage u _{gs has been} implemented:

In order to facilitate the determination of the transfer characteristic polynomial, it is advisable to transfer the measuring points from the threshold voltage to the Curve Fit program and to limit the transistor current to the lower limit

However, the limiter functions present in the simulator always have a lower and an upper limit. A reasonable upper limit would be the current of the output characteristic I _D = f (V _DS , V _GS = V _Dr ) at which the switch goes into current saturation. However, there are usually no measured data for these areas of the output characteristic field, since these operating points can not be approached with the usual measuring devices or, due to the resulting losses in the switch, immediate thermal effects act which would call the measured data into question. Therefore, it is recommended that the user specify as upper limit a maximum current value, which corresponds approximately to the 5 to 6 times the rated current of the switch. This drain The current lies in the output characteristic field, which is usually not reached in either switching operation or in the event of a short circuit, and thus has no influence on the simulation. Incidentally, the indicated current saturation is also already implemented by the modeling of the output characteristic field explained below.

4.1.3.2. Modeling the output characteristic field

An output characteristic describes the dependence of the drain current I _D as a function of the drain-source voltage with the gate-source voltage as a parameter: I D = f (v DS , V GS = const.). (4.3)

125 [27] shows measured output characteristics of the low-voltage trench gate MOSFET at different V _GS voltages at T _j = 125 ° C.

The designations used below for mathematical replication correspond to the designations used in the model. Since a current injection is expected in the switch model, the following explanations and the associated ones relate 127 on the inverse function of the output characteristic definition: V DS = f (I D , V GS = const.). (4.4)

The modeling of the active region can be done by generating a parallel set, since the slope r _s in the current saturation region of all output characteristics is approximately equal and almost fair the entire region constant:

From the transfer characteristic, a point (u _{ds_trans} ; i _{t_trans} ) of the corresponding output characteristic can be determined for each gate-source voltage (cf. 126 ). The voltage u _{ds_trans} for all these points is the drain-source voltage at which the transfer function was measured. The increase r _s is approximated from the measured AKF: r s = ΔV DS / .DELTA.I D , (4.6)

By inserting the point (u _{ds_trans} ; i _{t_trans} ) in the parallel _equation , the intersection point n _i with the V _DS axis can be determined: n i = u ds_trans - r s · i t_trans , (4.7)

The parallels can thus generally be detected by the following equation and implemented in the switch model: u ds_ps = r s · i t + ds_trans - r s · i t_trans · (4.8)

) aufeinander liegen. Deutlich wird auch, dass die Nachbildung der Übertragungsfunktion die Qualität des Aktiven Bereiches beeinflusst, weil sie die Lage der Ausgangskennlinien festlegt.It should be noted that the output characteristics for gate-source voltages below the threshold voltage (V _GS ≤

) lie on one another. It is also clear that the simulation of the transfer function influences the quality of the Active Area because it determines the position of the output characteristics.

The characteristic field must be limited. When the breakdown voltage is exceeded, the current increases very strongly. The upper limit is therefore the avalanche voltage V _{AV of} the switch. Down the characteristic field is limited by the ohmic range. The on-resistance r _{ds (on)} is particularly voltage-dependent for MOSFETs. Therefore, the ohmic range of the output characteristics was modeled with a straight line:

The straight lines go through the origin and their rise m is determined as a function of the gate-source voltage. To identify the necessary parameters, measured r _{ds (on)} -Kenn approximates lines as linear equations and determines a polynomial m = f (u _gs ) for the ascents thus determined:

This Polynomial is allowed over the entire domain of gate voltage have no poles and is in the simulator up and down limited to facilitate finding a matching polynomial. The change from Ohm to Active is greatly simplified. To more steadily model the transition to the boundaries, There is a softknee factor for the top and bottom Border (SK_o and SK_u).

4.1.4. Transmittance behavior of the diode

The transmission characteristic of the inverse diode can be simulated correspondingly by a polynomial. Since the model assumes a current injection, the following polynomial is implemented in the simulator, which corresponds to the inverse function of the diode characteristic:

Also here it must be ensured that the domain of definition is no Contains poles. A limitation of the function exists in the existing model not yet, but the installation would be to exclude possible poles recommended.

4.1.5. Modeling the gate circuit

The gate circuit is constructed with the following equations (cf. 128 ):

The switch model combines all the resistors and inductances of the switch and does not differentiate between source, drain and connection inductances or internal resistances and connection resistances. Therefore, the factor Ki has been introduced to simulate di / dt feedback (see Section 2.2.1.). Ki results from the ratio of the source inductance to the switch inductance:

In addition to those in Section 4.1.2. - States and switching conditions of the switch model - states described the model distinguishes by means of the drive signal X, whether the driver voltage U _dr applied or not.

4.1.6. Modeling the voltage-dependent Drain-source capacitance

The modeling of a voltage-dependent capacitance Crss for the simulation of the dv / dt feedback (see Section 2.3.2 - dVDS / dt - Feedback through the drain-gate capacitance) is also realized with a polynomial. Since the switching characteristics are relatively sensitive to changes in capacitance, a polynomial of the fifth degree was used to enable the most accurate simulation of the characteristic curve:

Since more poles occur in polynomials of higher order and it is therefore more difficult to find a polynomial that has no poles over the entire domain of definition, in addition to the limitation of Cm also a limitation of the drain-gate voltage in the simulator has been made possible. The drain-gate voltage changes in the course of a switching operation between the negative drive voltage in the switched-on and the intermediate circuit voltage in the off state and can also increase beyond the intermediate circuit voltage when switching off due to the resulting overvoltage. However, in this range of drain-to-source voltage, the Miller capacitance is approximately constant, so if limitation in that direction becomes necessary, the accuracy of the simulation is largely maintained. The restricted function Cm 'can then be moved with the offset Om: Crss = Cm '+ Om. (4.18)

The displacement _current i _dg results from:

4.2. Parameterization of the switch model in the buck converter

4.2.1. Parameter of the model

The switch model Et3g has the following parameters: Parameters of the output characteristic field t _i (with i = 0..7) : Coefficients of the transfer characteristic Uth : Threshold voltage of the transfer characteristic Uds_trans : Drain-source voltage of the transfer characteristic rs : Increase of the output characteristic to the active range uAV : Avalanche voltage of the switch rds _i (with i = 0..4) : Coefficients of the polynomial m _rd = f (u _gs) SK_o : Soft Knee Factor for Transition to Upper Limit (Uav) Sk_u : Soft knee factor for transition to lower bound (r _{ds (on)} straight) Parameters of the integrated inverse diode d _i (with i = 0..4) : Coefficients of the diode characteristic trr : Time constant for setting the reverse current break td : Time constant for setting the reverse current peak Parameters of the commutation inductances and resistances R _s : Switch resistance L _s : Switch inductance Ki : relative proportion of Ls causing the di / dt feedback Krlm : relative proportion of Ls lying between the measurement points of v _ds Parameters of the gate circuit Cgs : Gate capacity of the switch rg : Gate resistance vdr : Driver voltage Miller capacity and du / dt feedback parameters m _i (with i = 0..10): Coefficients of the polynomial Cm = f (ν _dg ) U _{m_u} : lower limit of the voltage v _dg as argument of Cm U _{m_o} : upper limit of the voltage v _ds as argument of Cm C _{m_u} : lower limit of millimeter capacity Cm C _{m_o} : upper limit of millimeter capacity Cm O _m : Offset for shifting the polynomial Cm ' Tu: Time constant with the v _{dg is} differentiated

It should be noted that the units of Cm_u, Cm_o, Om and Tu are the unit of fit Miller capacity curve. If, for example, the Miller capacitance [nF = 10 ^-9 F] has been fitted as a function of the drain-gate voltage v _dg [V], then Tu = 10 ^-9 and the values Um_u, Um_o, Cm_u, Cm_o and Om are also set the unit nF.

4.2.2. Determination of the parameters of the switch model

• • Quantisierungsfehler der AD-Wandlung im Oszilloskop und im Curve Tracer
• • Offsetfehler des Oszilloskops und des Curve Tracers
• • Bit-Auflösung des Oszilloskops und des Curve Tracers
• • Tastköpfe
• • Pearsonsonde
• • Rauschen
• • ...

In order to check the plausibility of the determined capacitance characteristics, all switch-specific parameters for the present MOSFET bridge branch must first be determined from the data sheet or from the measurements. The following sections, however, may not be intended to accurately determine the inductances and characteristics. Rather, it is about finding orders of magnitude to provide the switch model with realistic parameters. However, the measurement data is only recorded on a sample so that no scatters are taken into account and averages are formed. A more exact determination of the values can not make sense for this reason. Therefore, a mistake is omitted. Instead, only a few sources of error are mentioned:

• • Quantization error of the AD conversion in the oscilloscope and in the Curve Tracer
• • Offset error of the oscilloscope and the Curve Tracer
• • Bit resolution of the oscilloscope and the Curve Tracer
• • probes
• • Pearson probe
• • Noise
• • ...

4.2.2.1. Parameters of the output characteristic field and the diode characteristic

wurden mit Hilfe von TableCurve 2D mit folgendem Ergebnis ermittelt (vgl. 129):

• t₀ = –354,85082
• t₁ = 315,39758
• t₂ = –93,802305
• t₃ = 9,339166
• t₄ = 1,
• t₅ = –0,56186353
• t₆ = 0,098355257
• t₇ = –0,0017673537.

The coefficients of in 124 represented, at Uds_trans = 30 V measured transfer characteristic

were determined with the help of TableCurve 2D with the following result (cf. 129 ):

• t ₀ = -354,85082
• t ₁ = 315.39758
• t ₂ = -93.802305
• t ₃ = 9.339166
• t ₄ = 1,
• t ₅ = -0.56186353
• t ₆ = 0.098355257
• t ₇ = -0.0017673537.

From the measurement, a threshold voltage U _th = 3.2 V was determined.

The factor r _s is very difficult to evaluate from the measured characteristic field. The rise of the characteristics is different not only within an output characteristic, but r _s is also different from curve to curve. Since a model is a simplified representation of reality, a constant increase of all output characteristics in the active range has been assumed in favor of the computing speed and at the expense of accuracy. Looking at the 125 , so this assumption for the MOSFET bridge branch used seems to be close to a good approximation. This is not true for all low-voltage MOSFETs too. In general, this assumption is true only for certain areas of the output characteristic field. Thus, in the range of the nominal current, the increase r _s = ΔV _DS / ΔI _D = 3.2 Ω was determined and defined for the simulation. In principle, it would also be conceivable operating point-dependent r _s set when changing the climbs too strong. For operating points around the nominal current, a different value may result than for operating points which are only 1/10 of the rated current. The increase r _s is and remains an average. A more accurate replica of the Active range is not possible with this model!

The Avalanche voltage of the switch is according to the data sheet at 75 V. [27].

wurden mit Hilfe von TableCurve 2D mit folgenden Werten bestimmt (vgl. 130):

• rds₀ = 0.040194805
• rds₁ = 0
• rds₂ = 0,0015956115
• rds₃ = 0
• rds₄ = 0,22509648

The coefficients of the polynomial

were determined with the help of TableCurve 2D with the following values (cf. 130 ):

• rds ₀ = 0.040194805
• rds ₁ = 0
• rds ₂ = 0.0015956115
• rds ₃ = 0
• rds ₄ = 0.22509648

The pictures 131 and 132 represent the simulated output characteristic field compared to the measured and show how it _turns on and off (I _L = 150 A, R _G = 10 Ω, V _DClink = 30 V _Dr U _Dr = 12 V and T _j = 125 ° C ). However, the illustrated switching on and off curves are the measured quantities. In the simulation, the output characteristic field is computationally traversed with the channel current i _t and the gate voltage u _gs as input. It provides as output the switch voltage u _s . The courses can therefore only be regarded as a guide. They differ from the transistor-internal variables by the effect of commutation inductances and commutation capacities.

When generating the output characteristic field in the simulator, it was also analyzed which soft-edge factors produce the best result. The result of this analysis is that with the help of these factors, the transition from the ohmic to the active region is not replicable. The so-called R _{DS (on)} lines are not straight lines and deviate from the approximated straight lines as the drain-source voltage increases, so that errors are made here during the simulation. The effect is consistently stronger at higher gate voltages. The pictures make it clear that the Ohm's range is otherwise relatively accurate and that hardly any simulative errors are made. The active range seems to simulate relatively well below the nominal current. It turns out, however, that the simplistic assumption that r _s is constant leads to inaccuracies. The longer the transistor stays in these defective areas, the more important is the exact replica for best simulation results. In this context, it should be considered whether it would be more effective to measure the transfer function and the ACF very precisely, to use the measurements thus obtained directly for the simulation and to interpolate linearly between the measured points, rather than the relatively complex determination of the parameters to carry out the measurement data.

wurden mit Hilfe von TableCurve 2D mit folgenden Werten bestimmt (vgl. 133):

• d₀ = 0,22908059
• d₁ = 0,47814107
• d₂ = 0,0030868108
• d₃ = 0,78775813
• d₄ = 0,00023899839

The coefficients of the diode characteristic

were determined with the help of TableCurve 2D with the following values (cf. 133 ):

• d ₀ = 0.22908059
• d ₁ = 0.47814107
• d ₂ = 0.0030868108
• d ₃ = 0.78775813
• d ₄ = 0.00023899839

4.2.2.2. Determination of inductances and resistances

The switch model does not differentiate between the internal inductances and the connection inductances, but only processes the switch inductance L _s . Due to the factors Ki and Krls in L _s ne ben the actual switch inductance in addition, the DC link inductance may be included. Nevertheless, as much information as possible about the individual inductances can be obtained from the measurement data of the industrial sample so that the simulation parameters Ki and Krls can obtain real values. The determination of the di / dt feedback parameter Ki takes place, as explained above, with the equation (4.16). For the determination of the measuring voltage results for the parameter Krls:

The basic structure of the buck converter circuit used to obtain the measurement data is in 14 shown. From the recorded measurement data, it is possible to determine the inductances which lie outside the measuring points P3 and P2 or between P4 and P2. They cause an overvoltage between the points when the lower transistor is switched on due to the positive current increase and a voltage release when the negative current increase is switched off (cf. 134 - Voltage drop across the inductors when switching on and off switch 2). For calculating the _{DC link} inductance L _DClink and the inductance L _{1 of} the upper switch, the turn-off characteristics of transistor T _{2 were} investigated for different load currents I _L (Tj = 125 ° C, V _DC = 30 V and R _G = 10 Ω).

135 (Switching off of T ₂ at I _L = 150 A, V _DD = 30 V, R _G = 10 Ω) shows the example of the measurement curves of the drain current I _D , the half-bridge voltage V _HB , the drain-source voltage V _DS and the gate -Source voltage V _GS at a load current of 150 A, the determination of the voltages for the determination of the voltage drop across the inductors and the associated current increase from the measured data.

The DC link inductance was calculated approximately. It results as a quotient of the difference between the maximum value of the half-bridge _voltage V _HBmax and the mean value of the half-bridge _voltage in the switched on and off state (V _HBoff and V _HBon ) and the current increase during the voltage peak ΔI _D / Δt:

The different half-bridge _voltages in the switched on and off state come about through the ohmic resistance R _DClink in the _{DC link} . When the lower switch T ₂ is turned on, a current flows in the intermediate circuit which causes a voltage drop across these resistors which reduces the half-bridge voltage V _HB : V HBVon = V DClink - I D · R DClink , (4.21a)

On the other hand is V HBOFF = VD Clink , (4.21b)

During current commutation, V _{R_DClink drops} from V RDClink = I D · R DClink , (4.21c) on V RDClink = 0V (4.21d) and thus does not remain constant. However, this change should be considered in the calculation for reasons of accuracy. Therefore, for simplicity, the average of V _HBoff and V _{HBon was chosen} for the calculation. On the other hand, if the drain-source voltage is considered, then the sum of the inductances in the intermediate _circuit L _DClink and in the upper switch L _{1 can be} calculated accordingly:

The mean value of the drain-source voltage in the off state V _DSoff , the diode passage voltage V _F and the half-bridge voltage in the on state V _HBon was again used as a simplification to take into account that at the beginning of the current commutation V DS = V F + V HBon (4.22a) and towards the end V DSoff = V HBOFF + V SD (I L ) (4.22b) is applied to the switch. Due to this simplification, the changes that are not caused by the inductances can be included in the inductance calculation. The forward voltage was determined by linear approximation of the transmission characteristic at T _j = 125 ° C. The resulting intersection with the V _SD axis at V _SD = 0.62 V was used in the calculations for V _F. The temperature dependence of the characteristic has not been taken into account (cf. 137 ), ie all considerations are based on the simplifying assumption that T _J remains constant and does not increase even at higher currents due to higher losses.

The results of the evaluation of the measured data are summarized in the following table: I _L ^{[ A ]} L _{DClink & 1} [nH] L _DClink [nH] L ₁ [nH] R _DClink [Ω] 10 10.7 7.4 3.3 0,018 30 10.5 7.7 2.8 0,012 50 10.1 7.9 2.2 0,014 75 10.7 8.5 2.1 0,015 100 10.5 8.3 2.2 0.12 150 10.3 8.3 2.0 0.13

These results for the _{DC link} inductance L _DClink and the inductance L _{1 of} the upper switch were _checked at the switch-on characteristics of the lower switch T ₂ at T _j = 125 ° C., V _DC = 30 V and R _G = 10 Ω for different load currents I _L see.

136 (Switching on of T ₂ at I _L = 150 A, V _DD = 30 V, R _G = 10 Ω)). The inductances L _DClink and L ₁ result accordingly from the following equations:

Here V _{HBmin (+ di / dt)} and V _{DSmin (+ di / dt) represent} the voltage _minima which are reached during the positive current increase (cf. 136 ). The results of the evaluation of the measured data are summarized in the following table. The evaluation of the switch-on process roughly confirms the values that were determined from the data at switch-off. The different inductance values when switching on and off should be checked again in further measurements. I _L [A] L _{DClink & 1} [nH] L _DClink [nH] L ₁ [nH] 10 13.3 11.7 1.5 30 12.9 10.6 2.3 50 12.2 10.4 1.7 75 12.6 10.7 1.8 100 12.0 10.2 1.8 150 13.0 10.4 2.9

To determine the inductance L _{2 of} the lower switch and to verify the _{DC link inductance} L _DClink measurement data were evaluated, however, submit only for the switching off of T ₁ for two different gate resistors R _G and load currents I _L. 138 (Switching off T ₁ with diode current measurement D2 at I _L = 150 A, V _DD = 30 V, R _G = 10 Ω) and 139 (Switching off T ₁ at I _L = 150 A, V _DD = 30 V, R _G = 10 Ω) show the determination of the relevant data. It is noticeable that two different measuring methods were used. The reason for this is that in the existing measuring circuit, the current can only be measured by the lower switch, that is to say by transistor T ₂ or diode D ₂ . When the transistor T ₁ turns off, then the diode D ₂ turns on passive. The current flow in 138 is thus the already inverted diode current, which corresponds approximately to the current through T ₁ . The voltage measurement across the upper MOSFET was measured with a differential head that is ground reference. However, this goes from 42 V in the limit, as can be seen at the kink in the drain-source voltage. Therefore, only the determined current increase can be used from this measurement.

The second measurement was made at the upper switch, where + _{VDClink was} selected as ground reference _point . Consequently, the data had to be inverted and offset before the evaluation before the necessary voltage values could be read. The desired inductances can then be calculated as follows:

The results are summarized in the table below. It should be noted that the use of two different measurements to determine the necessary parameters can lead to erroneous results. I _L [A] R _G [Ω] L _{DClink & 2} [nH] L _DClink [nH] L ₂ [nH] R _DClink [Ω] 150 10 15.4 8.7 6.7 0,013 300 10 15.2 8.7 6.5 0.011 150 1.2 15.4 8.6 6.9 0.019 300 1.2 16.3 8.9 7.3 0,018

The _{DC link inductance} L _DClink has been re-solidified, but it is noticeable that the inductance of the lower switch is about three times that of the upper switch. This finding is confirmed by an analysis of the construction drawing of the Trench Power MOSFET used. On the basis of the measurement data _evaluation , L _DClink = 9 nH, L ₁ = 2.5 nH and L ₂ = 7 nH have been determined and the following transistor _inductances and K _rlm values have been determined (compare equation (4.20)). In this case, half of the DC link inductance was proportionally attributed to the switch inductances. L s1 = 0.5 · 9nH + 2.5nH = 7nH L s2 = 0.5 9nH + 7nH = 11.5nH K RLM1 = 0.36 K rlm2 = 0.61 R s1 = R s2 = 5 mΩ

The estimation of the individual inductances was carried out with the aid of the construction drawing. Since a load current impression is assumed, the voltage drop across the load inductance is negligible. Consequently, the determined inductance values L _s1 and L _s2 consist only of the corresponding source and drain inductances. Assuming that the average current path length is proportional to the inductance, the partial inductances were estimated from the length ratio of the source to the drain inductance from the upper and lower switches and the corresponding Ki values were determined for the simulation (compare equation (4.16)): inductance [NH] L _D1 2.0 L _S1 0.5 Ki ₁ 0.07 L _D2 3.5 L _S2 3.5 Ki ₂ 0.3

4.2.3. Integration of the parameterized switch model in the buck converter

140 shows the integration of the switch models in the buck converter circuit in the simulator. (The associated measuring circuit is in 14 The following equations are therefore calculated in the simulator:

The RC element, which is not included in the associated measurement circuit, is an aid to be able to determine the potential between the two switches in the current leakage region. Depending on the capacity _{ratios of} the two switches, this may differ from U _DClink / 2. With the help of this RC element vibration frequencies and amplitudes can be adjusted. In this context, however, there is still a need for analysis, which physical variables are modeled by this member, which are otherwise not included in the model. Thus, R _b and C _{b represent} two parameters that still have to be set by trial and error. However, it may be assumed that the output capacitance and the parasitic ohmic and capacitive impedance of the load coil, which are not further taken into consideration in the switch model, are possibly contained in these parameters. Corresponding consequences for the modeling of the step-down converter circuit, such as, for example, that the auxiliary element is to be implemented parallel to the load coil, can, however, only be drawn after further investigations.

In addition to the node voltage v _{k of} the voltage-impressed switch model resulting from equation (4.31), the drive signal X is a further input variable of the switch model. To generate this signal, an automatic control unit is used in the simulation.

This results in the following additional parameters for the simulation in addition to the parameters of the switch model: Parameters of the automatic control unit: Vt : Duty cycle tp : Pulse period tv : Branch lock time aw : Initial value Other parameters of the buck converter: U _DClink : DC link voltage uq : _{Auxiliary voltage} to clamp the load to + or - U _DClink L ₁ : Coil in the load circuit R ₁ : Resistance in the load circuit cb : Auxiliary capacity Rb : Auxiliary resistance

4.2.4. Summary of the parameters of the used measurement setup

Parameters of the output characteristic field Coefficients of the transfer characteristic: t ₀ = -354,85082 t ₁ = 315.39758 t ₂ = -93.802305 t ₃ = 9.339166 t ₄ = 1 t ₅ = -0.56186353 t ₆ = 0.098355257 t ₇ = -0.0017673537 Threshold voltage of the transfer characteristic: U _th = 3.7V Drain-source voltage of the transfer characteristic: U _dstrans = 3.7 V Increase of the output characteristic in the active range: rs = 3.2 Ω Avalanche voltage of the switch: U _AV = 75V Coefficients for determining the R _{DS (on)} straight line: rds ₀ = 0.040194805 rds ₁ = 0 rds ₂ = 0.0015956115 rds ₃ = 0 rds ₄ = 0.22509648 Soft Knee Factors Limiting Active Area: S _{K_o} = 0 SK_u = 0 Parameters of the integrated inverse diode Coefficients of the diode characteristic: d ₀ = 0.22908059 d ₁ = 0.478 14107 d ₂ = 0.0030868108 d ₃ = 0.78775813 d ₄ = 0.00023899839 Time constant for setting the reverse current peak: Td is operating point dependent Time constant for setting the reverse current break: Trr is dependent on the operating point Parameters of the commutation inductances and resistances L _S1 = 7nH L _S2 = 11.5 nH Ki1 = 0.07 Ki2 = 0.3 Krlm1 = 0.36 Krlm2 = 0.61 R _S1 = 0.005 mΩ R _S2 = 0.005 mΩ Parameters of the gate circuit Gate capacity of the switch: Cgs = 5 nF Gate resistors: Rg1 is operating point dependent. Rg2 is operating point dependent. Driving voltage: Vdr is working point dependent. Parameters of the used Millerkapacitätskennlinie and du / dt feedback m ₀ = 9.88806 m ₁ = 2.0574 m ₂ = 19.3493 m _{3 =} -1.81321 m ₄ = 0.752699 m ₅ = 0 m ₆ = 0.500754 m ₇ = 2.581380 m ₈ = 0.620787 m ₉ = 0.198495 m ₁₀ = 0.0125828 Tu = 1e ^-9 Limiting the Miller capacity Cm_o = 20 Cm_u = 1 Limitation of the voltage v _dg Um_o = 40V Um_u = -15V Parameters of the automatic control unit: duty cycle: Vt = 0 Pulse period: Tp is operating point dependent Branch locking time: tv is only relevant for synchronous operation Other parameters of the buck converter: Intermediate circuit voltage: U _DClink is _{operating point dependent} . _{Auxiliary voltage} to clamp the load to + or - U _DClink : Uq is operating point dependent. Auxiliary capacity: Cb must be set by trial and error. Auxiliary resistance: Cb must be set by trial and error. Load Impedance: Is to be oriented on the measurement setup.

4.3. Investigation of the capacity characteristic in one working point

Since the parameterization of switch capacities in switch models is relatively problematic, the focus of the work "Parameter extraction of a low-voltage Trench Gate MOSFET half-bridge and simulation in a state-controlled behavioral model" has been focused on the determination and verification of switch capacitance, especially of the retroactivity The aim of this study is to clarify the plausibility of the characteristics determined in Chapter 3 - Determining the Capacities by means of Transient Analysis - The investigations were carried out last in the present work, which means that the results are at the highest level of knowledge, which means that both offset correction of the gate current the measured data used was taken as well as the parasitic elements were taken into account In subchapter 3.8 - model concept of the switch capacitances fair the simulation - has already been explained that the gate capacitance for the documented switch model ET3g should be regarded as constant. For constant capacities, the following equations apply

Latter was used in the modeling of the gate circuit (see section 4.1.5. - Modeling the gate circuit - Equation (4.15)). Furthermore, it was shown that all nonlinearities be put into the reaction capacity. That it is related to the resulting current through a nonlinear capacity does not matter if the differential capacitance or the large signal capacity is stated in subsection 3.2 - Nonlinear Capacitance - large signal and small signal capacity - shown Service. As the current equation of the differential capacitance has a simpler structure (see Section 3.2, Equation (3.2)) in the modeling of the displacement or coupling current through the reaction capacity is used (see section 4.1.6. - Modeling the drain-gate capacitance - Equation (4.19)).

141 essentially corresponds 119 , Differences in the two figures result only from the offset correction of the measured gate current and the consideration of the parasitic elements. Furthermore, not only the input but also the switch-off characteristics of the capacities Crss _LS and Ciss _{LS were} shown. The turn-off characteristics usually play a greater role in the simulation, since the turn-off losses have the largest share of the switching losses. 141 (Comparison of large signal input and response capacitance as a function of the gate-source voltage (I _L = 150 A, R _G = 180 Ω, T _j = 25 ° C and V _{DC link} = 30 V)) is the basis for determining the value the gate capacitance for the parameterization of the switch model. The difference of the two Ausschaltkapacitätskennlinien lies during the current commutation between 6.6 and 6 nF (see. 142 - CiSS _{LS (off)} difference - Crss _{LS (off)} as a function of the gate-source voltage). As a result, the gate capacitance should be populated with a value in this range.

For the parameterization of the feedback capacitance, the switch-off characteristic of the differential capacitance Crss _diff (R _G = 10 Ω) is chosen because of the dependence of the characteristic on the switching speed in the area of the intermediate circuit voltage, since in this subchapter only the switching characteristics for the rated operating conditions (I _L = 150 A R _G = _10Ω , T _j = 25 ° C and V _DClink = _30V ). For the investigations in subsection 3.5.2.2. - Differential reaction capacity Crss _diff (R _G ) - the gate current was not corrected. Therefore, the characteristic is again determined for a resistance of 10 Ω and using TableCurve 2D fitted. The 143 (Polynomial approximation of the charge curve (I _L = 150 A, R _G = 10 Ω, T _j = 25 ° C and V _DClink = 30 V)) first shows how the charge curve Qr _{(off) was} fitted. 144 then compares the fitted charge curve Qr _fitt and the differential capacitance Crss _{diff_fit} determined _therefrom with the charge curve _Qr determined from the measured data and the differential capacitance Crss _diff calculated therefrom. Finally ask 145 (1st variant of the polynomial approximation of Crss _{diff_fit} (I _L = 150 A, R _G = 10 Ω, T _j = 25 ° C and V _DClink = 30 V)) and 146 (2nd variant of the polynomial approximation of Crss _{diff_fit} (I _L = 150 A, R _G = 10 Ω, T _j = 25 ° C and V _DClink = 30 V)), two variants are available, as the determined capacitance curve _Crss diff_fit _approximates by a polynomial can be. Variant 1 reproduces the reaction capacity until the overvoltage peak is reached. However, clarifies 144 Again, with fast switching, the differential capacitance after reaching the spike is much smaller than the capacitance values that result at the same voltages before the spike. The approximation of the characteristic, as shown in 146 shown, the resulting errors could reduce something. Although the reaction capacitance is initially too low after reaching the intermediate _circuit voltage, the deviations after reaching the overvoltage peak are lower here than in variant 1. _Further optimization of the capacity _selection in the region between the intermediate _circuit voltage V _DClink and the overvoltage _peak V _DGmax should be _pursued Generate statements.

• • Der (konstante) Gatewiderstand spiegelt die ohmschen Verhältnisse im Gatekreis nicht richtig wider.
• • Die Rückwirkungskapazität ist in diesem Bereich zu groß.
• • Die Gatekapazität C_GS ist zu groß.

The first results of the simulation are documented and briefly commented on ( 147 (Comparison of the measured and simulated switch-off characteristics (I _L = 150 A, R _G = 10 Ω, T _j = 25 ° C and V _DClink = 30 V with C _GS = 6 nF and Crss _{diff_fit} (Variant 1)) and 148 (Comparison of the measured and simulated switch-off characteristics (I _L = 150 A, R _G = 10 Ω, T _j = 25 ° C and V _DClink = 30 V) with C _GS = 6 nF and Crss _{d iff_fit} (variant 2))). The switch model was compared with those in subchapter 4.2. - Parameterization of the switch model in the buck converter - assigned parameters. The switch capacities were chosen according to the terms of the pictures. First, due to their importance for the switching losses, the turn-off characteristics are to be considered. The simulation results are amazingly good. Also, the current and voltage curves of the two approximation variants of the differential feedback capacitance do not differ significantly from each other. The course of the simulated gate-source voltage, however, makes it clear that the modeling and parameterization of the gate circuit can be improved by considering additional parasitic inductances, resistances and capacitances [28]. Moreover, the time constant in the gate circuit seems to be too large during current commutation. Possible causes should only be mentioned in the context of this thesis, but not further investigated:

• • The (constant) gate resistance does not correctly reflect the ohmic conditions in the gate circuit.
• • The reaction capacity is too large in this area.
• • The gate capacitance C _GS is too large.

As a general rule should - if further improvements of the simulation are desired - first, the modeling of the gate circuit is reconsidered and then carry out appropriate investigations.

The switch-on characteristics are in the pictures 149 (Comparison of the measured and simulated curves (I _L = 150 A, R _G = 10 Ω, T _j = 25 ° C and V _DClink = 30 V) with C _GS = 6 nF and Crss _{diff_fit} (variant 1) - optimized maximum drain current ) and 150 (Comparison of the measured and simulated curves (I _L = 150 A, R _G = 10 Ω, T _j = 25 ° C and V _DClink = 30 V) with C _GS = 6 nF and Crss _{diff_fit} (variant 1) - optimized open-loop behavior) shown. The difference in the two figures results from the setting of the diode time constants T _d and T _rr . They were set for the turn-on process shown so that either the maximum drain current or the Aufsteuereffekt after the reverse current tear of the associated freewheeling diode was emulated as well as possible. No values for the diode time constants could be found which accurately simulate both the maximum drain current and the open-loop. Causes for it can be again Both in the modeling and parameterization of the gate circuit, but also in the primitive modeling of the diode. The switch-on _{characteristics were} simulated only with variant 1 of the differential reaction capacity _{Crss diff_fit} , since the corresponding investigations in section 3.5.4. - Comparison of the reaction capacity on switching on and off - have shown that the capacitance characteristics differ when switching on and off. For one _thing , the characteristic does not go beyond V _DG = V _DClink . On the other hand, it is relatively easy to estimate from the charge curve Qr _(on) (see, for example, the diagrams explained in section 3.5.4.) That the turn-on capacitance characteristic Crss _{diff (on)} between V _DG = V _{DS (off)} = V _DClink and the beginning of the current commutation, due to the relatively small increase of the drain-gate voltage in this region at turn-on, is above the turn-off characteristic Crss _{diff (off)} . For improved simulation processes, it should therefore be considered to integrate different characteristics into the simulator for switching on and off. In the context of this work, however, is waived. It should also be refrained from determining the differential capacitance Crss _{diff (on)} for the operating conditions examined in this subchapter. In summary, however, it can be seen for the simulated switch-on characteristics that they look surprisingly similar to the measurement curves. The simulation results of the parameterized buck converter are in the form of current and voltage curves as a function of time in the figures 147 . 148 . 149 and 150 shown. In order to improve the capacity model conception, however, it would also be interesting to see which capacity curves would result depending on the associated voltage if the simulated measurement data were evaluated in the same way as the measurement data. Therefore, for each operating point, the large signal feedback capacity Crss _LS (V _DG ) and the large signal input capacitance Crss _LS (V _GS ) are evaluated and compared with the corresponding courses resulting from the measured data. 151 (Simulated large signal input capacitance and charge curve as a function of the gate-source voltage) and 152 (Simulated large-signal reaction capacity and charge curve as a function of the drain-gate voltage) first show the evaluation of the simulation data. Ciss _LS (V _GS ) was determined for the following simulation parameters: load current I _L = 150 A; Gate resistor R _G = 180 Ω, and _{DC link voltage} V _DClink = 30 V. (For the parameterization of the feedback _capacitance , variant 1 in 145 used.) Crss _LS (V _DG ), on the other hand, was at I _L = 150 A; R _G = _180Ω , and V _DClink = _30V . With the associated measurement data (T _j = 25 ° C), the capacitance characteristics were shown in the figures 153 (Comparison of the capacitance Crss _{LS_sim} (VDGchip) of corrected simulated measurement curves with the input capacitance _{Crss LS_mess} (V _DGchip ) of corrected measurement _curves ) and 154 (Comparison of the capacity Crss _{LS_sim} (V _DGchip ) of corrected simulated measurement curves with the capacity Crss _{LS_mess} (V _DGchip ) of corrected measurement _curves ). While looking at the pictures 151 and 152 First of all, it is striking that the characteristic curves of the two capacitors are reproduced relatively well. However, the direct comparison with the associated measurement data also illustrates some shortcomings of the model. Thus, the characteristics determined from the simulation data tend to be lower than those resulting from the measured data.

154 would at least explain why voltage commutation during switch-on and switch-off is faster in comparison to the measured data (cf. 147 and 149 ). A reason for the too small time constants in the gate circuit before Stromkommutierung when switching on, however, could 153 deliver. When you turn off these time constants, however, are too large during the current commutation, although the input capacitance characteristics Ciss _{LS_sim,} is below the characteristic Ciss _{LS_mess.} That's surprising. However, the cause research remains reserved for future work. The pictures 153 and 154 could, however, provide initial evidence for this.

• 1. Sowohl für das Ein- als auch das Ausschalten muss verdeutlicht werden, dass vermutlich weder die Mess- noch die Simulationsverläufe die tatsächlichen Verhältnisse vollkommen richtig widerspiegeln. Viel wahrscheinlicher ist es, dass die tatsächlichen Verläufe irgendwo zwischen Simulation und Messung liegen.
• 2. Trotz aller Abweichungen und Fehler, die durch die einfache Modellvorstellung der Schalterkapazitäten entstehen, machen die Untersuchungen in diesem Unterkapitel deutlich, dass es zur Erzielung guter Simulationsergebnisse nicht notwendig ist, die Halbleiterphysik im Inneren der Schalter nachzubilden. Aus Messungen können Parameter bestimmt werden, die das Ergebnis dieser halbleiterphysikalischen Vorgänge sind und eine relativ exakte Parametrierung von zustandsgesteuerten Verhaltensmodellen ermöglichen.

Following the considerations of this subchapter, two further comments will be made:

• 1. It must be made clear for both switching on and off that presumably neither the measurement nor the simulation progressions fully reflect the actual conditions. It is much more likely that the actual courses are somewhere between simulation and measurement.
• 2. Despite all the deviations and errors that result from the simple modeling of the switch capacities, the investigations in this subchapter make it clear that in order to obtain good simulation results, it is not necessary to simulate the semiconductor physics inside the switches. From measurements, parameters can be determined that are the result of these semiconductor physical processes and allow a relatively accurate parameterization of state-controlled behavioral models.

4.4. Bias studies

4.4.1. Definition of characteristic values for evaluation the simulation

The parameterization of the switch model was carried out for a fast-switching low-voltage trench gate MOSFET bridge branch with very low on-resistance R _{DS (on} ) and integrated inverse diode. The evaluation of the model with the determined parameters for the bridge branch should not be done by comparing the current and voltage curves, but by comparing characteristic values. This results in a more objective comparison, which allows not only qualitative, but also quantitative statements. The switching times and switching energies specified in MOSFET data sheets are defined for ohmic load. However, the voltage and current curves with purely ohmic load are not relevant for most applications. Also result in ohmic-inductive load significantly different curves. To evaluate the simulation results of the switch model, IGBT definitions are therefore used to determine the switch-on and switch-off characteristics from the simulation and measurement data (cf. 155 - Characteristics of the transistor and states and switching conditions in the switching time macro (SZM) and the switching energy macro (SEM)) and to compare the results with each other.

Turn-on characteristics of the transistor

The time interval between the time at which the gate-source voltage V _{GS reaches} 10% of its final value and that at which the drain current I _{D has} risen to 10% of the load current is referred to as the turn-on delay time t _{d (on)} . The rise time t _r denotes the subsequent period in which the drain current increases from 10% to 90% of the load current. The sum of turn-on delay time and rise time is referred to as on-time t _on .

The turn- _on loss energy E _on is determined by integrating the turn- _on power loss P _on from the start of the turn-on time to the time when the drain current after the reverse current break becomes equal to the load current. The switch-on loss energy therefore also includes the influence of the reverse-current peak of the free-wheeling diode.

Turn-off characteristics of the transistor

The time interval between the time at which the gate-source voltage V _{GS has} dropped to 90% of its Einschaltendwertes and that at which the drain current I _{D has} fallen to 90% of the load current is referred to as off delay time t _{d (off)} , The fall time t _f is the subsequent period in which the drain current drops from 90% to 10% of the load current. The switch-off time t _off is the sum of the switch-off delay and the fall time.

The turn- _off loss energy E _off detects the losses from the start of the turn-off time to the time when the drain current I _D ≈ 0.01 * I _L.

Turn-off characteristics of the diode

The reverse recovery time t _rr is defined in this work as the time between the two diode current zero crossings. It is divided according to the figure 156 (Characteristics of the diode and states and switchover conditions in the diode characteristic data macro (DKDM)) in storage time t _s (during this period, the charge carriers are removed from the diffusion capacity.) And decay time t _f (during this time, the remaining residual charge, which mainly comes from the junction capacitance , cleared out.).

The switch-off _losses E _offD are determined during the fall time by integration of the switch-off _{power loss} P _offD .

Other characteristics are the maximum reverse _current I _RRM and the reverse _recovery charge Q _rr . The reverse recovery charge is defined as the charge that is removed from the space charge zone during the switching process by the negative current. The current increase at the zero crossing di _F / dt is determined between +/- 25% of the maximum return current.

4.4.2. Tools for evaluation of the simulation

in the As part of this work, evaluation macros have emerged that make it possible The defined characteristics are automated during the simulation to determine from the current and voltage curves. extensive Operating point examinations can be carried out very efficiently become. The evaluation macros are for documentation purposes below briefly explained.

4.4.2.1. Switching power macro (SEM)

• – Schalterstrom is,
• – Schalterspannung us,
• – Gate-Source-Spannung u_GS,
• – Laststrom i_L und
• – das Ansteuersignal X und die Ausgänge
• – Einschaltverlustenergie E_on,
• – Ausschaltverlustenergie E_off und
• – Zustand des Schaltenergiemakros str.

The switching power macro has the inputs

• - switch current is,
• - switch voltage us,
• Gate-source voltage u _GS ,
• - load current i _L and
• - The drive signal X and the outputs
• - switch-on loss energy E _on ,
• - Turn-off power E _off and
• - condition of the switching power macro str.

157 shows the structures and Umschaltbedingen the Schaltergiemakros (see also 155 ). The switch-on losses are therefore determined in states 1 and 2:

The switch-off loss energy is calculated in condition 4:

• – ugs_OGW_SEM: Modifikation der unteren I_G von E_off,
• – ugs_UGW_SEM: Modifikation der unteren I_G von E_on und
• – is_UGW_SEM: Modifikation der oberen Integrationsgrenze von E_on.

For this purpose, the driver voltage V _Dr must be specified. The integration limits (IG) can be adjusted using other definitions using the following factors:

• - ugs_OGW_SEM: modification of the lower I _G of E _off ,
• - ugs_UGW_SEM: Modification of the lower I _G of E _on and
• - is_UGW_SEM: Modification of the upper integration limit of E _on .

In State 0, the transistor is off and on in state 3, so that no shares of the switching losses are determined here. The Schaltergiemakro can also by a suitable selection the inputs sizes the losses from the simulated ones Determine chip and measured quantities and so in comparison Generate additional information for real measurement.

4.4.2.2. Switching time macro (SZM)

The Tractor has the same inputs as the switching power macro and following outputs:

• - switch-on delay time t _{d (on),}
• Risetime t _r ,
• - switch-off delay time t _{d (off)}
• - Fall time t _f and
• - Status of the switching time macro str.

158 shows the states and switching conditions of the switching time macro (cf. 155 ).

die Anstiegszeit in Zustand 2:

die Ausschaltverzögerungszeit in Zustand 4:

und die Abfallzeit in Zustand 5:

ermittelt. Dazu muss die Treiberspannung V_Dr vorgegeben werden. Die Integrationsgrenzen (IG) können bei Anwendung anderer Definitionen über die folgenden Faktoren verändert werden:

• – ugs_OGW_SZM: Modifikation der unteren IG von t_d(off),
• – ugs_UGW_SZM: Modifikation der unteren IG von t_d(on),
• – is_OGW_SZM: Modifikation der oberen IG von t_r und t_d(off) und
• – is_UGW_SZM: Modifikation der oberen IG von t_{d ( on )} und t_f bzw. Modifikation der unteren IG von t_r.

The switch-on delay time is in state 1:

the rise time in state 2:

the off-delay time in state 4:

and the fall time in state 5:

determined. For this purpose, the driver voltage V _Dr must be specified. The integration limits (IG) can be changed using other definitions using the following factors:

• - ugs_OGW_SZM: Modification of the lower IG of t _{d (off)} ,
• - ugs_UGW_SZM: Modification of the lower IG of t _{d (on)} ,
• - is_OGW_SZM: modification of the upper IG of t _r and t _{d (off)} and
• - is_UGW_SZM: Modification of the upper IG of t _{d ( on )} and t _f or modification of the lower IG of t _r .

In the states 0 and 3 are not calculated. They serve just as a transition to the next switching operation.

4.4.2.3. Diode Characteristic Macro (DKDM)

The Diode code macro has the inputs

• - switch current is,
• - switch voltage us,
• - measuring voltage vds
• - load current i _L and
• - the signal X _R and the outputs
• Storage time t _s ,
• - fall time t _f ,
• - reverse delay time t _rr ,
• Reverse current I _RRM ,
• Reverse recovery charge Q _rr ,
• - current increase at the zero crossing di / dt,
• - Off _{loss energy} E _offD or E _offDchip and
• - Status of the diode data macro str.

159 shows the states and switching conditions of the diode characteristic data macro (also see 156 ). The delta limit value i1_DGW_didt can be used to set the range in which the current increase at the zero crossing is determined. It refers to the load current i _L. However, as the range is by definition related to the reverse current peak, the ratio of I _RRM to i _{L must be} taken into account: il_DGW_didt = 0.25 · I RRM / i L · (4.42)

Z _R is a logical signal generated outside of the DKDM, with the aid of which the beginning (Z _R = 1) of the reverse current breakdown is determined. It can be generated from the states of the switch model, in which the state of the acting as a freewheeling diode switch divided by 4 and the resulting signal is used as the input of X _R. 4 is based on the fact that the switch model transitions to state 4 at the time of the reverse current demolition. Thus, at this time, X _R = 1, and the structure switching in the DKDM from state 5 to state 6 can be made.

The characteristics are determined using the following equations:

The states 0 and 1 are auxiliary states whose purpose is primarily to bring the macro, which can be switched on by an external circuit at any time, defined in the range where the diode is conducting, and then the characteristics during the subsequent Turn off the diode to determine. However, states 0 and 1 have no influence on the determination of the characteristic data. State 2 is used to determine the switch current at time t ₄ . The somewhat cumbersome determination of the current difference .DELTA.I is due to the need for revision Sample & Hold macro.

4.4.3. Evaluation of the simulation and comparison with the measured data

With the documented evaluation tools (see chapter 4.4.2 - Tools for Evaluation of the Simulation) the integration of the in 160 Crss characteristic curve shown a comprehensive operating point investigation with different gate resistors R _G and drain current strengths I _D when switching on and off performed. This characteristic is traversed from right to left during switch-on and from left to right during switch-off. It must be made clear at this point that the present work is the result of an iterative process. Thus, the characteristic curve used in the simulator for this investigation was created by a first measurement data _evaluation and was modified by sampling so that those _measured at V _DClink = 30 V, I _L = 150 A, R _G = 10 Ω and T _j = 25 ° C Switching curves are emulated as best as possible.

161 ( _Turning on the MOSFET with V _DClink = 30 V, h, = 150 A, R _G = 10 Ω and T _J = 25 ° C) and 162 ( _Turning off the MOSFET with V _DClink = _30V , I _L , = _150A , R _G = 10Ω and T _J = 25 ° C) show the results of this modification. Based on the resulting characteristic and the simulation results, the theoretical work-up followed, which is explained in detail in Chapter 3. In the subsequent interpretation of the results, these are partly taken into account, but a renewed operating point analysis taking into account the new findings is omitted for reasons of time

Referring to 161 , it must also be pointed out that the two diode time constants have been determined by time-consuming superimposition of measurement and simulation. In the subsequent evaluation, therefore, the diode time constants are determined by a procedure described in subsection 4.4.3.2 below with the aid of the evaluation macros. The time constants therefore deviate for the operating point V _DClink = 30 V, I _L , = 150 A, R _G = 10 Ω and T _J = 25 ° C from those used for these figures. The developed procedure is not only less time consuming, it also prevents the time constants from being set by endless (and meaningless) testing in such a way that the simulation progresses Be adjusted to measuring gradients.

• • Der Index „mess" steht für die tatsächlich gemessenen Verläufe. Die Messdaten sind fast ausschließlich am unteren Schalter generiert worden. Ist das nicht der Fall, wird darauf gesondert hingewiesen.
• • Die Indizes „1" und „2" beziehen sich grundsätzlich auf die Simulation der Messgrößen und die daraus ermittelten Kennwerte. „1" symbolisiert den oberen Schalter, „2" den unteren MOSFET in der Tiefsetzstellerschaltung (vgl. Abschnitt 4.2.3).
• • Bei den Schaltverlusten werden die aus den simulierten Messgrößen ermittelten Werte denen gegenübergestellt, die aus den simulierten Chipgrößen bestimmt wurden.
• Letztere erhalten dann die Indizes „chip1" und „chip2", wobei „1" bzw. „2" wieder für den oberen bzw. den unteren Schalter steht.

The in section 4.4.1. defined characteristic values were determined both from the measurement and from the simulation and are compared with the following subsections as a function of the gate resistance R _G and the drain current I _D for switching on and off. In general, the labeling of the characteristic curves in the figures applies:

• • The index "mess" stands for the actually measured gradients The measured data was almost exclusively generated at the lower switch, if not, it will be pointed out separately.
• • The indices "1" and "2" basically refer to the simulation of the measured quantities and the characteristic values determined from them. "1" symbolizes the upper switch, "2" the lower MOSFET in the step-down converter circuit (see section 4.2.3).
• • In the case of switching losses, the values determined from the simulated measured variables are compared with those determined from the simulated chip sizes.
• The latter then receive the indices "chip1" and "chip2", where "1" or "2" again stands for the upper or the lower switch.

• • E_on = 0,41 mJ zu E_off = 0,69 mJ verhält sich wie 1:1,68.
• • t_on = 202 ns zu t_off = 472 ns verhält sich wie 1:2,34.

Of particular importance in the investigations are the switch-off parameters, because these cause the greater proportion of the switching losses. To corroborate this statement, for the operating point V _DClink = 30 V, I _L = 150 A, R _G = 10 Ω and T _J = 25 ° C, the turn-on and turn-off losses and the turn-on and turn-off times are compared with each other the measured data were obtained:

• • E _on = 0.41 mJ to E _off = 0.69 mJ behaves like 1: 1.68.
• • t _on = 202 ns to t _off = 472 ns behaves like 1: 2.34.

The measurements mainly provide information about the lower switch, since the present measurement setup allows the drain current measurement only in the lower bridge section. The simulation also generates important clues about the upper switch and the losses that occur when switching in the chip. In addition, the influence of the internal inductances of the upper and lower switch on the switching energies and switching times becomes clear. The determined internal inductances are summarized again in the following table (see subsection 4.2.2.2 - Determination of inductances and resistances): Schalterinduktivität [NH] _L D1 2.0 L _S1 0.5 L _D2 3.5 L _S2 3.5

Here in the only differences are the parameterization of the two MOSFETs.

Before now in the following subsections the results of the simulative Working point examinations should be evaluated and evaluated once again - albeit philosophically - clarified that a model is an idea of reality.

• • Folgende Vereinfachungen, die bei der Nachbildung des Gatekreises vorgenommen worden sind (vgl. Abschnitt 4.1.5), haben einen relativ starken Einfluss auf die Kennwerte: – die konstante Gate-Source-Kapazität C_GS, – die Vernachlässigung der internen Gateinduktivität, – die Vernachlässigung sonstiger Induktivitäten im Gatekreis und – die unzureichende Berücksichtigung der ohmschen Widerstände im Gatekreis.
• • Außerdem könnte die in Unterkapitel 3.8. dargelegte Modellvorstellung der Kapazitäten die Wirklichkeit nicht ausreichend genau widerspiegeln und so Abweichungen verursachen.
• • Die Modellierung und Parametrierung der Messumgebung entspricht nicht genau dem tatsächlichen Messaufbau.
• • Denkbar ist grundsätzlich auch, dass die der Messmethode zugrunde liegenden Messfehler zu einer Verfälschung der Ergebnisse führen und die Wirklichkeit irgendwo zwischen der Simulation und der Messung liegt.

Within this concept there are a number of rules that relate the magnitudes of the model to observations. A good model must describe a large class of observations (eg, the output characteristic field or the on-state behavior of the diode) and allow for predictions about future observations (eg, switching characteristics). The quality of the simulation depends heavily on the modeling of the real switches, the simulation environment, and the simplifications made in this model. There will always be simplifications in the creation of a model. These different simplifications can either be in the same direction or opposite, so that they increase or decrease, or at best can cancel. In assessing the deviations of the simulated characteristic values, however, only the model concept of the reaction capacity is considered, all other sources of error are disregarded, since a correct error consideration would go beyond the scope of this work due to the complexity of the model. Nevertheless, the following list mentions a few other causes of deviations between measurement and simulation, but without claiming to be exhaustive:

• • The following simplifications made in the simulation of the gate circuit (see section 4.1.5) have a relatively strong influence on the characteristic values: - the constant gate-source capacitance C _GS , - neglecting the internal gate inductance, - the neglect of other inductances in the gate circuit and - the insufficient consideration of the ohmic resistances in the gate circuit.
• • In addition, the subchapter 3.8. The modeling of capacities presented above does not sufficiently reflect reality and thus cause deviations.
• • The modeling and parameterization of the measurement environment does not exactly match the actual measurement setup.
• • In principle it is also conceivable that the measuring errors on which the measuring method is based lead to a falsification of the results and the reality lies somewhere between the simulation and the measurement.

4.4.3.1. Evaluation of the switch-off parameters the mosfet bridge

Off times as a function of the gate resistance R _G

The pictures 163 (Comparison of the switch- _off delay time t _{d (off)} as a function of the gate resistance R _G (VD _Clink = 30 V, I _L = 150 A and T _j = 25 ° C)) and 164 (Comparison of the fall time t _f as a function of the gate resistance R _G (V _DClink = 30 V, I _L = 150 A and T _J = 25 ° C)) show the influence of the gate resistance R _G on the switch-off delay time t _{d (off)} and Fall time t _f .

• • Mit steigendem Gatewiderstand R_G steigt auch die Ausschaltverzögerungszeit t_d(off).
• • Die Ausschaltverzögerungszeit t_d(off) ist in der Simulation größer als in der Messung. Vergleicht man die t_d(off) der Messung mit t_d(off) der Simulation des unteren Schalters, so weicht die simulierte Ausschaltverzögerungszeit bis zu 20% von der dazugehörigen gemessenen Zeit ab. Die Ursache dafür liegt hauptsächlich in der verwendeten Crss-Kennlinie. Die in Abschnitt 3.5. dargelegte Ermittlung der Crss_diff-Kennlinien zeigt, dass die Kennlinie, beginnend bei negativen Drain-Gate-Spannungen, zunächst auf ein lokales Maximum ansteigt und dann absinkt, bevor sie bei größeren positiven Drain-Gate-Spannungen in Abhängigkeit vom Gatewiderstand wieder ansteigt (vgl. 47). Die für diese Untersuchung verwendete Kennlinie weist diese typische Charakteristik jedoch nicht auf. Je langsamer geschaltet wird, umso größer ist der Einfluss falscher Kennlinienbereiche auf die Simulation. Die vereinfachte Nachbildung der Kennlinie bei negativen Drain-Gate-Spannungen verursacht so die Zunahme des Simulationsfehlers von 2% bei R_G = 10 Ω auf 20% bei R_G = 100 Ω.
• • Der Einfluss der internen Sourceinduktivität auf die Ausschaltverzögerungszeit ist vernachlässigbar, da ein konstanter Drainstrom vorliegt (I_D = I_L).
• • Mit steigendem Gatewiderstand R_G steigt auch die Abfallzeit t_f.
• • Die simulierte Abfallzeit ist bei kleinen Gatewiderständen größer und bei größeren Widerständen kleiner als die der dazugehörigen Messungen. Die prozentualen Abweichungen der Abfallzeit der Simulation von der Messung liegen zwischen 0% und 18%. Die Ursachen für diese Diskrepanzen liegen in der Abhängigkeit der Crss_diff-Kennlinie vom verwendeten Gatewiderstand (vgl. 47). Bei schnelleren Schaltvorgängen ist der tatsächlich anliegende Wert der differentiellen Rückwirkungskapazität nach der Überspannungsspitze geringer als die Kennlinie, die in den Simulator eingebunden ist (vgl. Abschnitt 3.5.2.). Da die Simulation zur Vereinfachung nur von einer Abhängigkeit von der Drain-Gate-Spannung ausgeht, ist dieser Effekt in das Modell nicht integrierbar. Damit sind die spannungsabhängigen „Zeitkonstanten" im Gatekreis in diesem Bereich zu groß und verursachen dadurch die längere Abfallzeit während der Stromkommutierung. Bei großen Widerständen hingegen ändert sich die charakteristische Kennlinie und steigt bei großen, positiven Drain-Gate-Spannungen wieder an. Die im Simulator verwendete Kennlinie weist diese Charakteristik jedoch nicht auf. Damit sind die „Zeitkonstanten" in diesem Bereich zu klein und die Abfallzeit der Simulation ist geringer als in der zugehörigen Messung. Aufgrund der geschilderten Zusammenhänge kann die Simulation durch die Einbindung verschiedener C-Kennlinien für bestimmte Widerstandsbereiche verbessert werden.
• • Der Einfluss der unterschiedlichen Sourceinduktivitäten der Halbleiterbrücke durch die di_D/dt-Rückkopplung wird bei der Abfallzeit deutlich. Der Spannungsabfall über der Sourceinduktivität hebt das am Chip anliegende Gatepotential an und verzögert so das Ausschalten. Infolgedessen kann der obere Schalter viel schneller schalten als der untere, da seine Sourceinduktivität viel kleiner ist als die des unteren MOSFETs. So ist bei R_G = 10 Ω die Anstiegszeit t_r am oberen Schalter um 41% geringer als am unteren Schalter. Die Diskrepanz verringert sich bei langsamen Schaltverläufen (R_G = 100 Ω) nur auf 15%.

The following statements can be derived from the figures:

• • As the gate resistance R _G increases, the off-delay time td _{(off) also increases} .
• • The switch-off delay time t _{d (off)} is greater in the simulation than in the measurement. If the t _{d (off) of} the measurement is compared with t _{d (off) of} the simulation of the lower switch, the simulated switch-off delay time deviates up to 20% from the associated measured time. The reason for this lies mainly in the Crss characteristic used. The in section 3.5. The determination of the Crss _{diff characteristics as described} above shows that the characteristic initially increases to a local maximum starting with negative drain gate voltages and then drops before it rises again with greater positive drain gate voltages as a function of the gate resistance (cf. , 47 ). However, the characteristic used for this study does not have this typical characteristic. The slower the switch, the greater the influence of wrong characteristic areas on the simulation. The simplified simulation of the characteristic with negative drain-gate voltages thus causes the simulation error to increase from 2% at R _G = 10Ω to 20% at R _G = 100Ω.
• • The influence of the internal source inductance on the off-delay time is negligible as there is a constant drain current (I _D = I _L ).
• • As the gate resistance R _G increases, the fall time t _{f also increases} .
• • The simulated decay time is greater for small gate resistances and smaller for larger resistances than for the corresponding measurements. The percentage deviations of the fall time of the simulation from the measurement are between 0% and 18%. The causes of these discrepancies lie in the dependence of the Crss _diff characteristic on the gate resistance used (cf. 47 ). For faster switching operations, the actual value of the differential feedback capacitance after the overvoltage peak is less than the characteristic integrated in the simulator (see Section 3.5.2.). Since the simulation assumes only a dependence on the drain-gate voltage for the sake of simplicity, this effect can not be integrated into the model. This means that the voltage-dependent "time constants" in the gate circuit in this area are too large and thus cause the longer decay time during current commutation, whereas with large resistances the characteristic curve changes and rises again at high, positive drain-gate voltages However, the characteristic used does not have this characteristic, so that the "time constants" in this range are too small and the decay time of the simulation is lower than in the associated measurement. Due to the described relationships, the simulation can be improved by incorporating different C-characteristics for specific resistance ranges.
• • The influence of the different source inductances of the semiconductor bridge by the di _D / dt feedback becomes clear at the fall time. The voltage drop across the source inductance raises the gate potential applied to the chip, thus delaying the turn-off. As a result, the upper switch can switch much faster than the lower one because its source inductance is much smaller than that of the lower MOSFET. Thus, at R _G = 10 Ω, the rise time t _r at the top switch is 41% lower than at the bottom switch. The discrepancy only decreases to 15% with slow switching characteristics (R _G = 100 Ω).

Off times as a function of drain current I _D

• • Die Ausschaltverzögerungszeit t_d(off) sinkt mit steigendem Strom und ist damit abhängig davon, wo das Ausgangskennlinienfeld durchlaufen wird. So ergibt sich bei kleineren Strömen das Millerplateau bei niedrigeren Gate-Source-Spannungen als dies bei größeren Strömen der Fall ist. Demnach ist die Zeitspanne bis zum Erreichen des Millerplateaus und damit auch die Ausschaltverzögerungszeit bei kleineren Strömen länger als bei größeren Strömen.
• • Die prozentuale Abweichung der Simulation von der Messung liegt zwischen 0% und 3% und besitzt damit für die Simulation eine erstaunlich hohe Genauigkeit.
• • Bezug nehmend auf 162 ist festzustellen, dass eine Veränderung des Drainstromes kaum Einfluss auf den Bereich der negativen Drain-Gate-Spannungen der C-Kennlinie hat (vgl. Abschnitt 3.5.5.).
• • Die Wirkung der internen Induktivitäten ist vernachlässigbar, da ein konstanter Drainstrom vorliegt (I_D = I_L).
• • Mit steigendem Drainstrom verlängert sich die Abfallzeit t_f (mehr Strom kommutiert).
• • Die prozentualen Abweichungen von Messung und zugehöriger Simulation liegen zwischen 0% und 18%. Für große Ströme liegt die simulierte Abfallzeit zunächst über der der Messung, bei kleinen darunter. Ursprung dieser Diskrepanzen ist wieder die verwendete C-Kennlinie (vgl. 160 und 47). Während bei großen Stromstärken und kleinem Gatewiderstand die tatsächlich wirkende Rückwirkungskapazität nach der Spannungsspitze kleiner ist, geht dieser Effekt bei kleineren Drainstromstärken aufgrund der langsameren Stromkommutierung nach und nach verloren und die Schalterkapazität steigt nach der Spannungsspitze weiter an.
• • Die Beeinflussung des Schaltvorgangs durch die internen Sourceinduktivitäten ist sehr stark. Die Stromkommutierung am oberen Schalter ist bei großen Strömen wesentlich schneller als am unteren. So ist bei I_L = 150 A die Anstiegszeit t_r am oberen Schalter 41% geringer als am unteren Schalter. Die Diskrepanz verringert sich allerdings bei kleinen Strömen (I_L = 10 A) auf 3%, da sich bei der Kommutierung von kleineren Strömen die Drainstromanstiege verringern.

The pictures 165 (Comparison of the switch-off delay time t _{d (off)} as a function of the drain current I _D (V _DClink = 30 V, R _G = 10 Ω and T _J = 25 ° C)) and 166 (Comparison of the fall time t _f as a function of the drain current I _D (V _DClink = 30 V, R _G = 10 Ω and T _J = 25 ° C)) show the influence of the drain current I _D on the turn-off. The following findings can be deduced from the diagrams:

• • The off delay time t _{d (off)} decreases with increasing current and thus depends on where the output characteristic field is traversed. Thus, for smaller currents, the Miller plateau results at lower gate-source voltages than is the case for larger currents. Accordingly, the time to reach the Millerplateaus and thus the turn-off delay time is smaller for smaller currents than for larger currents.
• • The percentage deviation of the simulation from the measurement is between 0% and 3% and therefore has an amazingly high accuracy for the simulation.
• • Referring to 162 It should be noted that a change in the drain current has little effect on the range of the negative drain-gate voltages of the C characteristic (see Section 3.5.5.).
• • The effect of the internal inductances is negligible as there is a constant drain current (I _D = I _L ).
• • As the drain current increases, the fall time t _{f increases} (more current commutates).
• • The percentage deviations of the measurement and the associated simulation are between 0% and 18%. For large currents, the simulated decay time is initially above that of the measurement, with small below. The origin of these discrepancies is again the used C-characteristic (cf. 160 and 47 ). While at high currents and small gate resistance, the actual acting feedback capacitance is smaller after the voltage spike, this effect is gradually lost at lower drain currents due to the slower current commutation, and the switch capacitance continues to increase after the voltage spike.
• • The influence on the switching process by the internal source inductances is very strong. The current commutation at the top switch is much faster at high currents than at the bottom. Thus, at I _L = 150 A, the rise time t _r at the upper switch is 41% lower than at the lower switch. The discrepancy, however, decreases to 3% for small currents (I _L = 10 A), since the commutation of smaller currents reduces the drain current increases.

Switch-off energy as a function of the gate resistance R _G

167 (Comparison of the measured and simulated turn-off _energies E _offmess , E _off1 and E _off2 as a function of the gate resistance R _G (V _DClink = 30 V, R _G = 10 Ω and T _j = 25 ° C)) shows the turn- _{off loss energy} E _off as a function of gate resistance.

• • Die Ausschaltverlustenergie nimmt mit steigendem Gatewiderstand zu.
• • Die aus der Simulation ermittelten Ausschaltverluste sind größer als die der zugehörigen Messung. Die Diskrepanz zwischen tatsächlicher Messung und zugehöriger Simulation liegt zwischen 18% bei R_G = 10 Ω und 15% bei R_G = 100 Ω. Die Ursache dieser Abweichungen findet sich in der Verlustbestimmung von Simulation und Messung. Während die Simulation die Einschaltverluste entsprechend der Definition in Abschnitt 4.4.1. ermittelt, werden in der Messdatenauswertung die Verluste nur während der Strom- und Spannungskommutierung bestimmt. Die simulativen Einschaltverluste enthalten somit gewissermaßen noch einen Anteil an Durchlassverlusten.
• • Die Ausschaltverluste am oberen und unteren Schalter sind nahezu identisch, da in beiden Schaltern dieselben Kapazitäten umgeladen werden müssen. Das heißt natürlich nicht, dass die Verluste völlig unabhängig von den Induktivitäten sind. Vielmehr muss hier differenziert werden. Die Verluste sind sehr wohl abhängig von der gesamten Kommutierungsinduktivität. Sie scheinen jedoch relativ unabhängig davon zu sein, wie diese Induktivität im Kommutierungskreis verteilt ist. Die letzte Aussage sollte durch entsprechende Simulationen überprüft werden.
• • Die kürzere Abfallzeit des oberen Schalters verursacht größere Überspannungen am Schalter, sodass die Verluste am oberen und unteren Schalter einander letztendlich entsprechen. (Die Ausschaltverzögerungszeiten (vgl. 163) der beiden MOSFETs entsprechen sich.)

It should be noted that:

• • The turn-off loss energy increases with increasing gate resistance.
• • The switch-off losses determined from the simulation are greater than those of the associated measurement. The discrepancy between the actual measurement and the associated simulation is between 18% at R _G = 10 Ω and 15% at R _G = 100 Ω. The cause of these deviations can be found in the loss determination of simulation and measurement. During the simulation, the turn-on losses as defined in Section 4.4.1. determined, the losses are determined in the measurement data evaluation only during the current and voltage commutation. The simulative switch-on losses thus to a certain extent still contain a proportion of forward losses.
• • The turn-off losses at the top and bottom switches are nearly identical, as the same capacitances must be reloaded in both switches. Of course, this does not mean that the losses are completely independent of the inductances. Rather, it must be differentiated here. The losses are very dependent on the total commutation inductance. However, they appear to be relatively independent of how this inductance is distributed in the commutation circuit. The last statement should be checked by appropriate simulations.
• • The shorter fall time of the upper switch causes greater overvoltages on the switch, so that the losses at the top and bottom switch ultimately correspond to each other. (The switch-off delay times (cf. 163 ) of the two MOSFETs are the same.)

• • Die Ausschaltverluste am Chip sind höher als zwischen den Messpunkten, da die Spannungsabfälle über der Drain- und der Sourceinduktivität die Messspannung gegenüber der Chipspannung beim Einschalten verringern.
• • Der Unterschied zwischen Mess- und Chipspannung ist am unteren MOSFET größer als am oberen, da die Induktivitäten im unteren Schalter größer sind als im oberen. Mit steigendem Gatewiderstand verringert sich der Einfluss. So weichen am oberen Schalter die Ausschaltenergien im Chip zwischen 3% bei R_G = 10 Ω und rund 0% bei R_G = 100 Ω von den Verlusten zwischen den simulierten Messpunkten ab. Am unteren Schalter liegt die Diskrepanz zwischen 9% bei R_G = 10 Ω und 1% bei R_G = 100 Ω.

The pictures 168 (Comparison of the simulated turn-off losses of the upper MOSFET on the chip and between the drain-source terminals as a function of the gate resistance R _G (V _DClink = 30 V, R _G = 10 Ω and T _J = 25 ° C)) and 169 (Comparison of the simulated turn-off losses of the lower MOSFET on the chip and between the drain-source terminals as a function of the gate resistance R _G (V _DClink = 30 V, R _G = 10 Ω and T _J = 25 ° C)) directly _offset the simulated losses in the chip and between the measuring points. It remains to be noted:

• • The turn-off losses on the chip are higher than between the measuring points, since the voltage drops across the drain and the source inductance are the measuring voltage compared to the chip voltage at switch-on reduce.
• • The difference between the measurement voltage and the chip voltage is greater at the lower MOSFET than at the upper one, since the inductances in the lower switch are larger than in the upper one. As the gate resistance increases, the influence decreases. For example, at the upper switch, the switch-off energies in the chip deviate from 3% at R _G = 10Ω to around 0% at R _G = 100Ω from the losses between the simulated measuring points. At the lower switch the discrepancy lies between 9% at R _G = 10 Ω and 1% at R _G = 100 Ω.

Switch-off energy as a function of drain current I _D

• • Bei steigendem Drainstrom nehmen die Verluste zu.
• • Die simulierten Verluste sind höher als die zugehörigen gemessen. Die Abweichung der simulierten Verluste des unteren Schalters von den Messungen liegen zwischen 18% bei I_L = 150 A und 11% bei I_L = 10 A.

170 (Comparison of the measured and simulated turn-off _{energies Eoffmess} , E _off1 and E _off2 as a function of the drain current I _D (V _DClink = 30 V, R _G = 10 Ω and T _J = 25 ° C)) represents the dependence of the turn-off loss energy on the drain current I. _D dar. The following findings can be derived from the presentation:

• • As the drain current increases, the losses increase.
• • The simulated losses are higher than the associated measured. The deviation of the simulated losses of the lower switch from the measurements are between 18% at I _L = 150 A and 11% at I _L = 10 A.

• • Die Verluste am Chip sind höher als die zwischen den Drain- und Sourceanschlüssen ermittelten.
• • Der Einfluss der internen Induktivitäten auf die Verluste bei kleineren Drainstromstärken geht gegen Null. So sind am unteren Schalter die Verluste am Chip bei I_L = 150 A um 9% größer als und bei I_L = 10 A genauso groß wie die Einschaltverluste, die aus den Messungen ermittelt werden. Am oberen Schalter betragen die Abweichungen 3% bei I_L = 150 A und rund 0% bei I_L = 10 A.

The representations 171 (Comparison of the simulated turn-off losses of the upper MOSFET on the chip and between the drain-source terminals as a function of the drain current I _D (V _DClink = 30 V, R _G = 10 Ω and T _J = 25 ° C)) and 172 (Comparison of the simulated turn-off losses of the lower MOSFET on the chip and between the drain-source terminals as a function of the drain current I _D (V _DClink = 30 V, R _G = 10 Ω and T _J = 25 ° C)) are the influence of the internal Switch inductances on the switching losses dar. It is noted:

• • The losses on the chip are higher than those determined between the drain and source connections.
• • The influence of the internal inductances on the losses at lower drain currents goes to zero. At the lower switch, the losses on the chip at I _L = 150 A are 9% greater than and at I _L = 10 A are the same as the switch-on losses, which are determined from the measurements. At the upper switch, the deviations are 3% at I _L = 150 A and around 0% at I _L = 10 A.

• 1. Die Simulationsergebnisse der Ausschaltverzögerungszeit t_d(off) lassen sich durch eine Korrektur der verwendeten Rückwirkungskapazitätskennlinie bei negativen Drain-Gate-Spannungen verbessern.
• 2. Die Nachbildung der Rückwirkungskapazitätskennlinie beeinflusst auch die Simulation der Abfallzeit t_f. Es ist zu erwägen, verschiedene Kennlinien für bestimmte Widerstandsbereiche in den Simulator zu integrieren (vgl. Abschnitt 3.5.2.).
• 3. Die Simulation der Ausschaltverluste E_off liefert Informationen zu den Verlusten, die am Chip entstehen. Diese sind höher als die Verluste, die aus den simulierten Messungen ermittelt werden.
• 4. Die prozentualen Abweichungen der simulierten Verluste im Chip und zwischen den Messpunkten lassen sich auf die tatsächlichen Messungen übertragen. (Die Verläufe der Kennlinien Eoff₁ und Eoff_chip1 bzw. Eoff₂ und Eoff_chip2 sind ähnlich. Unter Berücksichtigung der Abweichungen zwischen Eoff_mess und Eoff₂ können damit die tatsächlichen Chipverluste abgeschätzt werden.)
• 5. Die Verläufe der simulierten Ausschaltzeiten und -verlustenergien in Abhängigkeit von R_G und I_D sind den Messverläufen sehr ähnlich. Die Abweichungen zwischen Simulation und dazugehöriger Messung betragen maximal 20%. Diese Genauigkeit ist für eine Simulation ausreichend und steht für die Stabilität des Modells.
• 6. Generell ist eine Verbesserung der Simulationsergebnisse durch Umsetzung der Erkenntnisse aus Abschnitt 3.5. zu erwarten.

The following summary is given for the switch-off times and losses:

• 1. The simulation results of the off delay time t _{d (off)} can be improved by correcting the used feedback capacitance characteristic at negative drain gate voltages.
• 2. The simulation of the feedback capacitance characteristic also influences the simulation of the decay time t _f . It should be considered to integrate different characteristics for certain resistance ranges into the simulator (see section 3.5.2.).
• 3. The simulation of the switch- _off losses E _off provides information about the losses that occur on the chip. These are higher than the losses that are determined from the simulated measurements.
• 4. The percentage deviations of the simulated losses in the chip and between the measuring points can be transferred to the actual measurements. (The paths of the characteristics Eoff ₁ and Eoff _Chip1 or Eoff ₂ and Eoff _Chip2 are similar. Taking into account the deviations between _measured and Eoff Eoff _2, the actual chip losses can be estimated with it.)
• 5. The curves of the simulated switch-off times and energy losses as a function of R _G and I _D are very similar to the measurement curves. The deviations between simulation and associated measurement amount to a maximum of 20%. This accuracy is sufficient for a simulation and represents the stability of the model.
• 6. In general, an improvement of the simulation results by implementing the findings from section 3.5. expected.

4.4.3.2. Setting the diode time constants

• • Wird der untere Schalter als Freilaufdiode verwendet, so wird zunächst mit T_d die Rückstromspitze I_RRM2 der Diode D2 so eingestellt, dass sie der Rückstromspitze I_RRMmess der Messung entspricht. Danach wird T, so angeglichen, dass die Diodenabfallzeiten von Simulation und Messung übereinstimmen.
• • Wird der obere Schalter als Freilaufdiode verwendet, muss die Einstellung der Parameter T_d und T_rr entsprechend durch Abgleich des Drainstromverlaufs des unteren MOSFETs erfolgen, da der Strom durch den oberen MOSFET bzw. seine Inversdiode mit dem vorliegenden Messaufbau nicht gemessen werden kann.

The reverse recovery behavior of the inverse diode is simulated by means of two delay elements and their time constants. With the time constant T _d the height of the reverse current peak is set and with T _rr the diode fall time. This relatively primitive diode model requires a complex setting of the diode time constants by a comparison of simulation and measurements for each operating point investigated:

• • If the lower switch is used as a freewheeling diode, the reverse current _peak I _{RRM2 of} the diode D2 is first adjusted with T _d so that it corresponds to the reverse current _peak I _{RRMmess of} the measurement. Thereafter, T is adjusted so that the diode fall times of simulation and measurement match.
• • If the upper switch is used as a freewheeling diode, the adjustment of the parameters T _d and T _rr must be done by adjusting the drain current characteristic of the lower MOSFET, as the current through the upper MOSFET or its inverse diode can not be measured with this test setup.

The resulting parameters are in 173 (Diode time constant Td as a function of the gate resistance (V _DClink = 30 V, I _L = 150 A and T _J = 25 ° C)), 174 (Diode time constant Td as a function of the drain current (V _DClink = 30 V, I _L = 150 A and T _J = 25 ° C)), 175 (Diode time constant T _rr as a function of the gate resistance (V _DClink = 30 V, I _L = 15 A and T _J = 25 ° C)) and 176 (Diode time constant T _rr as a function of the drain current (V _DClink = 30 V, R _G = 10 Ω and T _J = 25 ° C)) as a function of gate resistance and drain current shown. An analysis of the results is waived. However, the figures in this subsection provide a good basis for further analysis, which could eventually lead to a new diode model that does not require the user to set time constants.

Since the subsequent evaluation of the switch-on parameters shows that the reverse-recovery behavior of the diode can be reproduced by T _d and T _rr , the question arises as to whether a further mathematical relationship can be derived from further measurements and analyzes. This is how the pictures show 177 (Reverse recovery time of the diode D2 as a function of the current increase), 178 (Maximum reverse current of the diode D2 as a function of the current increase) and 179 (Reverse recovery charge of the diode D2 as a function of the current increase) the results of the evaluation of the diode measurement in the lower bridge branch. (Comparable diagrams for the upper switch can not be generated with the existing test setup.) These diagrams are also presented here only, without the resulting statements being derived for the diode model. They merely serve to stimulate further investigations.

• • T_d scheint vor allem vom Stromanstieg abhängig zu sein (vgl. 178).
• • Die Herleitung eines Zusammenhangs für T_rr. ist wesentlich komplizierter. An dieser Stelle muss darauf hingewiesen werden, dass der Parameter T_rr sich nur auf die Abfallzeit der Diode bezieht, t_rr in der Darstellung 177 jedoch auf die gesamte Sperrverzögerungszeit. Es gilt durch Messungen und Simulation zu untersuchen, inwiefern T_rr im Simulator nur vom reinen Rückstromabriss abhängt – der die verbleibende Restladung ausräumt, welche hauptsächlich aus der Sperrschichtkapazität stammt – oder ob auch die Aufsteuereffekte und die Entlastung durch die Schalterkapazitäten einen Einfluss auf diesen Parameter haben. Durch Messungen, die durch Anlegen einer negativen Gatespannung bzw. durch Verwendung kleiner Gatewiderstände im Gatekreis des als Diode betriebenen MOSFETs gezielt das Aufsteuern verhindern, können zumindest die Aufsteuereffekte ausgeschlossen werden. Es besteht jedoch die Gefahr, dass die Diode durch solche Messungen zerstört wird (vgl. 2.2.3.).

If a relationship should be derivable from these representations, which can be integrated into the simulator, then the user could be spared the time-consuming setting of the time constants. However, identifying such a relationship is by no means trivial and beyond the scope of this paper. Below are some (incomplete) hints given, what to consider:

• • T _d seems to depend mainly on the current increase (cf. 178 ).
• • The derivation of a connection for T _rr . is much more complicated. It should be noted at this point that the parameter T _rr refers only to the decay time of the diode, t _rr in the illustration 177 however, on the total reverse delay time. By means of measurements and simulation, it is necessary to investigate to what extent T _rr in the simulator depends only on pure reverse current breakdown - which removes the remaining residual charge, which mainly derives from the junction capacitance - or if the control effects and the discharge through the switch capacities also have an influence on this parameter , At least the control effects can be ruled out by measurements which selectively prevent the triggering by applying a negative gate voltage or by using small gate resistances in the gate circuit of the diode-operated MOSFET. However, there is a risk that the diode will be destroyed by such measurements (see 2.2.3.).

4.4.3.3. Evaluation of the switch-on parameters the mosfet bridge

Switch-on times as a function of gate resistance R _G

The pictures 180 (Comparison of the switch- _on delay time t _{d (on)} as a function of the gate resistance R _G (V _DClink = 30 V, I _L = 150 A and T _J = 25 ° C)) and 181 (Comparison of the rise time t _r as a function of the gate resistance R _G (V _DClink = 30 V, I _L = 150 A and T _J = 25 ° C)) show the influence of the gate resistance R _G on the switch-on delay time t _{d (on} ) and the Rise time t _r .

• • Mit steigendem Gatewiderstand R_G steigt auch die Einschaltverzögerungszeit t_d(on).
• • Die Einschaltverzögerungszeit t_d(on) ist in der Simulation kleiner als in der Messung. Vergleicht man die td(on) der Messung mit t_d(on) der Simulation des unteren Schalters, so weicht die simulierte Zeit zwischen 30% und 32% von der dazugehörigen gemessenen Zeit ab. Hauptgrund für diese starke Abweichung ist wieder die Modellierung der Crss-Kennlinie. Die Crss-Kennlinie in 160 unterscheidet sich bei positiven Drain-Gate-Spannungen von den Crss_diff-Kennlinien, die in Abschnitt 3.5. bestimmt werden (vgl. 47). So fehlt beispielsweise das Ansteigen der differentiellen Kapazität bei größeren positiven Drain-Gate-Spannungen. Somit ist die Rückwirkungskapazität zu Beginn der Kommutierung zu klein und damit auch die spannungsabhängigen „Zeitkonstanten" im Gatekreis.
• • Der Einfluss der internen Sourceinduktivität auf die Einschaltverzögerungszeit ist vernachlässigbar.
• • Mit steigendem Gatewiderstand R_G steigt auch die Anstiegszeit t_r.
• • Die Anstiegszeit t_r ist in der Simulation kleiner als in der Messung. Die prozentuale Abweichung der Simulation von der Messung steigt von 1% bei R_G = 10 Ω Ohm auf 25% bei R_G = 100 Ω an. Der Grund für diese stark ansteigende Abweichung ist wieder vorrangig in der verwendeten C-Kennlinie zu finden. Das typische Ansteigen bei größeren positiven Drain-Gate-Spannungen bei größeren Gatewiderständen ist in der verwendeten Kennlinie nicht enthalten (vgl. Abschnitt 3.5.3.). Dadurch entstehen vor allem zu Beginn der Stromkommutierung kleinere „Zeitkonstanten" im Gatekreis.
• • Der Einfluss der unterschiedlichen Sourceinduktivitäten der Halbleiterbrücke wird bei der Anstiegszeit bzw. der Stromkommutierung deutlich. Die Rückkopplung über die Sourceinduktivität verlangsamt die Stromkommutierung, da das am Chip anliegende Gatepotential durch die Spannung über der internen Sourceinduktivität verringert wird. Deshalb schaltet der obere MOSFET mit L_S1 = 0,5 nH schneller als der untere mit L_S2 = 3,5 nH. Die Anstiegszeit t_r ist bei R_G = 10 Ω am oberen Schalter um 20% geringer als am unteren Schalter. Der Einfluss der Induktivität verringert die Anstiegszeit auch bei R_G = 100 Ω noch um 11%.

The following statements can be derived from the figures:

• • As the gate resistance R _G increases, the on-delay time td _{(on) also increases} .
• • The switch-on delay time t _{d (on)} is smaller in the simulation than in the measurement. Comparing the td (on) of the measurement with t _{d (on) of} the simulation of the lower switch, the simulated time deviates between 30% and 32% of the associated measured time. The main reason for this strong deviation is again the modeling of the Crss characteristic. The Crss characteristic in 160 differs for positive drain-gate voltages from the Crss _diff characteristics, which are discussed in Section 3.5. be determined (cf. 47 ). For example, there is a lack of increase in differential capacitance at larger positive drain-to-gate voltages. Thus, the feedback capacitance at the beginning of the commutation is too small and thus also the voltage-dependent "time constants" in the gate circuit.
• • The influence of the internal source inductance on the turn-on delay time is negligible.
• • As the gate resistance R _G increases, the rise time t _r also increases.
• • The rise time t _r is smaller in the simulation than in the measurement. The percentage deviation of the simulation from the measurement increases from 1% at R _G = 10Ω ohms to 25% at R _G = 100Ω. The reason for this strongly increasing deviation is again to be found primarily in the C-characteristic curve used. The typical The increase in larger positive drain-gate voltages for larger gate resistances is not included in the characteristic curve used (see Section 3.5.3.). This creates smaller "time constants" in the gate circuit, especially at the beginning of the current commutation.
• • The influence of the different source inductances of the semiconductor bridge becomes clear during the rise time or the current commutation. The feedback via the source inductance slows the current commutation because the on-chip gate potential is reduced by the voltage across the internal source inductance. Therefore, the upper MOSFET switches with L _S1 = 0.5 nH faster than the lower one with L _S2 = 3.5 nH. The rise time t _r is 20% lower at R _G = 10 Ω at the upper switch than at the lower switch. The influence of the inductance reduces the rise time even at R _G = 100 Ω by 11%.

Switch-on times as a function of the drain current I _D

The pictures 182 (Comparison of the switch- _on delay time t _{d (on)} as a function of the drain current I _D (V _DClink = 30 V, R _G = 10 Ω and T _j = 25 ° C)) and 183 (Comparison of the rise time t _r as a function of the drain current I _D (V _{DC link} = 30 V, R _G = 10 Ω and T _J = 25 ° C)) show the influence of the drain current I _D on the turn-on delay time t _{d (on)} and Rise time t _r .

• • Mit steigendem Drainstrom I_D steigt auch die Einschaltverzögerungszeit t_d(on). Entsprechend dem typischen Durchlaufen des Ausgangskennlinienfeldes, stellt sich das so genannte Millerplateau bei höheren Gatespannungen ein. Daher nimmt auch die Einschaltverzögerungszeit bei größeren Drainströmen zu.
• • Die Einschaltverzögerungszeit t_d(on) ist in der Simulation kleiner als in der Messung. Vergleicht man die t_d(on) der Messung mit t_d(on) der Simulation des unteren Schalters, so weicht die simulierte Zeit wieder zwischen 30% und 32% von der dazugehörigen gemessenen Zeit ab. Ursachen dafür sind an der Stelle aufgeführt, wo die Abhängigkeit der Einschaltverzögerungszeit vom Gatewiderstand behandelt wird.
• • Der Einfluss der internen Sourceinduktivität auf die Einschaltverzögerungszeit ist vernachlässigbar.
• • Mit steigendem Drainstrom I_D steigt auch die Anstiegszeit t_r.
• • Die Anstiegszeiten t_mess und t_r2 sind nahezu identisch. Die prozentualen Abweichungen der Simulation von der Messung liegen zwischen 1% und 7%. Das zeigt, dass die Anpassung der Crss-Kennlinie an einen Arbeitspunkt (V_DClink = 30 V, R_G = 10 Ω, I_L = 150 A und T_J = 25°C) bei Veränderung des Drainstromes unter sonst gleichen Bedingungen bei der Abfallzeit zu erstaunlich guten Simulationsergebnissen fuhrt.
• • Der Einfluss der unterschiedlichen Sourceinduktivitäten der Halbleiterbrücke wird auch in 182 deutlich. Allerdings geht dieser Effekt aufgrund des Abnehmens der Stromanstiege bei kleinen Strömen immer mehr verloren. Während die Anstiegszeit t_r bei I_D = 150 A am oberen Schalter noch 20% geringer ist als am unteren Schalter, beträgt die Verkürzung der Anstiegszeit bei I_D = 10 A nur noch 5%.

The following findings can be derived from the two diagrams:

• • With increasing drain current I _D , the turn-on delay time t _{d (on) also increases} . According to the typical traversing of the output characteristic field, the so-called Miller plateau adjusts itself at higher gate voltages. Therefore, the turn-on delay time increases with larger drain currents.
• • The switch-on delay time t _{d (on)} is smaller in the simulation than in the measurement. If the t _{d (on} ) of the measurement is compared with t _{d (on) of} the simulation of the lower switch, the simulated time again deviates between 30% and 32% of the associated measured time. Causes for this are listed at the point where the dependence of the turn-on delay time is treated by the gate resistance.
• • The influence of the internal source inductance on the turn-on delay time is negligible.
• • As the drain current I _D increases, the rise time t _r also increases.
• • The rise times t _mess and t _r2 are almost identical. The percentage deviations of the simulation from the measurement are between 1% and 7%. This shows that the adaptation of the Crss characteristic to an operating point (V _DClink = 30 V, R _G = 10 Ω, I _L = 150 A and T _J = 25 ° C) changes the drain current under otherwise identical conditions at the fall time leads to amazingly good simulation results.
• • The influence of the different source inductances of the semiconductor bridge is also shown in 182 clear. However, this effect is lost more and more due to the decrease in current increases at low currents. While the rise time t _r at I _D = 150 A at the upper switch is still 20% lower than at the lower switch, the reduction of the rise time at I _D = 10 A is only 5%.

Turn on energy as a function of the gate resistance R _G

• • Während am unteren Schalter die Einschaltverluste E_on mit Zunahme des Gatewiderstandes R_G im betrachteten Bereich immer weiter ansteigen, gehen die Verluste am oberen Schalter ab ca. R_G = 80 Ω wieder leicht zurück.
• • Die aus den Messungen ermittelten Einschaltverluste sind höher als die der zugehörigen Simulation. Bewirkt wird dies vor allem durch die gegenüber der Messung verkürzten Anstiegszeiten und die dadurch entstehende Spannungsentlastung.
• • Die Diskrepanz zwischen Messung und zugehöriger Simulation beträgt bei R_G = 10 Ω 12%, steigt auf bis zu 28% bei R_G = 75 Ω und fällt dann bei R_G = 100 Ω wieder auf 23%. In Anbetracht der Tatsache, dass die verwendete C-Kennlinie einige Mängel aufweist, sind diese Simulationsergebnisse erstaunlich gut.
• • Die Einschaltverluste am oberen Schalter sind signifikant kleiner als am unteren Schalter. Zu begründen ist dies mit den kleineren Anstiegszeiten (vgl. 181), die sich durch die unterschiedlichen Induktivitätsverhältnisse an den Schaltern ergeben.

184 (Comparison of the measured and simulated switch-on energies E _onmess , E _on1 and E _on2 as a function of the gate resistance R _G (V _DClink = 30 V, I _L = 150 A and T _J = 25 ° C)) shows the influence of the gate resistance R _G the switch-on losses E _on . The following statements can be derived:

• • While the switch- _on losses E _on at the lower switch continue to rise in the considered range with the increase of the gate resistance R _G , the losses at the upper switch go back slightly from approx. R _G = 80 Ω.
• • The starting losses determined from the measurements are higher than those of the associated simulation. This is mainly due to the shortened rise times compared to the measurement and the resulting stress relief.
• • The discrepancy between the measurement and the associated simulation is 12% at R _G = 10 Ω, increases up to 28% at R _G = 75 Ω and then drops back to 23% at R _G = 100 Ω. Given the fact that the C-characteristic used has some shortcomings, these simulation results are surprisingly good.
• • The switch-on losses at the upper switch are significantly smaller than at the lower switch. This is justified by the smaller rise times (cf. 181 ), which result from the different inductance ratios at the switches.

The pictures 185 ( _{Measurement curves} (V _Dr1 = 0/10 V, I _L = 150 A, R _G = 10 Ω, V _DClink = 30 V), CH1: diode current I _Diode2 , CH2: drain-source voltage V _DS2 , CH3: drain Source voltage V _DS1 , CH4: half-bridge voltage V _D1S2 ), 186 ( _{Measurement curves} (V _Dr2 = 0/10 V, I _L = 150 A, R _G = 10 Ω, V _DClink = 30 V), CH1: drain current I _D2 , CH2: drain-source voltage V _DS2 , CH3: drain Source voltage V _DS1 , CH4: half-bridge voltage V _D1S2 ), 187 (Simulation _curves at the active MOSFET 1 (V _Dr1 = 10 V, I _L = 150 A, R _G = 10 Ω and V _{DC link} = 30 V)), 188 (Simulation _curves at the active MOSFET 2 (V _Dr2 = 10 V, I _L = 150 A, R _G = 10 Ω and V _DClink = 30 V)), 189 (Simulation _curves at passive diode 2 (V _Dr1 = 10 V, I _L = 150 A, R _G = 10 Ω and V _{DC link} = 30 V)) and 190 (Simulation _curves at passive diode 1 (V _Dr2 = 10 V, I _L = 150 A, R _G = 10 Ω and V _{DC link} = 30 V)) provide a comparison between the switching characteristics of the MOSFET and the associated diode when driving the lower or They illustrate the influence of the internal inductances on the Aufsteuerverhalten the operated as a freewheeling diode switch. The pictures 185 and 186 show measurements to the simulation courses, which in the pictures 187 . 188 . 189 and 190 are shown. The measurement procedure is described in subsection 4.4.2.2. described. First, it is noticeable that the simulation results are confirmed by the measurements. Considering 160 and the one in the pictures 189 and 190 shown drain-gate voltage of the operated as a freewheeling diode MOSFETs is clear that at the time of the reverse current tear at the operated as a freewheeling diode switches different drain gate voltages applied (see. 191 ). Therefore, the reaction capacity of the upper MOSFET at the time of the reverse current cutoff is larger than the lower one. Thus, more current flows into the gate circuit via the upper feedback capacitance causing a larger voltage drop across the gate resistor. For this reason, the upper transistor controls much more than the lower one.

• • Ab bzw. bis V_F ≈ 0,5 V fließt ein Diodenstrom.
• • V_L1 ≈ 0,33 V bzw. V_L1 – V_F ≈ –0,23V (V_Dr2 = 10 V, I_L = 150 A, R_G = 10 Ω, V_DClink = 30 V)
• • V_L2 ≈ 3,50 V bzw. V_L2 – V_F ≈ 3,00 V (V_Dr1 = 10 V, I_L = 150 A, R_G = 10 Ω, V_DClink = 30 V)

In addition, at the time of the reverse current break, the voltage V _{LS changes} its sign. For example, the source inductance influences the switching-on of the switches indirectly via the drain-gate voltage and directly via V _LS in the reverse-current breakdown. It also becomes clear that the influence of the drain-gate voltage by the source inductance plays a greater role than the di _D / dt feedback through the source inductance, since L _S2 = 3.5 nH >> L _S1 = 0.5 nH , This is reflected accordingly in the switch-on losses (cf. 184 ) contrary. Referring to 191 (Voltage ratios at the operated as a freewheeling diode MOSFET during the current commutation of diode to MOSFET), the magnitudes of the voltages V _F and V _L are listed as an example, to illustrate how sensitive the Aufsteuerverhalten to these effects:

• • From or to V _F ≈ 0.5 V, a diode current flows.
• V _L1 ≈ 0.33 V or V _L1 - V _F ≈ -0.23 V (V _Dr2 = 10 V, I _L = 150 A, R _G = 10 Ω, V _{DC link} = 30 V)
• V _L2 ≈ 3.50 V or V _L2 - V _F ≈ 3.00 V (V _Dr1 = 10 V, I _L = 150 A, R _G = 10 Ω, V _{DC link} = 30 V)

Looking now at the characteristic in 160 , it quickly becomes clear that the difference between the effective reaction capacities is very large. However, this analysis does not yet explain why the switch-on losses at the upper switch slightly decrease with higher gate resistances. Looking at the pictures 180 and 181 , it is found that both the turn-on delay time and the rise time of both switches increase with increasing gate resistance. Since the only difference between the two switches lies in the internal inductances, the falling of the turn-on loss energy at very high gate resistances at the upper switch would also have to be justified by this.

A comparison of the simulation of the switch-on operations of the upper and lower MOSFETs at R _G = 100 Ω shows that the upper MOSFET operated as free-wheeling diode opens much longer than the lower one (see also the curves with R _G = 10 Ω). 192 Simulation _curves at the active MOSFET 1 (V _Dr1 = 10 V, I _L = 150 A, R _G = 100 Ω, V _{DC link} = 30 V), 193 Simulation _curves at the active MOSFET 2 (V _Dr2 = 10 V, I _L = 150 A, R _G = 100 Ω, V _{DC link} = 30 V), 194 - Simulation _curves at passive diode 2 (V _Dr1 = 10 V, I _L = 150 A, R _G = 100 Ω, VDClink = 30 V) and 195 - Simulation _curves at passive diode 1 (V _Dr2 = 10V, I _L = 150 A, R _G = 100 Ω, V _{DC link} = 30 V)). Thus, the losses at the bottom switch increase despite the decreasing reverse current peak depending on the gate resistance.

At The present half bridge was also diode measurements performed for the inverse diode of the lower switch. For the upper switch, however, this is often the case mentioned, not possible in the present test setup. However, it is likely that the upper diode is similar behaves.

The representations 196 (Dependency of the diode current increase of the inverse diode 2 at the zero crossing _Diode2 dI / dt of the gate resistance R _G) and 197 (Dependence of the reverse _{recovery time of} the inverse diode 2 on the current increase dI _Diode2 / dt) of the measurement data of the lower MOSFET (I _L = 150 A, V _DClink = 30 V, T _j = 125 ° C) then provides the reason for reducing the turn-on losses at higher gate resistors. As expected, the diode current increase in the current zero crossing decreases continuously as the gate resistance R _G increases (cf. 197 ). The characteristic curve of the reverse recovery time trr (dI _diode / dt) has a direct influence on the switching losses in the diode and in the MOSFET (cf. 197 ). Since the lower diode does not open as much as the upper one, there is no short circuit in the bridge branch, which causes the losses in the upper MOSFET to continue to rise, even with large gate resistances, thus causing a slight decrease in switching losses at high gate resistances. In the context of the described Un Investigations have been shown with a simulation that for the present measurement setup, the di _diode / dt feedback through the source inductance has a negligible effect on the gate voltage applied to the chip and thus on the duration of the open-loop. Thus, the override is almost exclusively dependent on the acting feedback capacity during the reverse current stall. However, this is indirectly influenced by the current inductance ratios, the resulting feedback to the gate circuit, and the resultant drain-gate voltage at power up (1 / L ~ di _L / dt and L ~ v _L ). In this context, it should also be pointed out that tensions over capacity can not jump. The "jumps" in the pictures 185 to 195 have finite climbs. These are determined by the effective switching capacities in the reverse current break (1 / C ~ dv _c / dt and C ~ i _c ) and thus directly determine the open-loop behavior of the MOSFETs.

• • Die Einschaltverluste am Chip sind geringer als zwischen den Messpunkten, da die Spannungsabfälle über der Drain- und der Sourceinduktivität die Messspannung gegenüber der Chipspannung beim Einschalten erhöhen.
• • Da die Induktivitäten im unteren Schalter größer sind als im oberen, ist der Unterschied zwischen Mess- und Chipspannung am unteren MOSFET größer als am oberen. So weichen am oberen Schalter die Einschaltverluste im Chip zwischen 21% bei R_G = 10 Ω und 3% bei R_G = 100 Ω von den Verlusten zwischen den Messpunkten ab. Am unteren Schalter liegt die Diskrepanz zwischen 23% bei R_G = 10 Ω und 7% bei R_G = 100 Ω.

The pictures 198 (Comparison of the simulated turn-on losses of the upper MOSFET on the chip and between the drain-source terminals as a function of the gate resistance R _G (with V _DClink = 30 V, I _L = 150 A and T _J = 25 ° C)) and 199 (Comparison of the simulated turn-on losses of the lower MOSFET on the chip and between the drain-source terminals as a function of the gate resistance R _G (with V _DClink = 30 V, I _L = 150 A and T _J = 25 ° C)) simulated drain-source voltage and drain current profile or the simulated Chipspannungs- and channel current waveform determined switch-on for both switches. Taking into account the scaling of the diagrams, the following statements were derived from the diagrams:

• • The turn-on losses on the chip are lower than between the measuring points, since the voltage drops across the drain and the source inductance increase the measuring voltage compared to the chip voltage at switch-on.
• • Since the inductances in the lower switch are larger than the upper ones, the difference between the measurement voltage and the chip voltage is greater at the lower MOSFET than at the upper one. For example, the switch-on losses in the chip between 21% at R _G = 10Ω and 3% at R _G = 100Ω deviate from the losses between the measuring points at the upper switch. At the lower switch the discrepancy is between 23% at R _G = 10 Ω and 7% at R _G = 100 Ω.

Turning energy as a function of the drain current I _D

• • Bei steigendem Drainstrom nehmen die Verluste zu.
• • Die simulierten Verluste sind geringer als die zugehörigen gemessenen. Die Abweichungen der simulierten Verluste des unteren Schalters von den Messungen liegen zwischen 13% bei I_L = 150 A und 26% bei I_L = 10 A. Die notwendigen Verbesserungen der Crss-Kennlinie wurden bereits bei den Einschaltzeiten angedeutet.

The following diagram 200 (Comparison of the measured and simulated switch-on energies E _onmess , E _on1 and E _on2 as a function of the drain current I _D (V _DClink = 30 V, R _G = 10 Ω and T _J = 25 ° C)) sets the dependence of the switch-on loss energy on the drain current I. _D dar. The following findings can be derived from the presentation:

• • As the drain current increases, the losses increase.
• • The simulated losses are lower than the corresponding measured ones. The deviations of the simulated losses of the lower switch from the measurements are between 13% at I _L = 150 A and 26% at I _L = 10 A. The necessary improvements of the Crss characteristic were already indicated at the switch-on times.

• • Die Verluste am Chip sind geringer als die zwischen den Drain- und Sourceanschlüssen ermittelten.
• • Der Einfluss der internen Induktivitäten auf die Verluste bei kleineren Drainstromstärken sinkt. So sind am unteren Schalter die Verluste am Chip um 23% bei I_L = 150 A und bei I_L = 10 A nur um 4% geringer als die Einschaltverluste, die aus den Messungen ermittelt werden. Am oberen Schalter betragen die Abweichungen bei I_L = 150 A 20% und 0% bei I_L = 10 A.

The representations 201 (Comparison of the simulated turn-on losses of the upper MOSFET on the chip and between the drain-source terminals as a function of the drain current I _D (V _DClink = 30 V, R _G = 10 Ω and T _J = 25 ° C)) and 202 (Comparison of the simulated turn-on losses of the lower MOSFET on the chip and between the drain-source terminals as a function of the drain current I _D (V _DClink = 30 V, R _G = 10 Ω and T _J = 25 ° C)) are the influence of the internal Switch inductances on the switching losses. It can be stated that:

• • The losses on the chip are lower than those determined between the drain and source connections.
• • The influence of the internal inductances on the losses at lower drain currents decreases. At the lower switch, for example, the losses on the chip are 23% lower at I _L = 150 A and at I _L = 10 A, only 4% lower than the switch-on losses, which are determined from the measurements. At the upper switch, the deviations at I _L = 150 A are 20% and 0% at I _L = 10 A.

• 1. Die Simulationsergebnisse der Einschaltverzögerungszeit t_d(on) und damit auch der Einschaltenergie E_on lassen sich durch eine Korrektur der Rückwirkungskapazitätskennlinie bei größeren Drain-Gate-Spannungen verbessern (vgl. 160 und 47).
• 2. Die Nachbildung der Rückwirkungskapazitätskennlinie beeinflusst die Simulationsqualität der Anstiegszeit t_r in Abhängigkeit vom Gatewiderstand R_G viel stärker als in Abhängigkeit vom Drainstrom I_D. Es ist zu erwägen, verschiedene Kennlinien für bestimmte Widerstandsbereiche in den Simulator zu integrieren (vgl. Abschnitt 3.5.2), um auch eine genauere Ermittlung der Einschaltverluste E_on zu ermöglichen.
• 3. Die Simulation der Einschaltverluste E_on liefert nicht nur zusätzliche Informationen zum oberen Schalter, sondern auch über die Verluste, die am Chip entstehen. Diese sind geringer als die Verluste, die aus den Messungen ermittelt werden.
• 4. Die Verluste des oberen Schalters weichen von den Verlusten des unteren Schalters beim Einschalten stärker ab als beim Ausschalten. Es werden zwar dieselben Kapazitäten umgeladen, jedoch entstehen durch das unterschiedliche Aufsteuerverhalten der Inversdioden unterschiedliche Verluste.
• 5. Die Verläufe der simulierten Einschaltzeiten und -verlustenergien in Abhängigkeit von R_G und I_D sind den Messverläufen ähnlich – in der Simulation entsteht entweder ein anderer Offset oder ein anderer Anstieg der Kennlinien. Die Abweichungen sind demnach kalkulierbar. Trotz der Abweichungen ist das Schaltermodell sehr stabil.
• 6. Eine Verbesserung der Simulationsergebnisse durch Umsetzung der Erkenntnisse aus Abschnitt 3.5. ist zu erwarten.
• 7. Nach der Untersuchung der Einschaltparameter ist aufgrund der Ähnlichkeit der ermittelten Kennlinien zu vermuten, dass die Simulation des oberen Schalters ähnliche Diskrepanzen zur Messung hat wie der untere. Mit dem vorliegenden Messaufbau ist diese Untersuchung jedoch nicht möglich.

For the simulation of the switch-on times and switch-on losses can be summarized:

• 1. The simulation results of the switch-on delay time t _{d (on)} and thus also the turn-on energy E _on can be improved by correcting the feedback capacitance characteristic at higher drain-gate voltages (cf. 160 and 47 ).
• 2. The simulation of the feedback capacitance characteristic influences the simulation quality of the rise time t _r as a function of the gate resistance R _G much more than in dependence on the drain current I _D. It should be considered to integrate different characteristic curves for certain resistance ranges into the simulator (see section 3.5.2) in order to enable a more precise determination of the switch-on losses E _on .
• 3. The simulation of the switch- _on losses E _on not only provides additional information about the upper switch, but also about the losses that occur on the chip. These are lower than the losses that are determined from the measurements.
• 4. The losses of the upper switch deviate more from the losses of the lower switch when switching on than when switching off. Although the same capacities are reloaded, however, different losses occur due to the different triggering behavior of the inverse diodes.
• 5. The curves of the simulated switch-on times and energy losses as a function of R _G and I _D are similar to the measuring curves - in the simulation, either a different offset or a different slope of the characteristic curves arises. The deviations are therefore calculable. Despite the deviations, the switch model is very stable.
• 6. An improvement of the simulation results by implementing the findings from section 3.5. is to be expected.
• 7. After examining the switch-on parameters, it is to be assumed on the basis of the similarity of the determined characteristic curves that the simulation of the upper switch has similar discrepancies to the measurement as the lower one. However, this examination is not possible with the present test setup.

• – Betrachtet man die Abbildungen aus Sicht des thermischen Managements – wo aufgrund der thermischen Impedanz die Summe der Verluste von Interesse sind, die in einer Pulsperiode anfallen und nicht die einzelnen Ein-, Aus- und Durchlassverluste – so liefert das Modell erstaunlich genaue Ergebnisse. Die Abweichungen zu der Messung liegen bei maximal 11%.
• – Die Kennlinien verdeutlichen, dass die Abweichungen zwischen E_on1 + E_off1 und E_on1chip + E_off1chip sowie zwischen E_on2 + E_off2 und E_on2chip + E_off2chip für den vorliegenden Messaufbau vernachlässigbar klein sind, wenn der Drainstrom im Durchlasszustand nicht signifikant ansteigt. Die gesamten Schaltverluste sind am Chip tendenziell geringer als die Verluste, die aus den Messdaten ermittelt wurden. Zwar ist dieser Unterschied in der untersuchten MOSFET-Brücke nicht von Bedeutung, doch muss das nicht immer so sein.

The pictures 203 (Comparison of the switching losses E _TR as a function of the gate resistance R _G (V _DClik = 30 V, I _L = 150 Ω and T _J = 25 ° C)) and 204 (Comparison of the switching losses E _TR as a function of the drain current I _D (V _DClink = 30 V, R _G = 10 Ω and T _J = 25 ° C)) summarize the results of a study, both on the evaluation of the Ausschaltenergien and the turn-on energies relates:

• - Looking at the figures from the point of view of thermal management - where, due to the thermal impedance, the sum of the losses occurring in one pulse period and not the individual input, output and forward losses is of interest, the model delivers astonishingly accurate results. The deviations from the measurement are a maximum of 11%.
• - The curves illustrate that the deviations between E _on1 + E _off1 and E _on1chip + E _off1chip as well as between E _on2 + E _off2 and E _on2chip + E _off2chip are negligibly small for the present test setup, if the drain current in the on-state does not increase significantly. The total switching losses on the chip tend to be lower than the losses that were determined from the measured data. Although this difference in the investigated MOSFET bridge is not important, this does not always have to be the case.

origin for the differences are the nonlinear switch capacities. (For simplification, it can be assumed that the inductance is constant even if theoretical electrical engineering is the opposite can prove.) The C-curves are effective when switching on and off different, as opposed to the direction of the run is. Thus act at the beginning and so also during the voltage commutation when switching on and off different capacities. That affects the losses.

bibliography

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• [2] Lindemann, A .: New Trench Power MOSFETs in Isolated Packages; PCIM Conference Nuremberg; 2001 ,
• [3] Mohan, N .; Undeland, T .; Robbins, W .: Power Electronics - Converters, Applications and Design; WILEY; 1989 ,
• [4] Baliga, BJ: Modern Power Devices; Warrior Malabar 1992 ,
• [5] Rodrigues, P .: Computer-Aided Analysis of Nonlinear Microwave Circuits; ARTECH HOUSE; 1998; P. 35 ff ,
• [6] Bronstein, IN et al.: Taschenbuch der Mathematik, Teubner Leipzig; 1998 ,
• [7] Wintrich, A .: Behavioral Modeling of Power Semiconductors for Computer-Aided Design of Power Electronic Circuits; Dissertation; TU Chemnitz; 1998 , ( http://archiv.tu-chemnitz.de/pub/1998/0023/index_en.html )
• [8th] Lutz, H .; Wendt, L .: Paperback of Control Engineering, Harri Deutsch Tuhn et al. 2000 ,
• [9] TU Ilmenau, Institute of Solid State Electronics, Department of Semiconductor Technology (Hrsg.): Practical Course Microelectronics and Sensor Technology - Experiment: Electrical Characterization , ( http://www.tu-ilmenau.de/fakei/fileadmin/template/fg/fke_nano/Lehre/Praktikum/M ESS_2.pdf )
• [10] Cooke MJ: Semiconductor Devices; Munich et al. 1993; P. 309 ff ,
• [11] Paul, R .: Electronic Semiconductor Devices; Stuttgart 1992; P. 415 ff ,
• [12] Paul, R .: Field Effect Transistors - Physical Fundamentals and Properties; Leipzig 1972; P. 95 ff ,
• [13] Scientific advice of the Dudenredaktion (ed.): Duden spelling of the German language; 21st edition
• [14] Zhao, Y. et al.: Pulsed Characterization of Charge-Trapping Behavior in High κ Gate Dielecrics, 2005 , ( http://www.keithley.com/products/data?asset=50323 )
• [15] Kerber, A. et al .: Origin of the threshold voltage instability in SiO2 / HfO2 dual layer gate dielectrics; IEEE Electron Device Letter, Vol 24, 2003; P. 87 ,
• [16] Kerber, A. et al.: Characterization of the VT instability in SiO2 / HfO2 gate dielectrics; in Proceedings 41st Annual IEEE Intl. Reliability Physics Symp., 2003; Pp. 41-45 ,
• [17] Young, CD et al.: Interfacial Layer Dependence of HfSixOy Gate Stacks on Vt Instability and Charge Trapping Using Ultra-short Pulse IV Characterization; in proc. 43rd Annual IEEE Intl. Reliability Physics Symp .; Pp. 75-79 ,
• [18] Fischetti, MV et al.: Effective electron mobility in Si inversion layers in metal oxide-semiconductor systems with a high-κ insulator: The role of remote phonon scattering; Journal of Applied Physics, Vol. 90, 2001, pp. 4587-4608 ,
• [19] Kerber, A. et al .: Direct Measurement of the Inversion Charge in MOSFETs: Application to Mobility Extraction at Alternative Gate Dielectrics, Proceedings of the VLSI Technology Symposium, 2003; Pp. 159-160 ,
• [20] Zhu, W .; Han, J.-P .; Ma, TP: Mobility Measurements and Degradation Mechanisms of MOSFETs Made With Ultrathin High κ Dielectrics; IEEE Transactions on Electron Devices, Vol. 51, 2004; Pp. 98-105
• [21] Young, CD et al.: Intrinsic Mobility Evaluation of High-κ Gate Dielectric Transistors Using Pulsed Id-Vg; Electron Device Letter, Vol. 26, 2005; P. 586-588 ,
• [22] Gusev, EP et al .: Charge Detrapping in HfO2 High-κ Gate Dielectric Stacks, Applied Physics Letter; 2003, Vol. 83; P. 5223 ,
• [23] Lee, BH et al .: Validity of Constant Voltage Stress Based Reliability Assessment of High κ Devices; IEEE Transactions on Device and Materials Reliability, Vol. 5, 2005; Pp. 20-25 ,
• [24] Zafar, S. et al.: Theshold Voltage Instabilities in High κ Gate Dielectric Stacks; IEEE Transactions on Device and Materials Reliability, Vol. 5, 2005; Pp. 45-64 ,
• [25] Ribes, G. et al.: Review on High κ Dielectrics Reliability Issues; IEEE Transactions on Device and Materials Reliability, Vol. 5, 2005; Pp. 5-19 ,
• [26] Lübbers, M. et al.: Modeling and Simulation of Low Voltage Trench Gate MOSFETs, PCIM 2006 ,
• [27] IXYS (ed.): FMM 150-0075P - Trench Power MOSFET Phaseleg Topology in ISOPLUS i4-PACTM; Application Sheet 2006 , ( http://ixdev.ixys.com/DataSheet/1466.pdf )
• [28] Petzoldt, J. et al .: Influence of Device and Circuit Parameters on the Switching Losses of an Ultra Fast CoolMOS / SiC Diode Device Set: Simulation and Measurement; ISPSD'2001, Osaka; Pp. 187-190 ,

QUOTES INCLUDE IN THE DESCRIPTION

This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.

Cited non-patent literature

• - DIN IEC 747 [0043]
• - Martin, P. (ed.): Application Manual IGBT and MOSFET Power Modules; ISLE Ilmenau; 1998 [0313]
• - Lindemann, A .: New Trench Power MOSFETs in Isolated Packages; PCIM Conference Nuremberg; 2001 [0313]
• Mohan, N .; Undeland, T .; Robbins, W .: Power Electronics - Converters, Applications and Design; WILEY; 1989 [0313]
• - Baliga, BJ: Modern Power Devices; Warrior Malabar 1992 [0313]
• Rodrigues, P .: Computer-Aided Analysis of Nonlinear Microwave Circuits; ARTECH HOUSE; 1998; P. 35 ff. [0313]
• - Bronstein, IN et al.: Taschenbuch der Mathematik, Teubner Leipzig; 1998 [0313]
• - Wintrich, A .: Behavioral modeling of power semiconductors for computer-aided design of power electronic circuits; Dissertation; TU Chemnitz; 1998 [0313]
• - http://archiv.tu-chemnitz.de/pub/1998/0023/index_en.html [0313]
• - Lutz, H .; Wendt, L .: Paperback of Control Engineering, Harri Deutsch Tuhn et al. 2000 [0313]
• - TU Ilmenau, Institute of Solid State Electronics, Department of Semiconductor Technology (ed.): Practical Course Microelectronics and Sensor Technology - Experiment: Electrical Characterization [0313]
• - http://www.tu-ilmenau.de/fakei/fileadmin/template/fg/fke_nano/Lehre/Praktikum/M ESS_2.pdf [0313]
• - Cooke MJ: Semiconductor Devices; Munich et al. 1993; P. 309 ff. [0313]
• - Paul, R .: Electronic Semiconductor Devices; Stuttgart 1992; P. 415 ff. [0313]
• - Paul, R .: Field Effect Transistors - Physical Fundamentals and Properties; Leipzig 1972; P. 95 ff. [0313]
• - Scientific Council of the Dudenredaktion (ed.): Duden spelling of the German language; 21st edition [0313]
• - Zhao, Y. et al.: Pulsed Characterization of Charge-Trapping Behavior in High κ Gate Dielcrics, 2005 [0313]
• - http://www.keithley.com/products/data?asset=50323 [0313]
• - Kerber, A. et al.: Origin of the threshold voltage instability in SiO2 / HfO2 dual layer gate dielectrics; IEEE Electron Device Letter, Vol 24, 2003; P. 87 [0313]
• - Kerber, A. et al.: Characterization of the VT instability in SiO2 / HfO2 gate dielectrics; in Proceedings 41st Annual IEEE Intl. Reliability Physics Symp., 2003; Pp. 41-45 [0313]
• - Young, CD et al.: Interfacial Layer Dependence of HfSixOy Gate Stacks on Vt Instability and Charge Trapping Using Ultra-short Pulse IV Characterization; in proc. 43rd Annual IEEE Intl. Reliability Physics Symp .; Pp. 75-79 [0313]
• - Fischetti, MV et al.: Effective electron mobility in Si inversion layers in metal oxide semiconductor systems with a high-κ insulator: The role of remote phonon scattering; Journal of Applied Physics, Vol. 90, 2001, pp. 4587-4608 [0313]
• - Kerber, A. et al .: Direct Measurement of the Inversion Charge in MOSFETs: Application to Mobility Extraction at Alternative Gate Dielectrics, Proceedings of the VLSI Technology Symposium, 2003; Pp. 159-160 [0313]
• - Zhu, W .; Han, J.-P .; Ma, TP: Mobility Measurements and Degradation Mechanisms of MOSFETs Made With Ultrathin High κ Dielectrics; IEEE Transactions on Electron Devices, Vol. 51, 2004; Pp. 98-105 [0313]
• - Young, CD et al.: Intrinsic Mobility Evaluation of High-κ Gate Dielectric Transistors Using Pulsed Id-Vg; Electron Device Letter, Vol. 26, 2005; P. 586-588 [0313]
• - Gusev, EP et al.: Charge Detrapping in HfO2 High-κ Gate Dielectric Stacks, Applied Physics Letter; 2003, Vol. 83; P. 5223 [0313]
• - Lee, BH et al .: Validity of Constant Voltage Stress Based Reliability Assessment of High κ Devices; IEEE Transactions on Device and Materials Reliability, Vol. 5, 2005; Pp. 20-25 [0313]
• - Zafar, S. et al.: Theshold Voltage Instabilities in High κ Gate Dielectric Stacks; IEEE Transactions on Device and Materials Reliability, Vol. 5, 2005; Pp. 45-64 [0313]
• - Ribes, G. et al.: Review on High κ Dielectrics Reliability Issues; IEEE Transactions on Device and Materials Reliability, Vol. 5, 2005; Pp. 5-19 [0313]
• - Lübbers, M. et al.: Modeling and Simulation of Low Voltage Trench Gate MOSFETs, PCIM 2006 [0313]
• - IXYS (ed.): FMM 150-0075P - Trench Power MOSFET Phaseleg Topology in ISOPLUS i4-PACTM; Application Sheet 2006 [0313]
• - http://ixdev.ixys.com/DataSheet/1466.pdf [0313]
• - Petzoldt, J. et al.: Influence of Device and Circuit Parameters on the Switching Losses of an Ultra Fast CoolMOS / SiC Diode Device Set: Simulation and Measurement; ISPSD'2001, Osaka; Pp. 187-190 [0313]

Claims (2)

Method for determining capacitance-voltage characteristics of electronic switching elements, characterized in that in controlled electronic switching elements (three contacts) the dependence of the input, feedback and output capacitance of the associated residual stresses or in passive electronic switching elements (two contacts) the dependence the interelectrode capacitance of interelectrode voltage is determined as a differential or large signal capacitance from application-typical commutation by the discrete-time measurement data input, Rückwirkungs- and output voltage and the input and output current and in passive electronic switching elements, the time-discrete measurement data of the interelectrode voltage and the Interelektrodenstromstärke application-typical Kommutierungsvorgängen be included; that the measured time-dependent voltages at controlled electronic switching elements by the input and output current strength or passive electronic switching elements by the voltage caused by the interelectrode current drops across the acting resistors between the measuring points and the chip as well as controlled electronic switching elements by the input and output current increase or in the case of passive electronic switching elements Interelektrodenstromanstieg caused voltage drops over the acting inductance between the measuring points and the chip can be corrected according to the second Kirchhoff's theorem to chip voltages; wherein in controlled electronic switching elements, the output capacitance current strength by difference of the static output current intensity and the dynamically measured current from the output characteristic field of the electronic switching element for each measurement time or in passive electronic switching elements, the Interelektrodenkapazitätsstromstärke by difference of the Interelektrodenkennlinie of the electronic switching element for each measurement time detectable static Interelektrodenstromstärke and the dynamically measured interelectrode current intensity is determined; This results in controlled electronic switching elements by numerical integration of the input current intensity and the output capacitance current or passive switching elements by integration of Interelektrodenstromstärke after offset corrections, which satisfy the condition that the charge of the capacitances at the time zero Coulomb, to which the residual stress of the capacitance is zero, the time-dependent input, feedback and output or Interelektrodenladungsverläufe from which the differential capacitances (C _diff = dQ (t) / dV (t)) and the large signal capacitances (C _LS = Q (t) / V (t)) of the electronic switching elements can be determined. Method according to claim 1, characterized in that that the determined capacitance-voltage characteristics for Parameterization of Interelektrodenkapazitäten corresponding Switch models for their network simulation under consideration be used of commutation and electrical engineering basics.