DE102007011817B4 - Method and device for locating faults on electronic circuit boards with capacitive sensor - Google Patents

Abstract

A method of locating faults on multi-pin electronic circuit boards (15), wherein test parameters (603, 604) of a circuit (3) of the component-mounted circuit board (15) are measured, the measured test parameters (603, 604) being referenced with reference parameters ( 601), wherein the test parameters (603, 604) are obtained from a match analysis of a signal acting on the circuit (3) and a signal measured on the circuit (3), either the signal applied to or the circuit (3) measured signal is coupled directly into the printed circuit board (15) or coupled out of this and the respective other signal via a capacitive coupling (410) from the printed circuit board (15) is coupled or coupled into this, wherein for measuring the test parameters (603, 604) in each case one of the n total pins of the circuit (3) is acted upon as a pin to be examined with the acting signal, wherein the other n-1 pins of the Circuit (3) are connected to a defined potential, and wherein a known bit sequence represented by a sequence of pulses from a voltage or current source (1) is impressed on the pin to be examined.

Description

The invention relates to a method and a device for locating assembly errors, component errors and contacting errors on electronic circuit boards.

Conventionally, methods are used for detecting assembly errors, component defects and contacting errors, which apply an input signal to the circuit and measure one or more output signals directly at the pins or at terminals provided for this purpose. However, these methods are not always applicable, especially in SMD construction, as a contacting of the pins is not always possible, and special connections are not always available.

The state of the art is based on the European patent specification EP 0 775 318 B1 directed. This discloses a method for locating errors on printed circuit boards. The output signal is tapped capacitively. However, no relation between the input signal and the capacitively determined output signal is considered. Only the serial capacity of the single pin is used as a measure to check the correctness of the pin of the circuit board. A disadvantage of the method described is its sensitivity to capacitive coupling interference.

Furthermore, the publications US 2007 001 687 A1 and EP 633 478 A2 directed.

The invention has for its object to provide a method and an apparatus for determining errors on printed circuit boards, which are easy to handle and at the same time interference size resistant.

The object is achieved for the method by the features of claim 1 and for the device by the features of claim 11. Advantageous developments are the subject of the dependent claims.

The invention is based on the concept described below:

To determine sources of error on a printed circuit board, a signal is impressed successively in all connections of the circuit to be examined. By means of a capacitive sensor, a signal is tapped off the circuit. On the basis of the relationship between the application signal and the capacitively tapped signal, errors can be localized on the measurement object by comparison with reference parameters of a faultless printed circuit board.

The method of measurement preferably begins in a first phase with the discharge of all capacitances of the printed circuit board. For this purpose, all reference and test pins are discharged current-limited to the GND potential via an ammeter and a discharge circuit. In the second phase, each test pin is taken individually from the common measurement lead and connected to a single lead. A defined signal is now applied to the test pin via the signal source.

Advantageously, a digital bit pattern generated from a square wave signal is used as the apply signal. Advantageously, the adjustment of output voltage, current limit, waveform and / or frequency can be set individually for each test point. The voltage applied to the circuit capacitive sensor receives the signal modified by the circuit and prepares it advantageously in a sensor electronics before it is forwarded. It is advantageous to record the output signal of the capacitive sensor equidistantly in synchronism with the output of the input signal. After completion of the measurement, the single test pin is reconnected to the common measuring line.

Advantageously, a source with a bipolar characteristic is used to act on it. When the reference pins are stimulated, so many signal paths in the circuit couple the signal into the capacitive sensor. This leads to a significantly higher signal level compared to conventional test methods.

The output signal is similar in shape to the apply signal. For example, a parameter for evaluating the circuit can be obtained from the comparison of the amplitudes. Advantageously, a detection of the applied bit pattern is carried out in the output signal. The recorded analog signal of the sensor is evaluated within the respective bit duration and assigned to the corresponding bit a 0 or 1 by comparison with a threshold. The detection rate provides the parameter for evaluating the printed circuit board.

The determination of the test parameters is advantageously carried out with the aid of a so-called "learning program". A faultless DUT is connected to the test system. Default values are set for all test pins and a test is performed. By varying or adapting the output voltage, current limiting, signal shape and / or frequency, the feed signal is varied until an optimum ratio between the application signal and the signal determined by the sensor is reached. Advantageously, optimal recognition of the bit pattern is thus achieved. The determined test parameters are compared with the measurement parameters. On the basis of specified threshold values, it is determined whether an error of the device under test is present at the respective pin.

• 1 Eine seitliche Schnittdarstellung eines Ausführungsbeispiels der erfindungsgemäßen Vorrichtung;
• 2 Eine Darstellung eines Ausführungsbeispiels der erfindungsgemäßen Vorrichtung bei der Entladung;
• 3 das in 2 dargestellte Ausführungsbeispiel der erfindungsgemäßen Vorrichtung bei der Beaufschlagung mit einem Eingangs-Signal;
• 4 ein beispielhaftes Blockschaltbild der Signalverarbeitung;
• 5 ein beispielhaftes Eingangs-Signal und ein zugehöriges abgetastetes und detektiertes Ausgangs-Signal des kapazitiven Sensors;
• 6 eine Übersicht beispielhafter Referenzparameter und möglicher Testparameter.

The invention will be described by way of example with reference to the drawing, in which an advantageous embodiment of the invention is shown. In the drawing show:

• 1 A side sectional view of an embodiment of the device according to the invention;
• 2 A representation of an embodiment of the device according to the invention during the discharge;
• 3 this in 2 illustrated embodiment of the device according to the invention when subjected to an input signal;
• 4 an exemplary block diagram of the signal processing;
• 5 an exemplary input signal and an associated sampled and detected output signal of the capacitive sensor;
• 6 an overview of exemplary reference parameters and possible test parameters.

First, in 1 the mechanical structure of the device illustrated before in the 2 and 3 the interconnection is displayed. Based on 4 to 6 the evaluation of the signals is clarified. Identical elements have not been repeatedly shown and described in similar figures.

1 shows an embodiment of the device according to the invention in a side sectional view through the circuit board 15 and the capacitive sensor 104 , On a circuit board 15 is by means of pins 101 (Pins) mounted an electronic component within a component housing 102. On the component housing 102 is the capacitive sensor 104 on. This is done by spring-loaded pins 103 kept in position. The signals of the capacitive sensor 104 are processed by the sensor electronics 106 and forwarded via the sensor electronics connection line 105. The use of a capacitive sensor makes it possible to contact even difficult-to-contact components, such as SMD components, since it is not necessary to reach all the pins of the component.

In the 2 is an embodiment of the device according to the invention consisting of the circuit board to be tested 15 with the circuit 3 , an interconnection matrix 4, a voltage source or discharge unit 1, a current measuring device 2 , a capacitor connected to ground 14 , the lines "Current test pin" 9, the reference line 10 and the line "Remaining Test Pins" 11.

The circuit to be tested 3 has an input in the example shown 12 , an exit 13 , a first connection 5 for power supply VCC, one supply line 7 for connection to the ground potential GND, a terminal VIO 6, a second terminal 8th for power supply VSS. The circuit itself consists in the illustrated example of two diodes connected in series 32 . 33 , an input resistance 30 and in series with an input amplifier 31. At the output are two serially connected driver transistors 34 . 35 , as well as each parallel to the transistors 34 . 35 switched diodes 36 . 37 and an output resistance 38 connected.

The interconnection matrix 4 is switchable with all pins of the printed circuit board 15 to the line "Current Testpin" 9. Similarly, all pin connections to the line "remaining test pins" 11 switchable. The interconnection matrix 4 In particular, each has a connection to the entrance 12 and one to the exit 13 the circuit to be tested 3 ,

The circuit to be tested 3 has at the connection VCC 5 , VSS 8th , VIO 6 and GND 7 a switchable connection to the reference line 10. The connections VIO 6 , VCC 5 , VSS 8th and GND 7 also have a switchable connection to the "Current Test Pin" line 9. The "Current Test Pin" line 9 is connected to VCC 5 a branch with a capacitor connected to ground 14 , The line "Current Test Pin" 9 has one in series with a voltage source 1 switched electricity meter 2 , The second pole of the voltage source 1 has a switchable connection to the lines "reference" 10 and "remaining test pins" 11 and is also connected in the exemplary embodiment to ground.

To avoid interference from parasitic or switched capacitances, the circuit is first discharged with all pins. The connection will be VCC 5 , with the cable "Current test pin" 9, via the ammeter 2 and about the voltage source 1 switched to ground. The grounded capacitor 14 is part of the circuit to be tested and should be discharged.

In 3 the test procedure is shown on a pin. This is done by the voltage source 1 the positive portion of the known input signal is switched to the line "Current Test Pin" 9. The line "Current Test Pin" 9 is via the interconnection matrix 4 on the pin to be tested, in the example shown on the input 12 the circuit 3 is connected, connected. Via the input resistor 30 and the upper diode 32 will that Signal on the connection VCC 5 and via the line "Reference" 10 to the second pole of the voltage source 1 transfer. Due to the bipolar characteristic of the voltage source 1 negative signal components of the input signal from the second pole of the DC power source 1 on the line "Reference" 10, for connection GND 7 the circuit 3, via the lower diode 33 on the input resistor 30, via the measured pin on the line "Current Testpin" 9 to the voltage meter 2a and to the first pole of the voltage source 1 transfer.

The unmated pins are connected to ground together with the line "remaining test pins" 11 in the exemplary embodiment. Each pin to be measured is individually examined and used to interpret possible sources of error. All other pins remain untouched by the measurement.

Before the measurement can begin, preferably all pins of the unit to be tested should be discharged so that erroneous measurements due to transhipment effects are avoided during the later test. These effects are typically caused by populated or parasitic capacitors. For this purpose, as in 1 shown, all reference and test pins via the ammeter and the discharge circuit controlled unloaded to the ground potential and connected to a common measuring line "reference" or "remaining test pins".

In the second phase, each test pin is separated individually from the common test lead "remaining test pins" 11 and connected to the test lead "current test pin" 9. The test pin is measured via two circuits. The first starts at the voltage source 1 and carries the test pin, the VCC pin 5, the reference line and back to the voltage source 1 via the line "Current test pin" 9. The second circuit also starts at the voltage source 1 and leads over the line "Current Testpin" 9, the test pin, the GND connector 7 , the reference line 10 and back to the voltage source 1 , The remaining pins in the interconnection matrix 4 are connected to the line "Remaining test pins" 11. About the voltage source 1, a signal is now given to the Prüfpin.

The setting of output voltage, current limit, signal shape and / or frequency can preferably be set individually for each test point. Simultaneously with the switching on of the voltage source, the signal of the capacitive sensor 104 via the sensor electronics 106 and the sensor electronics connection line 105 transmitted to the voltmeter 2a and recorded eg equidistant. Here, the test pin is examined completely autonomously. Then each test pin is reconnected to the test lead "Remaining test pins" 11.

Alternatively to the measuring arrangement shown in the drawing can be measured with a changed direction of measurement. That the circuit 3 acting signal is via a in place of the capacitive sensor 104 mounted capacitive coupler impressed. While all remaining n-1 pins are connected to the line "Remaining Test Pins" 11, the current is measured by the test pin and in the evaluation device 400 processed.

4 shows an exemplary block diagram of the processing of the input signals and output signals. The capacitive sensor 104 stands with the circuit 3 via a capacitive coupling 410 in connection. The capacitive sensor is with the sensor electronics 106 connected. The sensor electronics 106 is still with the voltmeter 2a connected. The voltmeter 2a is connected to an evaluation device 400. The evaluation device 400 consists for example of an analog-to-digital converter 403 , a detector 402 , a control device 401 and a digital-to-analog converter 404. The voltmeter 2a is connected to the analog-to-digital converter 403. This one is with the detector 402 connected. The control device 401 is with the detector 402 and the digital-to-analog converter 404 connected. The digital-to-analog converter 404 is connected to the voltage source 1 in connection. The voltage source 1 is with the circuit 3 connected.

That from the voltmeter 2a measured signal is sampled by the analog-to-digital converter 403 and sent to the detector 402 transmitted. The control device 401 generates the input signal to which the circuit 3 is applied in digital form and transmits it to the digital-to-analog converter 403. This generates an analog signal with which the voltage source 1 is controlled. This generates the circuit 3 acting signal. The detector 402 detects the values of the received bits and passes the result to the controller 401 further. In the control device 401 become the test parameters from the detected values 603 . 604 and compares it with reference parameters 601 to derive the errors of the printed circuit board 15 to investigate.

5 shows an exemplary input signal 502 and an already processed output signal 500 of the capacitive sensor. As input signal 502 a known bit sequence was chosen. This is an input signal as a result of rectangular pulses 502 connected. To determine the test parameters when using such an input signal, the output signal of the capacitive sensor 104 via a sensor electronics 106 prepared, eg reinforced. Subsequently, the signal is in the voltmeter 2a measured and sampled bit-wise. The sampling takes place to those from the input signal 502 known bit times. The detection rate of the correct bits of the input data in the output signal is used, for example, as a test parameter for the evaluation of the circuit. Mis-detected bits 501 indicate an error of the respective pin.

In the example of 5 is a detection rate of 7/8 detectable. Another exemplary test parameter is the result of the correlation of the output signal with the input signal.

The determination of the setpoint values or desired value ranges of the test parameters is preferably carried out with the aid of a learning program. The definition of the test pins is done via an editable configuration file. An error-free sample copy of the test object 15 is connected to the test system. Default values are set for all test pins and a test is performed. By varying or adapting the output voltage, current limitation, signal shape and frequency, the input signal is varied until an optimum ratio between the application signal and the signal determined by the sensor is reached.

6 shows an overview of exemplary reference parameters 601 on different pins and associated test parameters 603 and 604 , Hatched is a test parameter span 602 , in which the measured value may be, so that the candidate is judged to be faultless. The test parameters 603 lie within the test parameter range 602 and thus correspond to the specification. The test parameters 604 lie outside the test parameter range 602 and do not conform to the specification. Is at least one test parameter 604 outside the test parameter range 602 , the examinee is judged to be faulty. The 6 shows the type of reference parameters 601 and associated test parameters 603 and 604 Not. The statements can be used for all reference parameters 601 and test parameters 603 and 604 generally considered.

The invention is not limited to the illustrated embodiment. As mentioned earlier, for the reference line 10 also other potentials than the ground potential GND can be used. Instead of a voltage source and a current source can be used, in which case instead of a current limit, a voltage limitation is used. The inventive method is not limited to digital ICs, but is also able to test passive components or circuit clusters. All features described above or features shown in the figures can be combined with each other in the invention as desired.

Claims (18)

Method for locating faults on multi-pin electronic circuit boards (15), wherein test parameters (603, 604) of a circuit (3) of the component-mounted printed circuit board (15) are measured, the measured test parameters (603, 604) being compared with reference parameters (601), the test parameters (603, 604) being obtained from a match analysis of a signal acting on the circuit (3) and a signal measured on the circuit (3), whereby either the acting signal or the signal measured at the circuit (3) is coupled directly into the printed circuit board (15) or coupled out of this and the respective other signal via a capacitive coupling (410) from the printed circuit board (15) coupled out or is coupled into this, wherein in order to measure the test parameters (603, 604), one of the n pins in total of the circuit (3) is acted upon as the pin to be examined by the applied signal, wherein the other n-1 pins of the circuit (3) are connected to a defined potential, and wherein a known bit sequence represented by a train of pulses from a voltage or current source (1) is impressed on the pin to be examined. Method according to Claim 1 , characterized in that for measuring the test parameters (603, 604) the signal acting on the circuit (3) is introduced conductively over the respectively to be examined pin, and that the signal measured on the circuit via the capacitive coupling (410) is measured. Method according to Claim 1 or 2 , characterized in that the capacitive coupling (410) by a capacitive sensor (104) which rests on the circuit (3) takes place. Method according to one of Claims 1 to 3 , characterized in that all pins are discharged current-biased to a ground potential before being exposed to a voltage or current source (1) via a discharge circuit. Method according to one of Claims 1 to 4 , characterized in that an adjustment of an output voltage or an output current, a current or voltage limit of a waveform and / or a frequency of the signal source (1) is done separately for each pin to be examined. Method according to Claim 3 , characterized in that the signal of the capacitive sensor (104) is recorded starting with the switching on of the signal source (1). Method according to one of Claims 1 to 6 , characterized in that the reference parameters (601) are determined on a perfect sample part and then stored. Method according to Claim 5 , characterized in that all measured values are adjusted by variation of output voltage and current limiting or output current and voltage limitation of the signal source (1) in a range of about 50% of the maximum value in order to achieve the maximum sensitivity at different test parameters (603, 604) , Method according to Claim 3 or 6 , characterized in that the output signal of the capacitive sensor (104) is sampled and the bit value is detected, that the resulting bit sequence is compared with the known bit sequence of the applied signal, and that the sequence of correctly detected bits is used as test parameter ( 603, 604) is used. Method according to Claim 8 , characterized in that the output signal of the capacitive sensor (104) is correlated with the applied signal, and that the result of the correlation is used as a test parameter (603, 604). Device for locating faults on electronic printed circuit boards (15), with a method according to one of the Claims 1 to 10 with a programmable signal source (1), a capacitive sensor (104) or a capacitive coupler, a flexible connection matrix (4) for the pins to be examined, an evaluation device (400) and a circuit for discharging the pins to be tested. Device after Claim 11 , characterized in that the evaluation device (400) determines test parameters (603, 604) and compares the test parameters (603, 604) with reference parameters (601) and the comparison of the test parameters (603, 604) with the reference parameters (601) the printed circuit board determines that the evaluation device (400) applies signals to the circuit, that the evaluation device (400) evaluates signals measured at the circuit (3), and that the evaluation device (400) uses the signals measured at the circuit (3) the signals acting on the circuit (3) determine the test parameters. Device after Claim 12 , characterized in that the, the circuit (3) acting signal is a known signal, and that the evaluation device (400) determines the test parameters (603, 604) by means of a match analysis of the measured signals and the circuit (3) acting signals. Device after Claim 13 , characterized in that the signal applied to the circuit (3) is a train of pulses. Device after Claim 14 , characterized in that the evaluation device consists of an analog-to-digital converter (403), a digital-to-analog converter (404), a detector (402) and a control device (401). Device according to one of Claims 11 to 15 , characterized in that the capacitive sensor (104) picks up the signal measured at the circuit (3). Device according to one of Claims 11 to 16 , characterized in that the signal source (1) by a bipolar characteristic allows the measurement of a plurality of signal paths. Device after Claim 17 , characterized in that the programmable signal source (1) is a programmable output voltage and current limiting bipolar pulsed voltage source (1) or a programmable output current and voltage limiting bipolar pulsed current source (1) with programmable waveform and / or frequency.

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