DE102007009727A1 - Method for manufacturing semiconductor component, involves preparing semiconductor substrate with active area and boundary area, which is adjacent to active area, where active area has conducting material having trenches - Google Patents

Abstract

The method involves preparing a semiconductor substrate (18) with an active area (10) and a boundary area (11), which is adjacent to the active area. The active area has a conducting material (16), which has trenches (15) in the semiconductor substrate. The conducting material is insulated from the semiconductor substrate in the trenches by an insulating layer (17). A spacer layer (12) is formed over the semiconductor substrate, which has a varying thickness (d-2,d-1') in the boundary area. An independent claim is also included for a semiconductor component.

Description

The The present invention relates to semiconductor devices and Manufacturing method for producing semiconductor devices and more particularly to vertical semiconductor devices.

at current power MOSFETs will in addition to the lowest possible on-resistance Rdson also always reducing the gate-drain reaction capacity more important. This capacity is essential for responsible for dynamic switching losses.

In an active cell array of such a power MOSFET, referred to as Trench transistor is formed, this z. B. by the introduction of a Source electrode under the gate electrode will be realized. Both types of electrodes are z. B. from highly doped Realized polysilicon. Independently whether the gate electrode alone is present in the trench, or whether there is still a source electrode under the gate electrode which is also referred to as a "field plate" However, the electrode must always be contacted in the trench.

These Contacting can take place, for example, in the edge area. Especially This connection can be made, for example, by contacts on planar Polysilicon can be produced in the edge region. This is to the Where contact has to take place, in the case of re-etching Polysilicon covered by a resist mask.

to Contacting the source region of a transistor becomes this Oxidenfernung made in the cell field to the oxide up to to etch away the top edges of the semiconductor mesa structures between the trenches a source contact metallization to be able to raise.

Furthermore is in the edge region a contacting of the gate material or the Source electrode under the gate electrode performed by the oxide above the planar conductive layer in the edge region open becomes.

By Applying metal material in this opening in the edge area can then the planar conductive Layer in the edge region and thus the gate electrode or possibly the Source electrode be contacted below the gate electrode.

adversely At this procedure is that different processing steps for the Cell field, so for the active area on the one hand and for the edge area on the other required are. So, when the cell field is first processed, covered the edge area, so that an oxide removal in the cell field does not affect the fringe area. This is then when an oxide removal should take place in the edge area, the active area covered. If both in the active area and in the edge area of the oxide the required places is removed, if necessary a common Metallization performed.

These Step sequence is expensive and therefore expensive and especially with regard to the risk of rejects, with each additional Process step may occur disadvantageously.

One The first aspect of the present invention relates to a method for producing a semiconductor device, comprising a step of Providing a semiconductor substrate with an active region and an edge region adjacent to the active region, wherein the active area with conductive Material filled Trenche in the semiconductor substrate, wherein the conductive material in the trenches through an insulating layer of the semiconductor substrate is isolated, and wherein between two trenches each have a Halbleitermesastruktur is formed, wherein in the edge region, a layer of the conductive material, which is isolated from the semiconductor substrate by an insulating layer is, and that with the conductive Material in the trenches is short-circuited, is formed, being above the Semiconductor substrate, a spacer layer is formed, which in Edge region has a varying thickness, and a step of breaking the spacer layer in the edge region at a selected location and Removing at least a portion of the spacer layer in the active layer Area using a common process step, wherein the place so selected is that under the condition that the spacer layer in the active Area is removed so that at least a portion of the Halbleitermesastruktur exposed is and the conductive one Material is not exposed in the trenches, the spacer layer in the edge area to the conductive Layer and not broken through to the semiconductor substrate.

A second aspect of the present invention relates to a semiconductor device comprising a semiconductor substrate having an active region and an edge region adjacent to the active region, the active region comprising conductive material filled trenches in the semiconductor substrate, the conductive material in the trenches being penetrated by an insulating layer of wherein a semiconductor mesa structure is formed between two trenches, wherein in the edge region a contact structuring is provided, which has a contact layer which is isolated from the semiconductor substrate, wherein above the contact layer, a spacer layer with varying thickness from place to place is formed, wherein the spacer layer at a position in the Edge region is broken at least up to the contact layer; and wherein the contact patterning is such that, at the location, a thickness of the spacer layer is within a tolerance range less than or equal to a thickness of the spacer layer in a range laterally limiting contact of the semiconductor memory structure in the active region.

Specific Semiconductor devices are MOS power transistors or so-called. IGBTs, ie insulated gate bipolar transistors. Unlike MOS power transistors, a source area, an adjoining body area, in which a channel can form and a subsequent drain region IGBT transistors have an emitter region connected to the Body area adjoins, which represents an upper base area. The lower base area becomes the semiconductor region adjacent to the body region formed having the same doping type as the emitter region. If necessary, a field stop layer adjoins the semiconductor region, which has the same doping as the lower base region, and the on its other side to a bipolar transistor collector, the also referred to as a "p-emitter", borders.

preferred embodiments The present invention will be described below with reference to FIGS attached drawings explained in detail. Show it:

1 a semiconductor device having an active region and a peripheral region;

2a a plan view of an edge region for illustrating a positioning of terminals in the edge region;

2 B a micrograph of a cross section of the implementation of 2a , in which case the contact is not yet drawn over the edge of the poly-silicon;

3a a plan view of an edge region for schematically illustrating an alternative contact positioning;

3b a schematic microscope photograph of a cross section through a structure of 3a with underlying poly layer and an underlying trench;

4 a schematic plan view of an alternative implementation of a contact on the polygon over the trench;

5a a plan view of an alternative implementation of a trench field under the poly-contact area;

5b an electron micrograph of a cross section of the structure of 2 before the contact hole filling;

6a a schematic representation of the cell field situation with sunk intermediate oxide;

6b a schematic representation of the chip edge situation with dummy trench;

7 a schematic representation of the contacting of the poly-gate in the edge region;

8th a schematic representation of the effectiveness of a "dummy Trenches";

9 a flowchart for illustrating a method for producing a semiconductor device;

10a a schematic representation of the situation in the chip edge region in a planar poly layer after application of the insulator intermediate layer;

10b a schematic representation of the cell array after application of the insulator intermediate layer with recessed intermediate oxide in the trenches;

11a a plan view of a semiconductor device;

11b a cross-section transverse to the trenches in the active area section A of 11a by a semiconductor device of 11a ;

11c an alternative cross section parallel to the trenches section B of 11a through the device of 11a ;

11d a schematic representation of the situation in the active area and in the edge region before the oxide etch with too thick oxide in the edge region;

12a to 12d a schematic representation of the various manufacturing steps for generating a transistor cell in the active region from gate poly Recess until immediately before the oxide etch and the upper trench portion;

13a a cross section through a semiconductor device with thick oxide-insulated trenches in the edge region and active trenches in the active region after the oxide etch;

13b an enlarged view of the upper trench portion after the Kontaktlochät Zung; and

13c a schematic cross-sectional microscope view of a failed contact attempt in the edge region after the same oxide etching as in 13b shown.

1 shows a schematic cross-sectional view of a semiconductor device with an active region 10 which is adjacent to a border area 11 adjacent, but the active area and the edge region in the figure does not necessarily have to come from the same cross-section, but wherein the edge region z. B. is another cross-sectional view than the active area. Important in 1 is however the one in the active area 10 shown spacer layer 12 , which is also present in the border area and there also with 12 is designated. In particular, the spacer layer has 12 in the active region, a thickness d ₁ over a semiconductor mesa structure 14 , The semiconductor mesa structure 14 is by two parallel trenches 15 defined, where the trenches 15 with a conductive material 16 are filled, wherein the conductive material 16 via a gate oxide 17 from the semiconductor substrate 18 is isolated. After the trenches do not reach the top of the semiconductor mesa structure with conductive material 16 but only up to a certain level below the top edge of the semiconductor mesa structure 14 is the top edge of the spacer layer 12 in the active area not completely flat, but has certain "dents" above the trenches, as in 1 at 13 is drawn. Further, due to the fact that in the "trench top areas" defined by the top edge of the semiconductor mesa structure and the top edge of the conductive material 16 , the thickness of the spacer layer 12 over the semiconductor mesa structure, which is denoted by d ₁ , total less than a thickness d ₂ in the edge region above a layer 20 made of conductive material. In the edge region, the thickness of the spacer layer would be above the layer 20 made of conductive material, if the layer of conductive material were continuous. Due to the special structuring of the layer of conductive material in the edge region, for example in two adjoining layers, a spacer layer is formed in the edge region 12 achieved with varying thickness, which varies between the large thickness d ₂ and the small thickness d ₁ .

So, as it is in 1 dashed lines, the gate contact or the poly-source contact 21 placed where the thickness of the spacer layer 12 above the conductive layer 20 in a tolerance range is equal to the thickness d _{1 of} the spacer layer 12 in the active region above the semiconductor mesa structure. Optimal applies d ₁ '<= d ₁ , such that when in the active region of the source contact, the dashed at 21 is drawn, in the same operation, the gate-poly-source contact 21 will be produced. For making the source contact 22 and the gate / poly source contact 21 becomes the same etching of the spacer layer 12 used both in the active area and in the border area. The etching is carried out in the active region so far that the spacer layer 21 to the top of the semiconductor mesa structure 10 is removed, while at the same time the etching is not carried out so far that the conductive material 16 is exposed in the trench. This should be isolated by an insulating layer above the trench, as will be explained later. The etching must therefore stop in time, so that the trench material is not exposed in the trench. It is also important that in the edge region of the spacer layer 12 to the conductive layer 20 such that contacting of the conductive layer can be achieved, and that no oxide remains on the conductive layer, due to the fact that the etching has already been stopped so as not to be the conductive electrode in the active region 16 ditch in the ditch. Furthermore, care must be taken that the semiconductor material is in the edge region 18 is not exposed, otherwise there would be a short circuit of the gate electrode or the poly-source electrode in the trench with the semiconductor material, when then a contact hole is filled with conductive material, as will be explained.

It should be noted that the conductive layer 20 in the border area is structured so that it is a spacer layer 12 above the conductive layer 20 There is a varying thickness. Furthermore, this spacer layer is then pierced exactly at the point where the thickness d ₁ , in the edge region is equal to or smaller than the thickness d ₁ in the active region. So if the thickness in the edge region of the spacer layer 12 above the conductive layer is smaller than the thickness of the layer in the active region, here is an opening of the spacer layer 12 performed, and the thickness should be large enough that no contacting of the semiconductor material 18 takes place. It must therefore be ensured that the contact hole for contacting the conductive layer 20 not to the semiconductor material 18 is enough to avoid the said short circuit.

9 shows a possible implementation of a manufacturing method for producing a semiconductor element. In one step 90 For example, a substrate having an active area and an edge area is shown, wherein the substrate has a varying ceiling of the spacer layer in the edge area 12 having. In one step 91 Then, the spacer layer in the active region and in the edge region is broken by a common contact hole etch, wherein, when a flat source contact is generated in the active region, the spacer layer in the active region is completely removed, while in the edge region only at the points the spacer layer is broken, where a contacting of a conductive layer has to be made.

After the step 91 In one implementation, it becomes an etching step 92 in order to etch the bulk trenches in the mesa structure in the active area, and furthermore, due to the fact that there are no intermediate steps that would cover somewhat in the edge area, the exposed layer is also etched in the edge area. The bulk trenches are in 11b at 25 drawn, and the result after this step 92 in the border area is in 5b shown.

This will be done in one step 93 applied a metallization in both the active region and in the edge region, which fills the contact holes or the contact trenches in the edge region, covering the remaining spacer layer there, and also covers the exposed structures in the active region and also covers remnants of the spacer layer adjacent to the contact. In this metallization, the region of the spacer layer between the contact holes in the edge region and the source contact is further metallized. However, this intermediate area then becomes one step 94 removed again, for example by photolithography, to separate the source contact and the gate contact and the poly-source contact from each other.

A resulting semiconductor device thus has the contact layer in the edge region 20 passing through the overlying spacer layer 12 through the contact 21 is contacted. This contact structuring, so the contact 21 to the conductive layer 20 or the contact layer in the edge region is formed so that at the point where the contact 21 in the spacer layer 12 with more variable thickness, the thickness of the spacer layer within a tolerance range is less than or equal to the thickness of the spacer layer, as present in a region in which contact of the semiconductor memory structure in the active region is laterally limited. This place is in 1 for example with 19 located. There is the edge of the source contact and there abuts the edge of the source contact to the durchgeätzte spacer layer, which still has a thickness which is about as large as the thickness of the spacer layer in which this spacer layer has been broken in the edge region. The thickness in the edge region can also be smaller than the thickness of the spacer layer at the location 19 , The thickness of the spacer layer 12 however, at the edge where the contact is present, it is not larger than the thickness of the spacer layer at the location 19 , since otherwise a successful joint etching of active area and contact area in the edge area is not possible.

Before discussing more specific exemplary embodiments, an exemplary semiconductor component will first be described with reference to FIG 11a - 11d described that z. B. may be a MOS field effect transistor, but at the same time may also be an insulated gate bipolar transistor (IGBT).

11a shows a plan view of such a transistor. The transistor has dotted lines trenched with conductive material 16 are filled, and by an insulating layer 17 from the semiconductor substrate 18 are isolated. However, there is a large source contact across the entire transistor 22 covering the trenches as well as the conductive materials in the trenches as well as the oxide layers, for which reason the latter are only indicated by dashed lines. The source contact 22 covers the entire active area and eventually stops at the edge area, as in 11a is shown. However, the trenches extend at the in 11a As an example, the transistor is drawn a little further and the trench filling is led out of the trenches in the peripheral area, around the conductive layer 20 to build. The conductive layer 20 is upwards with the spacer layer in 11a not indicated, covered, and the spacer layer 12 is through contact holes 21 pierced, which are filled with conductive material and through a gate contact 23 connected to each other. Of course, the contact holes could 21 also be designed as a continuous contact trench, this trench then directly the gate contact 23 could form.

The conductive layer 20 will be at the in 11 transistor formed by a "pulled out" trench filling material, said trench filling material, which is pulled out at the edge, either the gate electrode may be, or, as will be explained later, may be the poly-source electrode, which is arranged in the trench below the gate electrode.

11b shows a cross section along a line AA in 11a , In particular, it is shown that in the semiconductor mesa structures 14 a trench is formed, which at 25 is shown. This trench will be when the semiconductor mesa structure 14 is etched into the corresponding mesa structures etched to a depth extending below the n ⁺ source regions. Thus, if the source contact 22 is applied, and if the source contact material in particular in the trenches 25 is introduced, made a contact of the body area, wherein at the in 11b shown configuration in which the contacting of the source regions and the body Be If the same material is used, a short circuit between the body and source is automatically achieved, as is desired for many transistor applications.

In particular, the doping ratios are in 11b so that the source area that with 26 is designated, highly doped and to a low-doped region 27 adjacent, which is referred to as a body region, which in turn to a drain region 28 borders. The area 28 and the area 26 have the same doping characteristic opposite to the doping characteristic of the region 27 is. In particular, the areas are 26 and 28 n-doped and the area 27 p-doped, although the doping ratios may be reversed. If the semiconductor device is designed as a field-effect transistor, then the region 28 a highly doped layer having the same characteristic, which is further connected to a metal electrode which forms the drain of the field effect transistor.

Is the device in 11b whereas an insulated gate bipolar transistor is the area 26 the emitter of the transistor, so is the range 27 the upper base area, and is the area 28 the lower base area. Furthermore, a field stop region with a higher doping, which adjoins the collector of the transistor, which adjoins the doping conditions in FIG 11b has a p-doping to serve as a collector or as a hole emitter. In the case of the IGBT, this collector is then provided with a metallization.

11c shows a cross section along the line BB of 11a to make an exemplary transition between the active area 10 and the edge area 11 display. Especially interesting in 11c is the end of the source contact 22 and the adjoining pulled-out portion of the trench filling material comprising the layer 20 from 1 for example, forms. It is also shown how this withdrawn section 20 via a contact hole in which the gate contact 21 is arranged, contacted. 11d shows the situation of the semiconductor device before the etching of the source contact hole. As it is based on 11b and 11a has been shown, the entire surface of the active region is typically covered by a source contact, so that a large-area power supply takes place. Of course, structured source contact strips or the like could also be used. Full-area source contacts are preferred.

One Problem with oxide etching may be that it can not simply be extended until that Oxidized oxide even in the edge area Since then in the cell field, the electrodes located in the trench be exposed. In a fol lowing metallization so would Source and electrode shorted.

Before the source contact hole is etched, the spacer layer is located 12 on the semiconductor substrate in the active region. The spacer layer is also located in the edge area 12 on the in 11d shown withdrawn section with trench filler.

If there are no trenches in the edge region, the thickness d ₂ in the edge region is greater than the thickness d ₁ in the active region. If you look at the im 11d As shown in the scenario shown in the active area, the silicon mesa structure free etched, and the oxide removed to the thickness d ₁ , one would not yet in the edge region to the conductive layer 20 penetrate. So it would be after the contact etch oxide residues in the edge region above the conductive layer 20 left over. Simultaneous contacting of the source cell array and drive electrodes, that is, gate electrodes or field electrodes is thereby prevented, since the oxide thickness d ₂ in the edge region over the poly layer 20 significantly thicker than in the cell field. Therefore, it may happen that in the 11d Case shown, the chip can not be controlled or its maximum breakdown voltage is no longer achieved, as exemplified in 13c is shown. If this problem occurs, sufficient security would have to be achieved by introducing an additional photo level and an additional process, which would result in additional costs.

On the other hand, it should be noted that typically in the sense of a high transistor yield, all processes are optimized for the active region, and therefore the edge region must be aligned with the processes of the active region. So if the active area no longer etching the spacer layer 12 allows, since then a breakthrough to the conductive material would be achieved in the trench, so this etching must be stopped, regardless of whether a Durchät tion through the spacer layer 12 on the conductive layer 20 has been reached in the border area or not.

The following is based on the 12a - 12d a typical sequence for the preparation of trench structures shown. At the in 12a - 12d shown trenches are two electrodes in the trench. The upper electrode 16 represents the gate electrode and the lower electrode 30 represents the poly-source electrode or field-plate electrode. While the oxide 17 next to the gate electrode 16 is a thin oxide, so that the transistor has a good control behavior, is the oxide 17 next to the lower electrode 30 a thick oxide, there with the transistor has a good breakdown behavior. Starting from the in 12a is then shown in 12b the residual oxide 31 Still located on top of the trench, removed. This is the so-called. Postoxide 32 Grown up, as is in 12c is shown. Then, as it is in 12d shown is an intermediate oxide 33a . 33b which may be one or a combination of PSG, USG, TEOS or nitride. Subsequently, a planarization can be carried out.

Then the in 12d An anisotropic etch backlit schematic device structure having a combination of CMP and an oxide etcher or only an oxide etcher to produce the source contact hole is shown. In this case, the oxide in the cell field is etched back under the Si edge, while the connection of the edge contacts results from the cell field requirements. A schematic representation after the etching for the production of the source contact hole is shown in FIG 13a shown. The two right trenches and the right half of the middle trench form the active area, while the left half of the middle trench and the two left trenches already represent the edge area, which is also evident from the fact that the conductive electrodes in the trenches are replaced by a thick oxide from the Semiconductor material are isolated while the upper electrodes 16 in the active area only by a thin oxide 17 are separated from the semiconductor.

It should also be noted that the uppermost corrugated layer 40 is merely a microscope contrast agent, which serves better preparability and is not normally present, but that a semiconductor device without this layer is obtained when the contact hole etching has taken place in the active area, while the edge area is covered. In the edge area are in particular the postoxide 41 and the intermediate oxide 33a . 33b see, where the postoxide and the intermediate oxide together the spacer layer 12 form.

13b shows an enlarged view of the upper portion of a trench in the active area after the contact hole etching. Thus it can be seen that the surface of the silicon mesa structure is etched free. Since the etch is an oxide etch, the etch stops when the surface of the silicon mesa structure is exposed. However, in the oxide-filled trenches, the etch continues to etch defined under the mesa top features. However, the etching process must be stopped in good time so that there is still oxide above the gate electrode 16 remains so that no short circuit between source and gate is achieved. It should be noted that the etching process is not self-adjusting here, since the etching process above the gate electrode does not stop by itself, but must be actively terminated.

Due to the in 11d described situation, a simultaneous etching then leads to an insufficient contact takes place in the edge region, since the spacer layer 12 , in the 13c is called oxide, not completely up to the poly layer 20 is broken, as is clear from the microscope 13c is apparent. Thus, a skilful layout arrangement with regard to the structuring of the conductive layer in the edge region and / or the placement of the contact hole location in the edge region for contacting the gate electrode and / or the poly-source electrode achieves maximum security without additional processes, ie costs.

Special aspects include, for example, different approaches. A first aspect is based on the 2a and 2 B shown. In particular, as it is in 2a and 2 B is shown, the contact 21 placed in the edge area where the spacer layer 12 has a thinner thickness d ₁ , so that the contact hole, in which the metal contact 21 is attached, up to poly layer 20 passes. As the poly layer 20 is contacted near its edge, and due to the fact that typically used oxide, such as BPSG 33b from 12d , is relatively viscous, is how it is in 2 B at 42 is shown, the spacer material in the areas adjacent to the poly layer 20 "Flow", which causes the thickness of the spacer layer 12 near the edge of the poly layer 20 varies as indicated by a dashed line 43 in 2 B is indicated.

Thus, the drop in oxide thickness towards the edge is utilized. The contact is thus placed on the poly-edge, taking advantage of the effect of the BPSG flow, which means that the oxide over the edge is thinner due to the surface forces than on the left in the planar poly region 2 B where the thickness d is ₂ .

In an alternative embodiment, which is in 3a and 3b As shown, the contact between two polyvias is set, thereby preventing etching of the silicon substrate between the webs, since the oxide between the webs is thicker due to the flow-through step than over the poly-webs and is significantly thicker than on the poly-edge. In the 3a shown situation corresponds approximately to the in 1 shown representation where the contact 21 between the two layers 20 is appropriate. 3b shows a cross section through a semiconductor substrate, which is not exactly the situation in 3a corresponds, in addition to the conductive layers 20 which are set at a distance, nor an underlying conductive layer 45 exists in a ditch 46 leads to the later will be received. However, in 3b to see that the thickness of the oxide near the edges, which is marked with d ₁ , is much thinner than the leftmost or rightmost in 3b or in the middle, the higher thickness of the spacer layer 12 in the middle with d _{2 is} marked.

It should be noted that the thickness d ₁ above the edges corresponds approximately to the thickness d ₁ in the active cell array. This will ensure that an etch down to the layers 20 However, due to the higher thickness between the two layers, it takes place 20 no contacting of the underlying polysilicon layer 45 takes place. If this layer is not present, there should be no contacting of the semiconductor 18 take place so that no short circuiting between the gate filling material and the semiconductor is generated.

4 shows another aspect in which the contact is placed on the polygon over the trench. In this case, an etching of the silicon mesa section or of the semiconductor substrate is likewise carried out 18 prevents, since in case of doubt, if further etched, only the polysilicon would be etched out of the trench. 4 So in cross-section shows the situation when the lower layer 45 from 3b at the with 47 designated point to be contacted, and along along the trench 46 ie into the drawing plane or out of the drawing plane. It should also be noted that in this embodiment, the thickness d ₂ , the in 3b is at least as thick as the thickness d ₁ in the cell field, as it is in 1 is drawn. However, the thickness d ₂ could also be smaller, since the oxide etch on the polysilicon 45 automatically stops. In this case, it would have to be ensured that the thickness d _{2 is} in any case less than or equal to the thickness d ₁ . This can be achieved by creating trenches in the edge region, for example, as will be explained later, which have no gate functionality but merely serve to sink oxide to a thinner oxide level, ie a thinner spacer layer 12 reach, at the point where a contact is to be achieved.

In any case, at the in 3b In the example shown, if, after the oxide etch, a semiconductor etch still occurs to create the trenches in the mesa structure, which in FIG 11 With 25 are drawn and contact the body contact, just from the ditch 46 Etched polysilicon, but without such etching would in turn lead to a short circuit. However, a transistor structure would be built where the trenches 25 are not necessary, because the body region is floating or otherwise contacted, no polysilicon would be removed from the trench 46 in 3b be etched away.

The following is based on 5a and 5b another alternative for contact positioning shown. Here, a trench field is provided under the polycontact region, and the contact is positioned between two trenches. In particular shows 5b a cross section through the extracted area in 11a , although there the trenches compared to 11c until the end of the shift 20 continue and do not stop earlier. In particular, in 5b two adjacent trench fillings through the above the Halbleitermesastruktur 14 extending metallization structure 20 shorted together. Along with the etching of the source contact hole in the cell array, an etch of the oxide also becomes 12 , So the spacer layer, to the top of the conductive layer 20 carried out. Since this layer is made of polysilicon, the oxide etching stops automatically. Following this is the etching of the trenches 25 in the semiconductor mesa structure, which in 11b is drawn, whereby in the edge region and the conductive layer 20 However, this Halbleitätzung again on the oxide above the mesa structure 14 , in the 5b marked, stops. This stoppage of the etching process occurs automatically because the etching medium that etches polysilicon does not etch or etch oxide at all. It should be noted, however, that in the active region such an automatic termination of the etching process does not take place, but here the etching process must be actively interrupted as the trenches 25 otherwise would extend deeper and deeper into the semiconductor region.

Then the source contact metallization is applied which then covers not only the source region but also all the openings in the spacer layer 12 and in the polysilicon layer 20 fills so that good surface contact between the contact filling, in the 5b not yet introduced, and the layer to be contacted 20 is reached.

Hereinafter, referring to the 6a . 6b . 7 and 8th depicting another implementation in which dummy trench fields are deliberately introduced in the edge region, ie trench fields, as described, for example, in US Pat. B. left in 13a are shown. First, let's look at the 10a and 10b presented the problem, as they are already based on 11d has been discussed, namely that on the chip edge, then, if just a conductive layer 20 provided without special structuring, above the layer 20 a constant high thickness d _{2 is} present, which is typically greater than the thickness of the spacer layer 12 in the cell field, with d ₁ in 10b is shown. This is because in the edge region no intermediate oxide of the spacer layer 12 sink into areas above the Trenche. However, this is very well in the Cell field, since the trenches are filled with conductive material only up to a certain level, this level is well below the mesa top edge. These areas where an intermediate oxide sinks are included 50 in 10b shown. In the trench geometry present in the cell field, intermediate oxide sinks into the trench top regions, whereby the sunken volume is strictly bound to the cell field geometry. As a result, the total intermediate oxide thickness above the trenches, which has the thickness d ₁ , is less than in the chip edge region, which brings about the described problem.

In order to eliminate this problem, in another aspect, trenches in the chip edge region are introduced, which are dimensioned in such a way that a certain and preferably the same amount of intermediate oxide sinks as it sinks into the cell field in the trench top regions. However, in the chip edge area, because of the high gate-drain voltage, each trench should have a thick oxide, that is to say an oxide which has the same thickness as the oxide, that the lower electrode 30 Isolated from the semiconductor in the cell field. In order to sink about the same amount of intermediate oxide in the trenches, the trenches here are formed so broad that the deposited polysilicon, which is the layer 20 forms, and which is also deposited into the Trenche, the trench walls covered and those by the reference sign 50 designated areas for Zwischenoxid- sinking free.

It thereby results over the polysilicon layer 20 at the chip edge about the same intermediate oxide thickness as results in the cell field, which in 6a and 6b has been drawn as d ₁ . This allows the conductive layer 20 be contacted in Chiprandbreich everywhere, either in the gusset 52 , which forms directly above the recessed location or in the area between two gussets, since the maximum thickness of the spacer layer in the chip edge region above the layer 20 also not larger than in the cell field. In the gusset area 52 the layer is even thinner, but this is not a problem, since the oxide etch stops anyway on the polysilicon and possibly even some intermediate oxide from the field 50 etched out again when the contact is placed directly above the trench. However, this is not a problem and rather serves to improve the contact, if this area is filled in the later metallization of edge contact and source contact in the cell field by metal.

In 8th The dark rectangle schematically shows the volume into which the intermediate oxide can flow during annealing, thus reducing the effective inter-oxide thickness on the adjacent mesa. In one embodiment, there is also the contacting of the poly-source material next to the "dummy trench" attached to the edge region.

Of the Contact in the chip edge area will therefore be chosen everywhere where the thickness of the spacer layer is equal to or less than the thickness the spacer layer in the active region, ie in the cell field, is.

Thereby, that the cell geometries, such as trench width, trench depth, The depth of the body, the thickness of the polydicke, the mesawite, etc. are the desired performance of the MOSFET are automatically set above the Cell field a certain intermediate oxide thickness (ZWOX thickness). In contrast to results in the planar chip edge area as it has been shown is, a different, usually thicker Zwischenoxiddicke. There, however, are the poly contacts, so that the problem described arises. These two different intermediate oxide thicknesses are thus not sure to etch through in a single contact hole etch process. By Providing dummy trenches, which are preferably isolated by thick oxide from the semiconductor to the Not endanger voltage resistance will now also be in the chip edge area where the polycontacts are located produces almost the same intermediate oxide thickness, thus all contacts in a process to be able to produce a phototechnology safely. For this become special broader dummy trench structures among the polycontact regions introduced, in which just as much intermediate oxide volume can be sunk, that there again almost the same intermediate oxide thickness as in the cell field is present.

The Trench width can be any size depending on the desired Volume of material to be lowered. The material can be general each common in the semiconductor field be insulating material. Even in the event that two senior Materials to be brought to almost the same thickness, can This principle can be applied, including for z. B. metal or poly webs. The spacer layer can thus be used as an alternative to an insulating layer also a conductive Be layer. In the illustrated examples, one or more poly may be used Polys are present in the dummy trenches, and they can all be at fixed potentials lie or at least up to the polysilicon to be contacted be floating.

Furthermore, the poly regions in the edge trench regions may conform to the trench or may be partially recess etched. The mesa areas between the dummy trench fields can be of fixed size or vary as desired. The Mesaweite can be chosen so small that the Mesagebiete at least partially oxidize together. The trench fields themselves can have a variety of shapes in the layout, eg. As stripes, rectangles, checkerboard pattern, Trenchnadeln, Trenchkrei se or trenchellips. With trench circles or trenchellips, a dummy trench field can be closed layoutet without having to insert tees. In particular, for higher voltage data greater than 40 volts, this can bring particular benefits, since the transistor is finished clean towards the edge. The layout of the contact hole, which is placed at least partially over the dummy trench field, can furthermore have any shapes and sizes, but should preferably be inscribed in the trench field.

In general, a MOSFET contains, in addition to the cell array, at least one further structure in which wider trenches are formed than in the cell array and at least one overlying layer whose layer thickness is reduced by material sinking into these wider trenches compared to a corresponding structure without the trenches. Moreover, the trenches need not necessarily be polysilicon, but the trenches can also be made without being filled with polysilicon just to serve as an oxide sink. Further, regardless of whether the trenches are filled with polysilicon or not, or whether they are merely filled with oxide, if the thickness of the spacer layer in the cell array and the chip edge region are relatively similar, the gusset alone may already be sufficient, as in the gusset 52 the thickness is thinner than usual in the chip edge. In other words, z. B. in the in 6b shown embodiment, a contact directly into the gusset 52 when the thickness of the oxide in the gusset is as large as d ₁ in the cell array, and when the thickness of the spacer layer 12 between two trenches or between two gussets is significantly larger than in the cell field.

Hereinafter, referring to 7 an embodiment shown in which only the poly-gate contact to be contacted and the poly-source is not connected, so remains floating. In particular, the gusset is shown which also serves as a gate poly dip in 7 referred to as. Intermediate oxide is initially taken up by this gate poly dip, so that, since there are several trenches 15 are arranged side by side, between the trenches 15 So at one point 70 the spacer layer is thinner than at the edge area 71 , Depending on the design, the gusset can continue up to the top, as it is in 6 is shown, or the gusset may be at the top of the spacer layer 12 no longer be apparent as it dashed in 7 is drawn.

Nevertheless, the volume of the gate poly-die serves to sink enough intermediate oxide to have a thinner spacer layer between trenches in which inter-oxide has been buried to make contact therewith. The possibilities of contact application are through the boundary lines 72 and 73 hinted at, the contact does not necessarily have to be so broad that he is between 72 and 73 extends, but can also be narrower.

An alternative implementation for contacting the poly-source material in the trenches is in 8th shown. Here is the poly-source material, so the electrode 30 led out to the edge as a conductive layer to be connected 20 to serve, in turn, a connection can be achieved, in the area between the lines 72 and 73 , Again there exists a volume in 8th With 50 is designated, can be sunk in the intermediate oxide, so that in the vicinity of several trenches, a thinner intermediate oxide results than at the edge. The thickness at the point 70 in 8th is thus less than the thickness at one point 71 , It can also be seen that in the in 8th In the embodiment shown, the poly-gate material in the trench is contributed by an external poly-gate material 80 in 8th is disconnected.

When the contacts are placed as it is in 8th through the lines 72 and 73 is shown, and when an oxide etch is performed such that not only the Zwischenoxiddicke 12 is etched through, but also the sunken volume 50 Thus, in this implementation, the poly gate could be shorted to the poly source through the via fill and, for example, placed at source potential. However, this is only of interest for dummy trenches, ie for trenches where the poly gate electrode is not a true gate in the active field. Of course, no short circuit between poly-source and poly-gate can be achieved there. For such a case, however, the structuring of 8th used, namely, when the contact of the layer 20 is fabricated over a semiconductor mesa region such that the contact engages the poly gate 8th not contacted.

10

active Area

11

border area

12

spacer layer

19

dent or gusset

14

mesa

15

trench

16

conductive material

17

gate oxide

18

Semiconductor substrate

19

lateral Boundary point in the active area

20

layer made of conductive material

21

Poly-source or poly-gate contact or contact holes

22

Source contact

23

Gate contact

25

Bulk trenches

26

Source region or emitter area

27

Body region or upper base area

28

Drain region or lower base range

30

lower Electrode or poly-source electrode

31

residual oxide

32

post-oxide

33a

first intermediate oxide

33b

second intermediate oxide

40

Contrast middle class

41

post-oxide at the edge

43

upper Boundary of the spacer layer with varying thickness

45

Further underlying conductive layer

46

Dummy trench at the edge

47

contact site

50

Oxidversenkungsbereiche in the active cell field and in the border area

52

gore

70

Job with thinner spacer layer

71

Job with a thick spacer layer

72

first Border for the contact

73

second Border for the contact

90

step providing the preprocessed substrate

91

step breaking the spacer layer

92

step of the etching the bulk trenches

93

step of metallizing the chip surface

94

step structuring the metallization layer

Claims (30)

A method of manufacturing a semiconductor device comprising the steps of: providing ( 90 ) of a semiconductor substrate ( 18 ) with an active area ( 10 ) and an edge area adjacent to the active area ( 11 ), wherein the active region with conductive material ( 16 ) filled trenches ( 15 ) in the semiconductor substrate, wherein the conductive material in the trenches through an insulating layer ( 17 ) is isolated from the semiconductor substrate, and wherein between two trenches in each case a Halbleitermesastruktur ( 14 ), wherein in the edge region a layer ( 20 ) is formed of the conductive material which is insulated from the semiconductor substrate by an insulating layer and which is short-circuited with the conductive material in the trenches, wherein a spacer layer (12) is formed over the semiconductor substrate. 12 ) is formed, which in the edge region has a varying thickness (d ₂ , d ₁ '); and breaking through ( 91 ) of the spacer layer in the edge region at a selected location ( 21 , and removing at least a portion of the spacer layer in the active region using a common process step, wherein the site ( 21 . 70 . 72 . 73 ) is selected such that, under the condition that the spacer layer in the active region is removed in such a way that at least a part of the semiconductor metastucture ( 14 ) is exposed and the conductive material in the trenches is not exposed, the spacer layer is broken in the edge region to the conductive layer and not to the semiconductor substrate. The method of claim 1, wherein the common Process step has an anisotropic etching, the same affects the active area and the border area. The method of claim 2, wherein the etching is a Combination of a chemical-mechanical polishing and a oxide etch or an oxide etch having no chemical-mechanical polishing. Method according to one of the preceding claims, wherein after the step of breaking through a trench etching ( 92 ) is carried out in the semiconductor mesa structure without covering the location in the edge area. Method according to one of the preceding claims, in which the active region and the edge region are metallized after the step of breaking through ( 93 ) and a resulting metallization layer is subsequently structured ( 94 ) to disconnect a contact of the active area from a contact of the edge area. Method according to one of the preceding claims, in which the spacer layer ( 12 ) has a material which becomes more liquid with increasing temperature and wherein the spacer layer is applied at a temperature at which the material is so fluid that it penetrates into a depression or receives a decreasing thickness towards an edge. Method according to one of the preceding claims, in which the contact layer ( 20 ) is so structured in the edge region that it has an edge at which the contact layer stops, the spacer layer having a thickness ( 43 ) over the contact layer which decreases toward the edge, and wherein the location near the edge is selected so that the spacer layer to the contact layer is broken in the common process. Method according to one of the preceding claims, wherein the contact layer in the edge region at least two adjacent tracks ( 20 ) which are spaced apart from each other, the spacer layer having a thickness transverse to the adjacent webs above the one web towards the other Web and decreases over the other web towards the one web, and wherein the web has a continuous area comprising a part of the one web, a space between the webs and an adjacent part of the other web. Method according to one of the preceding claims, wherein below the contact layer in the edge region a trench ( 46 ) and in which the location is chosen so that it passes over the trench ( 46 ). Method according to one of the preceding claims, at the below the contact layer in the edge region a plurality of trenches is trained, and where the job is chosen that they are in at least one area between two trenches extends. The method of claim 9 or 10, wherein the at least one trench in the edge region wider than the Trenche ( 15 ) is in the active region, and in which a minimum insulation layer thickness in the at least one trench in the edge region is greater than a minimum insulation layer thickness in a trench in the active region. The method of claim 11, wherein a distance between two trenches in the edge area smaller than a distance between two trenches in the active area. Method according to one of Claims 9 to 12, in which the contact layer ( 20 ) has in the edge region a conductive material in the trench which is isolated from the semiconductor substrate. Method according to one of Claims 9 to 13, in which the contact layer ( 20 ) in the edge region a conductive material in the trench, which extends across a semiconductor mesa structure ( 14 ) between an adjacent trench and into the adjacent trench, and which is isolated from the semiconductor substrate by an insulating layer formed in the trenches and on the semiconductor memory structure. Method according to one of the preceding claims, in which the semiconductor component is a MOSFET transistor in which the semiconductor memory structure has a source region ( 26 ) and a body area ( 27 ), in which a channel can be generated, and in which the conductive material ( 16 ) in the trench ( 15 ) represents a gate. Method according to one of claims 1 to 14, wherein the semiconductor device is an insulated gate bipolar transistor, wherein the Halbleitermesastruktur an emitter region ( 26 ) and a body area ( 27 ), which constitutes an upper base region which adjoins a lower base region ( 28 ) and in which the conductive material in the trench is an isolated gate. A method according to claim 15 or 16, wherein a lower part of the trench is a conductive material ( 30 ) provided by the gate ( 16 ), and which is floating or connectable to the source or emitter to effect a field plate function. Semiconductor device having the following features: a semiconductor substrate ( 18 ) with an active area ( 10 ) and an edge area adjacent to the active area ( 11 ), wherein the active region with conductive material ( 16 ) filled trenches ( 15 ) in the semiconductor substrate, wherein the conductive material in the trenches through an insulating layer ( 17 ) is isolated from the semiconductor substrate, and wherein between two trenches in each case a Halbleitermesastruktur ( 14 ), wherein in the edge region a contact structuring is provided which forms a contact layer ( 20 ) formed by the semiconductor substrate ( 18 ), wherein above the contact layer a spacer layer ( 12 ) is formed with varying thickness from point to point (d ₂ , d ₁ '), wherein the spacer layer at one point ( 21 . 70 . 72 . 73 ) is broken in the edge region at least up to the contact layer; and wherein the contact patterning is formed such that, at the location, a thickness of the spacer layer is within a tolerance range smaller than or equal to a thickness of the spacer layer in an area (FIG. 19 ), in which a contact of the semiconductor memory structure in the active region is limited laterally. A semiconductor device according to claim 18, wherein the Tolerance range is less than or equal to 500 nm. Semiconductor component according to one of Claims 18 and 19, in which the contact layer ( 20 ) is so structured in the edge region that it has an edge at which the contact layer stops, the spacer layer having a thickness ( 43 ) over the contact layer, which decreases toward the edge, and wherein the location near the edge is selected so that the spacer layer is broken to the contact layer. Semiconductor component according to one of the claims 18 to 20, in which the contact layer ( 20 ) in the edge region has at least two adjacent webs which are spaced apart from each other, wherein the spacer layer has a thickness which decreases transversely to the adjacent webs over the one web towards the other web and decreases over the other web in the direction of the one web, and wherein the location comprises a continuous area comprising a part of the one lane, a space between the lanes and an adjacent part of the other lane. Semiconductor component according to one of Claims 18 to 21, in which, under the contact layer in the edge region, a trench ( 46 ), and wherein the location is selected to extend over the trench. Semiconductor component according to one of Claims 18 to 22, in which, underneath the contact layer in the edge region, a plurality of trenches ( 46 ), and wherein the location is selected to extend in at least an area between two trenches. Semiconductor component according to Claim 22 or 23, characterized at the at least one trench in the edge region wider than the trenches is in the active area, and in which a minimum insulation layer thickness in which at least one trench is greater in the edge region than a minimum insulation layer thickness in a trench in the active area. A semiconductor device according to claim 23, wherein a Distance between two trenches in the edge area smaller than a distance between two trenches in the active area. Semiconductor component according to one of Claims 23 to 25, wherein the contact layer in the edge region of a conductive material in the trench isolated from the semiconductor substrate. Semiconductor component according to one of Claims 23 to 26, in which the contact layer in the edge region is a conductive material in the trench which extends across a semiconductor memory structure ( 14 ) between an adjacent trench and into the adjacent trench, and which is isolated from the semiconductor substrate by an insulating layer formed in the trenches and on the semiconductor memory structure. Semiconductor component according to one of Claims 18 to 27, in which the semiconductor component is a MOSFET transistor in which the semiconductor memory structure has a source region ( 26 ) and a body area ( 27 ), in which a channel can be generated, and in which the conductive material ( 16 ) represents a gate in the trench. A semiconductor device according to any one of claims 18 to 27, wherein the semiconductor device is an insulated gate bipolar transistor in which the semiconductor memory structure has an emitter region ( 26 ) and a body area ( 27 ), which represents an upper base region, and to a lower base region ( 28 ) and in which the conductive material in the trench is an isolated gate. A semiconductor device according to claim 28 or 29, wherein a lower part of the trench is a conductive material ( 30 ) which is insulated from the gate and which is floating or connectable to the source or the emitter to effect a field plate function.