DE102007003534B4 - Operating, programming and erasing methods for a memory cell, semiconductor device and electronic system - Google Patents

Abstract

An operating method for a memory cell, comprising: applying a first voltage to a first pn junction (214) between a first source / drain region (212) and a substrate portion (230) and to a second pn junction (224) between a second one Source / drain region (222) and the substrate portion (230) such that avalanche breakdown occurs at the respective pn junction (214, 224); and applying a second voltage between a gate electrode (270) and the substrate section (230) in such a way that charge carrier (232) generated by the avalanche breakdown and injected into the substrate section (230) is inserted between the substrate section (230) and the gate electrode (270). arranged memory element to be injected.

Description

Embodiments of the invention relate to an operating method for a memory cell and to methods for programming and erasing a memory cell. Further embodiments relate to an operating method for a storage cell with localized charge storage and semiconductor components and to such comprehensive electronic systems which are suitable for carrying out said methods.

Non-volatile memory cells are usually based on an n-channel MOSFET, in which an insulated memory element is provided between the gate electrode and the channel region of the transistor. For programming the memory cell charge carriers are injected into the memory element. To delete the memory cell, the charge carriers are removed from the storage element or compensated with charge carriers of opposite polarity. The threshold voltage of the transistor is dependent on the charge stored in the memory element. In order to read the memory cell, a voltage is applied to the gate electrode, in which the memory cell is conductive, for example, in the programmed state and in the erased state non-conductive, and the current between the source / drain regions arranged on both sides of the channel region is evaluated.

The storage element of a floating gate cell is typically a conductive layer within the gate electrode stack, which is isolated by a tunnel oxide from the channel region and by a barrier layer from the gate electrode or the control gate. The programming or deletion of the floating gate cells takes place via mechanisms such as Fowler-Nordheim tunneling or hot-carrier injection (eg CHE, channel hot electron).

In trapping-layer-type memory cells, the memory element is a trapping layer of a nonconductive material with trapping sites for charge carriers, such as a silicon nitride layer. The charges are tied to the traps within the trapping layer.

In the case of 2-bit memory cells, the charge carriers are stored in two isolated storage zones, for example a trapping layer. Over the course of the operating life of the memory cell, electrons can accumulate in a central zone between the two memory zones whose distance from the source / drain regions is too great for backturning to the source / drain regions. These so-called excess electrons (overspill electrons) permanently bias the gate electrode.

In the US 6,243,300 B1 describes a method for erasing a 2-bit Trappingschicht memory cell, in which each of the pn junction between the respective source / drain and the channel region is poled in the flow direction. The resulting holes tunnel due to a negative gate voltage in the central channel region in the central zone of the trapping layer and compensate for the accumulated excess electrons there.

The US 6,800,493 B2 refers to neutralization of charge stored in the storage element during the manufacturing process by a wafer level Fowler-Nordheim mechanism.

In the article "A Novel 2-bit / Cell Nitride Storage Flash Memory with Greater Than 1M P / E-Cycle Endurance", Yen-Hao Shih et. al., in IEDM (San Francisco, Calif., USA), pp. 881-884; IEEE, 2004 describes a method of erasing accumulated charge in the trapping layer of a memory cell by means of a p ⁺ -doped gate electrode in conjunction with a negative Fowler-Nordheim reset.

Increasing the number of permissible programming / erasing cycles by injecting holes from the substrate is discussed in the article "Extending endurance of NROM memories to over 10 million programs / erase cycles" by Yakov Roizin et. al., 21st Non-Volatile Semiconductor Memory Workshop, (Montreal, CA, USA), pp. 74-75, IEEE 2006. For this purpose, the layer thickness of the tunnel oxide is reduced and the upper barrier layer is formed as an aluminum oxide layer or a p ⁺ -doped gate electrode is provided.

The US Pat. No. 6,487,121 B1 refers to a programming method for a 2-bit trapping layer memory cell in which the injection profiles of the electrons injected in the programming process and the holes injected during the erase process are matched to one another by applying an additional vertical field.

According to one in the US 6,930,928 B2 Prior to the actual program / erase cycle, preprogramming of a nonvolatile memory cell by means of Fowler-Nordheim tunnels is performed. Preprogramming prevents more charge in the trapping layer from being compensated or removed during the erase cycle than was injected into the trapping layer in the previous programming cycle.

The US 6,490,205 B1 relates to a method for deleting a 2-bit trapping layer memory cell in which the pn junctions between the source / drain during the erase operation Regions of the memory cell and the surrounding substrate trough is biased in the reverse direction with a voltage which is smaller than the breakdown voltage of the pn junction. The substrate bias is intended to amplify the lateral electric field within the channel region, thereby increasing the number of hot holes generated within the memory cell and accelerating the erase process altogether.

The US 6,744,675 B1 describes a method of programming a SONOS memory cell. After the actual programming process, a weak erase pulse is provided, in the course of which flat-seated charges in the lower, oriented to the substrate portion of the trapping layer are removed.

The US Pat. No. 6,891,760 B2 refers to a method for deleting a 2-bit trapping layer memory cell. With a suitable substrate bias, excess electrons are to pass into the substrate.

In the US Pat. No. 6,438,031 B1 For example, a programming method for 2-bit trapping-layer memory cells is described in which the application of substrate bias during the programming operation reduces the electric field strength near the source / drain regions. Due to the reduced impact ionization in these regions, the number of such electrons that can be injected in the region of the middle zone of the trapping layer is reduced.

The US Pat. No. 6,456,531 B1 refers to a programming method for a 2-bit trapping layer memory cell in which a blocking voltage near the breakdown voltage is applied between the source / drain regions and the substrate during the programming operation, around the injection profiles of the electrons injected in the programming process and during the erase process Align injected holes to each other.

In the article "Simultaneous Hot-Hole Injection at Drain and Source for Efficient Erase and Excellent Endurance in SONOS Flash EEPROM Cells", Myung Kwan Cho and Dae M. Kim, IEEE Electron Device Letters, Vol. 4, pp. 260-262, 2003 an erase method for SONOS memory cells is described. Hot holes are simultaneously injected into the trapping layer on both source / drain sides by a hot hole injection (HHI) mechanism, to which the substrate is biased.

The invention is defined in the independent claims. Further developments are the subject of the dependent claims.

The US 6,760,258 B2 describes a programming or erasing method for floating gate cells, in which the required charge carriers are each provided by an avalanche breakdown between one of the source / drain regions and the channel region.

The invention has for its object to provide improved methods of operation, such as for erasing and programming, of memory cells available that counteract the accumulation of excess electrons. The object-solving operating methods are specified in claims 1 and 12, such a programming method in claim 7, an erasing method in claim 8, a method enabling such a semiconductor device in claim 20 and an electronic system with such a semiconductor device in claim 29. Advantageous developments emerge from the respective subclaims.

One embodiment of the invention relates to an operating method for a non-volatile memory cell having two source / drain regions formed in a semiconductor substrate and a substrate portion formed between the two source / drain regions. The substrate portion adjoins a substrate surface of the semiconductor substrate. Above the substrate portion, a memory element of the non-volatile memory cell is arranged, which is isolated from the substrate portion by a first barrier layer. A second barrier layer isolates the memory element from a gate electrode via which the memory cell is addressed.

The two source / drain regions have a doping of a first conductivity type and the substrate portion has a doping of a second conductivity type opposite to the first conductivity type.

At a pn junction formed between one of the source / drain regions and the substrate section, a first voltage is applied such that avalanche breakdown occurs at the pn junction. For this purpose, in the reverse direction of the pn junction, at least the breakdown voltage of the pn junction is applied or a corresponding current impressed. The respective minority carriers are accelerated by the electric field in the space charge zone in such a way that electron / hole pairs are generated there. In the case of an n ⁺ -doped source / drain region and a p-doped substrate section, high-energy holes subsequently pass into the substrate section. The energy of the injected holes is sufficient to generate further electron / hole pairs there.

Substantially simultaneously or immediately after the application of the first voltage, a second voltage is applied between the gate electrode and the substrate section which is sufficiently large to deflect charge carriers generated in the substrate section as a result of the avalanche breakdown in the direction of the gate electrode. The energy of the charge carriers is sufficient to pass through the lower barrier layer into the storage element. For example, the gate electrode is negatively biased relative to the substrate portion, so that holes are injected into the memory element. The holes are generated by operating the pn junctions in the reverse direction (RDHI, reverse diode hole injection).

The avalanche breakdown provides a large number of electrons and holes for programming or erasure in a short time, resulting in a comparatively fast injection of electrons into the memory element and a correspondingly fast programming or erasing process.

If the first voltage is applied in each case between the two source / drain regions of the memory cell on the one hand and the substrate portion on the other hand, or if a current is injected via both pn junctions, so that both pn junctions are operated above the breakdown voltage in the reverse direction, then they are distributed of the avalanche breakdown injected into the substrate portion or there in the sequence generated charge carriers over the entire channel length. For example, for 2-bit trapping layer memory cells wired according to the virtual ground concept, a uniform-effect erase or refresh procedure results.

The breakdown voltage of a pn junction depends on the width of the space charge zones and thus on the doping and doping profiles of the source / drain regions and of the substrate section. The doping and doping gradients are selected, for example, such that a field strength of between 0.3 and 1.2 MV / cm results in the breakdown.

According to a possible embodiment, the source / drain regions have an n-type doping of about 10 ¹⁹ cm ^-3 and the substrate portion has a p-type doping of about 10 ¹⁷ cm ^-3 .

Another embodiment of the invention relates to a programming method for a nonvolatile memory cell. At least one of the pn junctions between one of the source / drain regions and a substrate section adjoining the source / drain regions, a first voltage is applied such that avalanche breakdown occurs at the pn junction. For this purpose, a voltage greater than or equal to the breakdown voltage of the pn junction is applied in the reverse direction of the pn junction. Substantially simultaneously or immediately thereafter, a second voltage is applied between the gate electrode of the memory cell and the substrate portion such that charge carriers generated as a result of the avalanche breakdown are injected into a memory element located between the substrate portion and the gate electrode and insulated from both. The memory element is electrically charged or discharged and the memory cell programmed.

When the second voltage of negative polarity is applied between the gate electrode and the substrate portion, so that the gate electrode is negatively biased with respect to the substrate portion, holes are injected into the memory element.

When the second voltage of positive polarity is applied between the gate electrode and the substrate portion, so that the gate electrode is positively biased with respect to the substrate portion, electrons are injected into the memory element.

Another embodiment of the invention relates to an erasing method for a nonvolatile memory cell. A first voltage is applied between one or both source / drain regions of the nonvolatile memory cell on the one hand and a substrate section of a semiconductor substrate adjoining the source / drain regions in such a way that the pn formed between the source / drain regions and the substrate section is applied Transitions each one avalanche breach occurs. For this purpose, the substrate section is negatively biased with respect to the source / drain regions with a voltage which corresponds at least to the breakdown voltage of the pn junction.

Between the gate electrode of the memory cell and the substrate portion, a second voltage is applied so that charge carriers generated due to the avalanche breakdown are accelerated toward the gate electrode, thereby being injected into a memory element disposed between the substrate portion and the gate electrode, extending from the substrate portion as well as from the substrate portion Gate electrode is electrically isolated. In this case, a charge stored in the memory element is compensated or the memory element is charged and the memory cell is erased.

Another embodiment of the invention relates to a method of operating a non-volatile memory cell with localized charge storage. The memory cell comprises two separate from each other by a substrate portion and formed in a semiconductor substrate source / drain regions. The source / drain regions have a doping of a first conductivity type and the substrate section which spaces the two source / drain regions comprises a doping of a second conductivity type opposite to the first conductivity type. The first barrier layer insulates the substrate portion from a memory element of the memory cell. A second barrier layer isolates the memory element from a gate electrode for addressing the memory cell. The memory element has two memory zones which are isolated from one another and can be controlled separately from one another and which are each oriented to one of the two source / drain regions. In a central zone between the two storage zones, owing to previous programming cycles, there may be an accumulation of excess electrons which can no longer be removed or compensated for by conventional extinguishing methods. The threshold voltage of the erased memory cell is permanently shifted in the direction of the programmed.

According to the present embodiment, a first voltage is applied to the pn junctions between the first and the second source / drain region on the one hand and a substrate portion adjoining the source / drain regions on the other hand in the reverse direction such that in each case at the pn junctions an avalanche breakdown takes place. In this case, electron / hole pairs are generated in the space charge zone of the respective pn junction by accelerated charge carriers.

For example, if the source / drain regions are n-doped and the substrate portion is p-doped, then the holes created in the space charge region are injected into the substrate portion. The holes have sufficient energy to generate further electron / hole pairs there by impact ionization. There is an accumulation of ionized electron / hole pairs in the substrate section. A second voltage of negative polarity is applied at the same time or immediately thereafter between the gate electrode of the memory cell and the substrate section, so that the holes resulting directly or indirectly from the avalanche breakdown in the substrate section are deflected in the direction of the gate electrode and into an area between the substrate section and the gate electrode arranged memory element of the memory cell are injected. The holes are injected into the storage element over the entire channel length between the two source / drain regions.

Any remanent negative charge in the central zone between the storage zones is at least compensated by the positive charge of the holes. The threshold voltage reaches at least the original value or a value below it, depending on the duration of the voltage pulses. The maximum allowable operating life of the memory cell or a semiconductor device based on this memory cell type is increased. The maximum possible number of program / erase cycles (cycle stability) is significantly increased. Reducing the load on the memory cell as a result of the cleared erase pulses also improves the data retention in such a semiconductor device.

For example, the first voltage is chosen so that the field strength at the pn junction is between 0.3 and 1.2 MV / cm, but in any case sufficient to trigger avalanche breakdown.

The first and second voltages may be applied substantially synchronously or simultaneously for a period of about 10 msec to 50 msec. Optionally, the application of the first and second voltage is extended or repeated until a threshold voltage determined for the memory cell is equal to or less than a predefined value. The predefined value is for example the original output value of the threshold voltage, which is determined at the beginning of the life of the memory device.

According to one embodiment, the refreshing of the memory element is performed even at the wafer level and before the first use of the memory in a product-specific application in order to compensate for a process-related accumulation of charge carriers in the memory layer.

According to another embodiment, the number of erase pulses required for a complete erase cycle is determined in each erase process and compared with a predetermined limit for the number of erase pulses. If the just required number of erase pulses exceeds the limit value, then the memory cell or the memory element is "refreshed" or reset by applying the first and second voltage.

According to a further embodiment, the refresh of the memory element is in each case carried out cyclically after a predetermined number of programming cycles. For this purpose, a current counter reading for programming operations is determined in each case before or after executing a programming operation. If the current counter reading exceeds a predetermined limit counter reading for the number of programming cycles, then the memory element is refreshed by applying the first and second voltages and the counter reading for programming cycles is reset.

A semiconductor device according to a further embodiment of the invention comprises memory cells each having a first and a second source / drain region, a substrate section formed between the two source / drain regions, a memory element isolated from the substrate section, and a gate electrode isolated from the memory element. The semiconductor device further comprises a first voltage supply unit which is capable of generating a first voltage suitable for triggering the avalanche breakdown between the source / drain regions on the one hand and the substrate portion or impressing a corresponding current, and a second voltage supply unit connected between the gate electrode and the substrate portion one capable of injecting the generated by the avalanche charge carrier into the memory element is capable of generating a second voltage suitable. Such a semiconductor device is advantageously suitable for the above-mentioned operating methods.

The source / drain regions and the substrate section may be formed in the same semiconductor substrate. The substrate portion may be isolated from the memory element by a first barrier layer and the memory element may be insulated from the gate electrode by a second barrier layer.

The memory element may be a conductive floating gate or a non-conductive trapping layer. The non-conductive trapping layer may, for example, have at least two spatially separated and mutually isolated storage zones whose charge states can be controlled independently of one another. If charge carriers are also injected into the storage element between the two memory zones during regular programming / erasing, this semiconductor device is advantageously suitable for the abovementioned operating method for a non-volatile memory cell with localized charge storage, which makes possible the compensation of these charge carriers.

In the following, embodiments of the invention, which are connected via the common concept of the carriers provided by means of avalanche breakdown, and their advantages are explained in more detail with reference to the figures. Show it:

1A - 1B FIG. 2: schematic cross-sectional views of a non-volatile 2-bit trapping layer memory cell for explaining an operating method according to an embodiment; FIG.

2 FIG. 2 is a schematic cross-sectional view of a 2-bit trapping-layer memory cell for explaining a method of operating a non-volatile memory cell according to another embodiment; FIG.

3A - 3B : schematic cross-sectional representations of a floating gate memory cell for explaining a programming or erasing method according to another embodiment;

4 FIG. 4 is a schematic flowchart for explaining a method of operating a non-volatile localized charge storage and adaptive refresh cycle memory cell according to another embodiment; FIG.

5 FIG. 12 is a schematic flow diagram of a method of operation for a non-volatile memory cell with localized charge storage and cyclic refresh cycles, according to another embodiment; FIG.

6 FIG. 4 is a diagram showing the dependence of the number of required erase pulses on the number of program and refresh cycles for a memory cell according to another embodiment; FIG.

7 FIG. 2 is a simplified schematic block diagram of a semiconductor device according to another embodiment; FIG.

8th FIG. 2 is a schematic block diagram of a data storage system according to another embodiment; FIG.

9 FIG. 3 is a simplified flowchart for a method of operating a nonvolatile memory cell according to an embodiment of the invention; FIG.

10 FIG. 5 is a simplified flowchart for a programming method for a nonvolatile memory cell according to an embodiment of the invention; FIG.

11 FIG. 2 is a simplified flowchart for a nonvolatile memory cell erasing method according to an embodiment of the invention; FIG. and

12 FIG. 2: a simplified flowchart for a method of operation for a non-volatile memory cell with localized charge.

The 1A and 1B refer to an operating method for a 2-bit trapping layer memory cell 199 , The memory cell 199 includes two each, for example, in a semiconductor substrate 100 trained source / drain regions 112 . 122 , The two source / drain regions 112 . 122 are through a substrate section 130 spaced apart. The substrate section 130 is, for example, a p-doped well in the semiconductor substrate 100 , To optionally selected areas of the semiconductor substrate from each other and other p-doped areas independently can bias the p-doped well into an n-doped well 102 be embedded. For example, an entire cell array, individual segments of a cell array or even a circuit periphery may share a common p-doped well 130 include. The two source / drain regions are n ⁺ doped in this example. The substrate section 130 adjoins the substrate surface 110 of the semiconductor substrate 100 at. Above the substrate section 130 within the conductive state of the memory cell between the two source / drain regions 112 . 122 a conductive channel is formed is a storage element, such as a trapping layer 150 arranged through a first barrier layer 140 from the substrate section 130 is isolated.

Opposite a gate electrode 170 is the trapping layer 150 through a second dielectric barrier layer 160 electrically isolated. The first and second dielectric barrier layers 140 . 160 are for example silicon oxide layers. The second barrier layer 160 can also be formed as a layer system with layers of different dielectric materials. The gate electrode 170 comprises approximately at least in one of the second barrier layer 160 subsequent section a polysilicon layer or a metal layer. The trapping layer 150 according to this embodiment is a non-conductive layer with traps for electrical charges, such as a silicon nitride layer or other non-conductive layer with deposits of conductive material. The layer thickness of the first barrier layer 140 is about 2 to 10 nm, that of the second barrier layer 160 5 to 20 nm and that of the trapping layer 150 about 2 to 10 nm.

The trapping layer 150 has two each to one of the source / drain regions 112 . 122 oriented storage zones 151 . 152 on, which are isolated from each other and independently controllable. When programming one of the bits of the memory cell 199 for example, within the storage zone 151 enriched negative electric charge, for example, through from the right source / drain region 122 exiting and towards the left source / drain region 112 accelerated, "hot" electrons, with sufficient energy in the left storage zone 151 through the lower barrier layer 140 tunnels and at trapping points within the storage zone 151 be fixed. The erasure is done, for example, by Fowler-Nordheim tunneling of the electrons to the left source / drain region 112 or by, for example by band-to-band tunneling, to compensate for "hot" holes in the storage zone 151 be injected.

Due to parasitic effects are also present in a central zone 153 between the two storage zones 151 . 152 so-called excess electrons (overspill electrons) 133 injected, whose charge is not fully compensated by conventional Löschálgorithmen, so that there is a continuous shift of the threshold voltage of the memory cell to higher values.

By means of a first voltage supply unit 181 is in the course of a refresh cycle between the source / drain regions 112 . 122 on the one hand and the substrate section 130 on the other hand, a positive voltage is applied and each between the substrate sections 130 and the source / drain regions 112 . 122 trained pn transitions 114 . 124 operated in the reverse direction (reverse bias). The applied voltage corresponds at least to the breakdown voltage of both pn junctions 114 . 124 , Inside of the pn-transitions 114 . 124 extending space charge zones 116 . 126 With a sufficient width of the space charge zones and sufficiently large electric field strength, the minority charge carrier which determines the reverse current will absorb sufficient energy to generate an electron / hole pair in the event of a collision with the thermally disordered grid. The result is an avalanche-like increase in the number of charge carriers. It goes in the space charge zones 116 . 126 generated holes 132 in the negatively biased substrate section 130 over there and generate there by impact ionization more electron / hole pairs.

According to 1B is a second power supply unit 182 provided, in this embodiment, the gate electrode 170 against the substrate portion 130 negatively biased. Due to the resulting electric field, those due to avalanche breakdown along the pn junctions become 114 . 124 in the substrate section 130 passed or generated there holes 132 in the direction of the memory element 150 deflected. With sufficient voltage between the gate electrode 170 and the substrate portion 130 tunnels a part of the holes 132 between the two storage zones 151 . 152 through the lower barrier layer 140 and compensates for the charge between the storage zones 151 . 152 fixed excess electrons 133 ,

Applying the first voltage across the first voltage delay unit 181 and a second voltage across the second voltage delay unit 182 is largely synchronous.

Instead of the two voltage delay units 181 . 182 three voltage supply units with common reference potential can be provided. The first power supply unit 181 may be formed such that a corresponding current is impressed on the pn junctions.

The 2 shows a memory cell 299 , their first and second source / drain region 212 . 222 to a first power supply unit 281 , whose gate electrode 270 to a second power supply unit 282 and their two source / drain regions 212 . 222 spaced apart substrate portion 230 to a third power supply unit 283 are connected. The power supply units 281 . 282 . 283 generate voltages referenced to a common reference potential.

In this case, the first voltage supply unit is capable of delivering a first voltage pulse which is positive relative to the reference potential and having a length of, for example, between 10 ms and 50 ms, approximately 20 ms, and a voltage of, for example, 3 to 5 volts, approximately 4 volts , The second voltage supply unit is capable of delivering a negative voltage pulse of -8 to -12 volts, approximately -10 volts, which is largely synchronized with the positive first voltage pulse, at least for a period of 10 to 50 ms. The third power supply unit 283 is capable of producing a third voltage pulse largely synchronized with the other voltage pulses, for example approximately -4 volts and a duration of approximately 10 ms to 50 ms. The voltages are chosen so that both a sufficient drain avalanche drain or source-to-substrate voltage, as well as a suitable potential difference, z. B. a sufficiently positive for the injection of holes, between substrate and gate.

The three voltage pulses become approximately synchronous with each other at the gate electrode 270 , the source / drain regions 212 . 222 and to the substrate portion 230 created. The between the n ⁺ -doped source / drain regions 212 . 222 and the p-doped substrate portion 230 trained pn transitions 214 . 224 are applied in the reverse direction with a voltage corresponding to at least their breakdown voltage. Doing so in the along the pn junctions 214 . 224 trained space charge zones 216 . 226 Electron / hole pairs formed and holes 232 in the negatively biased substrate section 230 injected. Part of the holes 232 is in the direction of the opposite to the substrate portion 230 negatively biased gate electrode 270 deflected and occurs at full length of the distance between the two source / drain regions 212 . 214 through the first barrier layer 240 , This will both charges in the storage zones 251 and 252 as well as fixed charges 233 between the two storage zones 251 . 252 the trapping layer 250 compensated. The second barrier layer 260 prevents further tunneling of the charge carriers to the gate electrode 270 ,

The 3A to 3B refer to a programming or erasing method for a floating gate memory cell 399 , The method is illustrated for explanation in two figures. In fact, both steps are largely synchronized. The memory cell 399 includes two source / drain regions 312 . 322 which are in a semiconductor substrate 300 are formed as n ⁺ -doped regions or impurity regions. The two source / drain regions 312 . 322 are through a substrate section 330 spaced apart. Between the source / drain regions 312 . 322 each yield pn transitions 314 . 324 , The two source / drain areas 312 . 322 spaced substrate portion 330 forms a substrate surface in sections 310 of the semiconductor substrate 300 out. Above the substrate section 330 is between the two source / drain regions 312 . 322 For example, a floating gate 350 provided by a on the substrate surface 310 overhead tunnel oxide 340 from the semiconductor substrate 300 is spaced. The tunnel oxide 340 is typically a silicon oxide layer with a thickness of 2 to 8 nm. The floating gate 350 is, for example, a conductive layer of doped polysilicon with a thickness of up to several 10 nm and is formed by a second barrier layer 360 from the gate electrode 370 isolated.

According to 3A is by means of a first power supply unit 381 the substrate section 330 negative against the right source / drain region 322 biased. The amount of voltage applied is at least the breakdown voltage of the pn junction 324 , In the process along the pn junction 324 extending space charge zone 326 become electrons / hole pairs 332 . 331 generated, with the holes 332 in the negatively biased substrate section 330 transgressed.

According to 3B is powered by a second power supply 382 between the gate electrode 370 and the substrate portion 330 a second voltage is applied to the gate electrode 370 opposite the substrate portion 330 negatively biased. The amount of the second voltage is sufficiently high to be in the substrate portion 330 passed or generated there in the secondary effect holes 332 through the first barrier layer 340 to let happen. The holes 332 enter the floating gate 350 over and change the threshold voltage of the memory cell 399 ,

If the gate electrode is positively biased relative to the substrate section, electrons generated in the substrate by impact ionization can likewise pass into the floating gate.

The 4 relates to an embodiment of an operating method for operating a non-volatile memory cell with located Charge storage, in which a drift of the threshold value of the memory cell is determined directly or indirectly and, depending on the magnitude of the deviation from a standard value, the memory cell is refreshed in the manner described above.

From a sequence control of the semiconductor device having such a memory cell, there is a delete call 402 , The initialization follows 404 a counter that registers the number of erase pulses executed within the respective erase call. The memory cell or one bit of the memory cell is supplied with an erase pulse 406 and the erase pulse counter increments 408 , Subsequently, it is checked 412 whether the memory cell or the bit of the memory cell to be erased has actually been erased. Is the result of this review 412 negative, more erase pulses are applied 406 and for each applied erase pulse, the erase pulse counter is incremented 408 , Will in the course of review 412 it is checked that the memory cell is actually erased 422 whether the number of erase pulses has exceeded a predetermined pulse limit. In the event that the pulse limit has actually been exceeded, the charge of the excess electrons in the storage element will be replaced by a refresh cycle 424 comprising leveling the application of the first and second voltage as described above and thereby "refreshing" or reverting the threshold voltage of the memory element of the memory cell.

Through an optional regular program / erase cycle 426 The charge injected during refreshment into the storage zones is removed. The deletion procedure will then be terminated 430 ,

The 5 refers to a flowchart for a method of operation for a non-volatile memory cell with localized charge storage, in which the memory element is refreshed cyclically.

From a program sequence control in a memory cell having semiconductor device is a programming call 502 , Before the actual programming start is checked 512 whether the number of write cycles already executed is greater than a limit cycle number. If this is not the case, the actual programming process follows immediately 532 , Is the result of the review 512 positive, the charge in the storage element is leveled by applying the first and second voltages as described above 522 and thereby the memory cell "refreshed". The counter is then reset for the write cycles since the last refresh 524 , This is followed by the regular programming cycle 532 , After the programming process, the counter for the already executed write cycles is incremented 534 , and then stop programming 536 ,

The 6 shows a diagram 600 to illustrate the relationship between the number of erase pulses required per erase with the number of write cycles in response to refresh pulses performed between the write cycles 601 . 602 . 603 . 604 , From the diagram 600 shows that averaged over several memory cells after every 10,000 write cycles on average about 7 erase pulses are required to completely erase the memory cells. After several 10,000 write cycles, the number of pulses required increases to 17. After a second refresh cycle 602 of the type described above, the number of erase pulses required initially drops below 13 and after another refresh cycle 603 after 100,000 write cycles again to less than 11. Through a fourth refresh cycle 604 After several 100,000 write cycles, the number of erase pulses required for a complete erase operation can be permanently reduced to less than 10 again.

The so-called cyclo-strength of such memory cells is significantly increased. Due to the lower stress in the regular programming or erasing procedures, the data retention in the memory cell is also significantly improved.

The 7 is a simplified block diagram of a semiconductor device 700 according to another embodiment.

The semiconductor device 700 includes to a memory cell array 710 arranged non-volatile memory cells 711 which are arranged, for example, in a "virtual ground array". The memory cells 711 become over with the gate electrodes of the memory cells 711 connected word lines 713 addressed. The data intended for storage or that from the memory cells 711 data read out are over bit lines 712 each transmitted to the source / drain regions of the memory cells 711 are connected. The selection of bit lines 712 via a bit line selector 720 , The addressing of the word lines 713 via a word line selection device 730 ,

The potential of the gate electrodes of the memory cells 711 is from one with the word line selector 730 connected word line power supply unit 731 generated, which provides for the reference to a reference potential voltage of about -10 volts for refreshing. The potential on the bit lines is from one with the bit line selector 720 connected bit line power supply unit 721 which is capable of generating a voltage of about +4 volts with respect to the reference potential for refreshing the memory cells. A substrate power supply unit 741 provides the substrate portions, respectively, disposed between the source / drain regions, typically portions of a p-doped well embedded in an n-doped well (triple well) having a substrate potential for refresh with respect to the reference potential -4 volts. The substrate power supply unit 741 may also be formed as a current source, which impresses a constant current between the substrate and about the reference potential. The impressed current flows as a reverse current through the pn junctions of the associated memory cells and is chosen so that the selected pn junctions are operated in the breakthrough. A control unit 750 controls the power supply units 721 . 731 . 741 depending on the procedure to be performed, such as writing, reading, deleting or refreshing.

The 8th shows an electronic system 800 , The system 800 has a semiconductor device 802 with memory cells 804 on. The memory cells each have a first and a second source / drain region and a substrate section formed between the two source / drain regions. A first voltage supply unit is capable of generating a first voltage suitable for triggering avalanche breakdown between the source / drain regions and the substrate portion, on the other hand.

The system 800 is for example a memory card, a digital camera, a mobile phone, an audio system, a video system, a computer system or a part thereof, such as a memory module, a graphics card or a mobile data carrier with an interface for connection to one of said systems.

The 9 FIG. 10 is a flowchart illustrating a method of operating a memory cell, such as a floating gate or trapping layer memory cell. The method includes the operation 900 at least one reverse pn junction above the breakdown voltage and biasing 902 the gate electrode opposite to the substrate. An avalanche breakdown occurs at the pn junction, resulting in holes in a p-doped substrate and electrons in an n-doped substrate. The respective charge carriers that have entered the substrate can generate additional electron / hole pairs by means of collision. Depending on the polarity of the gate electrode bias voltage with respect to the substrate, electrons or holes are injected into a memory element disposed between the substrate and the gate electrode. Operating the reverse pn junction 900 or the biasing of the gate electrode 902 is essentially the same time.

The 10 refers to a programming method for a, e.g. B. nonvolatile, memory cell. At least one of the pn junctions of the memory cell is reverse biased above the breakdown voltage 904 , The gate electrode is biased against the substrate in this way 906 in that the charge carriers required for programming are injected into a storage element arranged between the gate electrode and the substrate. Operating 904 the reverse pn junction and biasing 906 the gate electrode occurs substantially simultaneously.

The 11 refers to an erasure method for a, e.g. B. nonvolatile, memory cell. One of the pn junctions or both pn junctions are reverse biased above the breakdown voltage 908 , The gate electrode is biased against the substrate in this way 910 in that the charge carriers required for erasing the nonvolatile memory cell are injected into a memory element arranged between the gate electrode and the substrate.

The 12 is a schematic flow diagram illustrating an operating method for a, z. Non-volatile memory cell with localized charge storage. Both pn junctions of the memory cell are operated in the reverse direction above the breakdown voltage 912 , The gate electrode is positively biased against the substrate 914 whereby holes resulting from the avalanche breakdown are injected into a storage element arranged between the gate electrode and the substrate, where they compensate the charge of excess electrons. Operating the reverse pn junctions and positively biasing the gate electrode 912 . 914 is largely simultaneous. The operating method corresponds to a refresh cycle that is performed in addition to the actual erase cycle.

Claims (30)

A method of operating a memory cell, comprising: applying a first voltage to a first pn junction ( 214 ) between a first source / drain region ( 212 ) and a substrate section ( 230 ) as well as to a second pn junction ( 224 ) between a second source / drain region ( 222 ) and the substrate portion ( 230 ) such that at the respective pn junction ( 214 . 224 ) an avalanche breach occurs; and applying a second voltage between a gate electrode ( 270 ) and the substrate portion ( 230 ) such that generated by the avalanche breakdown and in the substrate section ( 230 ) injected charge carriers ( 232 ) in between the substrate portion ( 230 ) and the gate electrode ( 270 ) are injected memory element. A method according to claim 1, characterized in that the first voltage of at least the breakdown voltage of the first pn junction ( 214 ) corresponds. A method according to claim 1, characterized in that the first voltage is selected so that at the respective pn junction ( 214 . 224 ) gives a field strength of at least 0.3 MV / cm. A method according to claim 1, characterized in that the first voltage is selected so that at the respective pn junction ( 214 . 224 ) gives a field strength of at most 1.2 MV / cm. Method according to claim 1, characterized in that the respective source / drain region ( 212 . 222 ) a doping of 5 × 10 ¹⁸ to 2 × 10 ¹⁹ cm ^-3 and the substrate portion ( 203 ) have a doping of 5 × 10 ¹⁶ to 2 × 10 ¹⁷ cm ^-3 . A method according to claim 1, characterized in that the first and the second voltage are applied simultaneously. Programming method for a memory cell ( 399 ) comprising: applying a first voltage to pn junctions ( 314 . 324 ) between a first source / drain region ( 312 ) and one to the first source / drain region ( 312 ) Subsequent substrate section ( 330 ) as well as to a second pn junction ( 324 ) between a second source / drain region ( 322 ) and the substrate portion ( 330 ) such that at the pn junctions ( 314 . 324 ) an avalanche breach occurs; and applying a second voltage between a gate electrode ( 370 ) and the substrate portion ( 330 ) in such a way that charge carriers generated by the avalanche breakdown ( 332 ) in between the substrate portion ( 330 ) and the gate electrode ( 370 ) are injected, wherein the memory cell ( 399 ) is programmed. Extinguishing method for a memory cell ( 399 ) comprising: applying a first voltage to pn junctions ( 314 . 324 ) between a first source / drain region ( 312 ) and one to the first source / drain region ( 312 ) Subsequent substrate section ( 330 ) as well as to a second pn junction ( 324 ) between a second source / drain region ( 322 ) and the substrate portion ( 330 ) such that at the pn junctions ( 314 . 324 ) an avalanche breach occurs; and applying a second voltage between a gate electrode ( 370 ) and the substrate portion ( 330 ) in such a way that charge carriers generated by the avalanche breakdown ( 332 ) in between the substrate portion ( 330 ) and the gate electrode ( 370 ) are injected, wherein the memory cell ( 399 ) is deleted. Method according to one of claims 7 or 8, characterized in that holes are injected into the storage element by applying the second voltage with negative polarity. Method according to one of claims 7 or 8, characterized in that electrons are injected into the storage element by applying the second voltage with positive polarity. Method according to one of claims 7 to 10, characterized in that the first and the second voltage are applied simultaneously. A method of operating a memory cell with localized charge storage, comprising: applying a first voltage to pn junctions ( 214 . 224 ) between a first ( 212 ) and a second ( 222 ) Source / drain region on the one hand and one of the source / drain regions ( 212 . 222 ) Subsequent substrate section ( 230 ) on the other hand in the reverse direction such that at the pn junctions ( 214 . 224 ) an avalanche breach occurs; and applying a second voltage between a gate electrode ( 270 ) and the substrate portion ( 230 ) such that holes generated by the avalanche breakdown ( 232 ) in between the substrate portion ( 230 ) and the gate electrode ( 270 ) are memory element of the memory cell injected. A method according to claim 12, characterized in that through the injected holes between two storage zones ( 251 . 252 ) stored negative charges ( 233 ) are compensated. A method according to claim 12, characterized in that the first voltage of at least the higher breakdown voltage of the two pn junctions ( 214 . 224 ) corresponds. A method according to claim 12, characterized in that the first voltage is chosen so that at the pn junctions ( 214 . 224 ) gives a field strength between 0.3 and 1.2 MV / cm. A method according to claim 12, characterized in that the first and second voltages are applied substantially synchronously and for a period of 10 to 50 ms. A method according to claim 12, characterized in that the application of the first and second voltage is repeated until a threshold voltage of the memory cell ( 299 ) is equal to or less than a predetermined value. Method according to Claim 12, characterized by determining a current threshold value of the memory cell ( 299 after executing an erase operation; and performing application of the first and second voltages when a predetermined threshold limit is exceeded by the current threshold. A method according to claim 12, characterized by Determining a current count for programming operations before or after performing a program operation; and Executing the application of the first and second voltage and resetting the count when exceeding a predetermined limit count by the current count. Semiconductor device ( 700 ) having memory cells ( 711 ), each comprising: a first and a second source / drain region ( 212 . 222 ); and one between the two source / drain regions ( 212 . 222 ) formed substrate portion ( 230 ); a first power supply unit ( 741 ), one for triggering an avalanche breakthrough between the source / drain regions ( 212 . 222 ) on the one hand and the substrate section ( 230 ) on the other hand capable of generating suitable first voltage; and a bit line selection device ( 720 ) having the first voltage at each of the first and second source / drain regions ( 212 . 222 ) a subset of the memory cells ( 711 ) connected bitlines ( 712 ) can switch. Semiconductor component according to claim 20, characterized in that the memory cells in each case one of the substrate portion ( 230 ) isolated memory element and a memory element isolated from the gate electrode ( 270 ); and the semiconductor device has a second voltage supply unit ( 731 . 741 ), which between the gate electrode ( 270 ) and the substrate portion ( 230 ) one for injecting the charge carriers generated by the avalanche breakdown ( 232 ) is capable of generating in the memory element suitable second voltage. Semiconductor component according to Claim 20, characterized in that the first voltage supply unit ( 741 ) can be operated as a current source and is able to impress a constant reverse current in pn junctions of selected memory elements. Semiconductor component according to Claim 21, characterized in that the memory cells each have a substrate section ( 230 ) isolating from the memory element first barrier layer ( 240 ) exhibit. Semiconductor component according to Claim 21, characterized in that the memory cells each have a memory element from the gate electrode ( 270 ) insulating second barrier layer ( 260 ) exhibit. Semiconductor component according to Claim 21, characterized in that the memory elements are each in the form of a conductive floating gate ( 350 ) are formed. Semiconductor component according to claim 21, characterized in that the memory elements each as a non-conductive trapping layer ( 250 ) are formed. Semiconductor component according to Claim 26, characterized in that the trapping layer ( 250 ) at least two spatially separated and isolated storage zones ( 251 . 252 ), wherein the charge carriers ( 232 ) at least partially between the two storage zones ( 251 . 252 ) into the trapping layer ( 250 ) are injectable. Semiconductor component according to Claim 25, characterized by a control unit ( 750 ) which is capable of controlling a multilevel operation of the memory cells. Electronic system comprising a semiconductor component ( 800 ), comprising memory cells ( 804 ), each comprising: a first and a second source / drain region ( 212 . 222 ) and one between the two source / drain regions ( 212 . 222 ) formed substrate portion ( 230 ); a first power supply unit ( 281 . 381 ; 741 ), one for triggering an avalanche breakthrough between the source / drain regions ( 212 . 222 ) on the one hand and the substrate section ( 230 ) on the other hand capable of generating suitable first voltage; and a bit line selection device ( 720 ) having the first voltage at each of the first and second source / drain regions ( 212 . 222 ) a subset of the memory cells ( 711 ) connected bitlines ( 712 ) can switch. A system according to claim 29, characterized in that the system is a memory card, a digital camera, an audio system, a video system, a mobile telephone, a computer system, a graphics card, a memory module or a portable data carrier with a data interface for connection to one of said systems.

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