DE102007003534A1 - Memory cell e.g. non-volatile two-bit-Trapping layer-memory cell, operating method for e.g. memory card, involves applying voltage between gate electrode and substrate section such that charge carrier is injected into memory element - Google Patents

Abstract

The method involves applying a voltage to p-n junctions (114, 124) among a source region (112), a drain region (122) and a substrate section (130) such that an avalanche breakdown takes place at the respective p-n junction. Another voltage is applied between a gate electrode (170) and the substrate section such that a charge carrier (132) produced by the avalanche breakdown and injected into the substrate section is injected into a memory element that is arranged between the substrate section and the gate electrode. Independent claims are also included for the following: (1) a method for programming a memory cell (2) a method for deleting a memory cell (3) a semiconductor component with memory cells (4) an electronic system comprising the semiconductor component.

Description

embodiments The invention relates to an operating method for a memory cell and methods for programming and erasing a memory cell. Other embodiments relate an operating method for a memory cell with localized Charge storage and semiconductor devices for execution the said methods are suitable.

nonvolatile Memory cells are usually based on an n-channel MOSFET, at between the gate electrode and the channel region of the transistor an isolated memory element is provided. To program the memory cell becomes charge carriers in the memory element injected. To erase the memory cell, the charge carriers removed from the storage element or with charge carriers compensated for opposite polarity. The threshold voltage of the transistor is dependent on the in the memory element stored charge. To read the memory cell is connected to the Gate electrode applied a voltage at which the memory cell for example, in the programmed state, conductive and in the deleted state State is non-conductive, while keeping the current between the two sides evaluated the channel region arranged source / drain regions.

The Memory element of a floating gate cell is usually one conductive layer within the gate electrode stack, the through a tunnel oxide from the channel region and through a barrier layer is isolated from the gate electrode or the control gate. Programming or deleting the floating gate cells via Mechanisms such as Fowler-Nordheim tunneling or hot carrier injection (eg CHE, channel hot electron).

at Trapping storage type storage cells is the storage element Trapping layer of a non-conductive material with traps for charge carriers, such as a silicon nitride layer. The charges are trapped within the trapping layer bound.

at 2-bit memory cells transform the charge carriers into two from each other isolated storage zones stored about a trapping layer. Over the course of the operating life of the memory cell can in a central zone between the two storage zones electrons accumulate, whose distance to the source / drain regions too great for tunneling back to the source / drain regions is. These so-called excess electrons (overspill electrons) permanently bias the gate electrode.

In the US 6,243,300 B1 describes a method for erasing a 2-bit Trappingschicht memory cell, in which each of the pn junction between the respective source / drain and the channel region is poled in the flow direction. The resulting holes tunnel due to a negative gate voltage in the central channel region in the central zone of the trapping layer and compensate for the accumulated excess electrons there.

The US 6,800,493 B2 refers to neutralization of charge stored in the storage element during the manufacturing process by a wafer level Fowler-Nordheim mechanism.

In the article "A Novel 2-bit / cell Nitride Storage Flash Memory with Greater Than 1 M P / E-Cycle Endurance", Yen-Hao Shih et al., In IEDM (San Francisco, CA, USA), pp. 881-884; IEEE, 2004 For example, a method of erasing accumulated charge in the trapping layer of a memory cell using a p ⁺ -doped gate electrode in conjunction with a negative Fowler-Nordheim reset is described.

The increase in the number of permissible programming / erasing cycles by injecting holes from the substrate is in the article "Extending endurance of NROM memories to over 10 million program / erase cycles" by Yakov Roizin et al., 21st Non-Volatile Semiconductor Memory Workshop, (Montreal, CA, USA), pp. 74-75, IEEE 2006 , described. For this purpose, the layer thickness of the tunnel oxide is reduced and the upper barrier layer is formed as an aluminum oxide layer or a p ⁺ -doped gate electrode is provided.

The US Pat. No. 6,487,121 B1 refers to a programming method for a 2-bit trapping layer memory cell in which the injection profiles of the electrons injected in the programming process and the holes injected during the erase process are matched to one another by applying an additional vertical field.

According to one in the US 6,930,928 B2 Prior to the actual program / erase cycle, preprogramming of a nonvolatile memory cell by means of Fowler-Nordheim tunnels is performed. Preprogramming prevents more charge in the trapping layer from being compensated or removed during the erase cycle than was injected into the trapping layer in the previous programming cycle.

The US 6,490,205 B1 relates to a method of erasing a 2-bit trapping-layer memory cell in which, during the erase operation, the pn junctions between the source / drain regions of the memory cell and they surrounding substrate well is reverse biased at a voltage which is less than the breakdown voltage of the pn junction. The substrate bias is intended to amplify the lateral electric field within the channel region, thereby increasing the number of hot holes generated within the memory cell and accelerating the erase process altogether.

The US 6,744,675 B1 describes a method of programming a SONOS memory cell. After the actual programming process, a weak erase pulse is provided, in the course of which flat-seated charges in the lower, oriented to the substrate portion of the trapping layer are removed.

The US Pat. No. 6,891,760 B2 refers to a method for deleting a 2-bit trapping layer memory cell. With a suitable substrate bias, excess electrons are to pass into the substrate.

In the US Pat. No. 6,438,031 B1 For example, a programming method for 2-bit trapping-layer memory cells is described in which the application of substrate bias during the programming operation reduces the electric field strength near the source / drain regions. Due to the reduced impact ionization in these regions, the number of such electrons that can be injected in the region of the middle zone of the trapping layer is reduced.

The US Pat. No. 6,456,531 B1 relates to a programming method for a 2-bit trapping layer memory cell in which a blocking voltage near the breakdown voltage is applied between the source / drain regions and the substrate during the programming operation to control the injection profiles of the electrons injected during the programming process, and in the case of Extinguish injected holes to match each other.

In the article "Simultaneous Hot-Hole Injection at Drain and Source for Efficient Erase and Excellent Endurance in SONGS Flash EEPROM Cells", Myung Kwan Cho and Dae M. Kim, IEEE Electron Device Letters, Vol. 24, No. 4, pp. 260-262 , 2003 An erasure method for SONGS memory cells will be described. Hot holes are simultaneously injected into the trapping layer on both source / drain sides by a hot hole injection (HHI) mechanism, to which the substrate is biased.

A Embodiment of the invention relates to an operating method for a nonvolatile memory cell with two formed in a semiconductor substrate source / drain regions and one formed between the two source / drain regions Substrate section. The substrate portion is adjacent to a substrate surface of the semiconductor substrate. Above the substrate portion is a memory element of the nonvolatile memory cell is arranged, which is isolated from the substrate portion by a first barrier layer is. A second barrier layer isolates the memory element from a gate electrode through which the memory cell is addressed.

The both source / drain regions have a doping of a first Conductivity and the substrate portion doping of a first conductivity type opposite second conductivity type.

At a pn junction formed between one of the source / drain regions and the substrate section, a first voltage is applied such that avalanche breakdown occurs at the pn junction. For this purpose, in the reverse direction of the pn junction, at least the breakdown voltage of the pn junction is applied or a corresponding current impressed. The respective minority carriers are accelerated by the electric field in the space charge zone in such a way that electron / hole pairs are generated there. In the case of an n ⁺ -doped source / drain region and a p-doped substrate section, high-energy holes subsequently pass into the substrate section. The energy of the injected holes is sufficient to generate further electron / hole pairs there.

in the Essentially at the same time or immediately after the creation of the first voltage becomes between the gate electrode and the substrate portion second voltage applied, which is sufficiently large to generated in the sequence of avalanche breakdown in the substrate section To deflect charge carriers in the direction of the gate electrode. The energy of the charge carrier is enough to get through the bottom barrier layer into the memory element to pass. For example becomes the gate electrode opposite to the substrate portion negatively biased, so that holes in the memory element be injected. In doing so, the holes are broken by the operation reverse pn-transitions (RDHI, reverse diode hole injection).

Of the Avalanche breakthrough is a big number in a short time of electrons and holes for programming or for Delete available, so that a comparatively rapid injection of electrons into the storage element and a correspondingly faster programming or deleting results.

If the first voltage in each case between two source / drain regions of the memory cell on the one hand and the substrate portion on the other or a current via both pn-transitions eigeprägt so that both pn junctions are operated above the breakdown voltage in the reverse direction, so distributed as a result of the avalanche breakthrough in the sub stratabschnitt injected or there in the sequence generated charge carriers over the entire channel length , For example, for 2-bit trapping layer memory cells wired according to the virtual ground concept, a uniform-effect erase or refresh procedure results.

The Breakdown voltage of a pn junction is dependent from the width of the space charge zones and thus from the dopings and doping profiles of the source / drain regions as well of the substrate portion. The dopings and doping gradients for example, are chosen so that in the breakthrough case a field strength between 0.3 and 1.2 MV / cm results.

According to a possible embodiment, the source / drain regions have an n-type doping of about 10 ¹⁹ cm ^-3 and the substrate portion has a p-type doping of about 10 ¹⁷ cm ^-3 .

A Another embodiment of the invention relates to a Programming method for a nonvolatile memory cell. At least one of the pn junctions between one of the source / drain regions and one of the source / drain regions Subsequent substrate portion becomes a first voltage designed such that at the pn junction avalanche breakdown he follows. For this purpose, in the reverse direction of the pn junction a Voltage greater than or equal to the breakdown voltage of the pn transition created. Essentially at the same time or immediately thereafter, between the gate electrode of the memory cell and the substrate portion has a second voltage applied thereto, that generated as a result of avalanche breakdown carriers be injected into a storage element between the substrate portion and the gate electrode and is disposed isolated from both. It will the memory element is electrically charged or discharged and the memory cell programmed.

Becomes the second voltage with negative polarity between the Gate electrode and the substrate portion is applied, so that the gate electrode is negatively biased to the substrate portion, thus holes are injected into the storage element.

Becomes the second voltage with positive polarity between the Gate electrode and the substrate portion is applied, so that the gate electrode is positively biased to the substrate portion, so electrons are injected into the storage element.

A Another embodiment of the invention relates to an extinguishing method for a non-volatile Memory cell. Between one or both source / drain regions the non-volatile memory cell on the one hand and a at the or the source / drain regions subsequent substrate portion of a Semiconductor substrate, a first voltage is applied so that at the between the source / drain regions and the substrate portion trained pn-junctions one avalanche breakdown each he follows. For this purpose, the substrate portion opposite to Source / drain regions with a voltage that is at least the breakdown voltage of pn junction corresponds, negatively biased.

Between the gate electrode of the memory cell and the substrate portion becomes a second voltage applied so that due to the avalanche breakdown accelerates generated charge carriers in the direction of the gate electrode and thereby into between the substrate portion and the gate electrode arranged storage element are injected, both from the substrate section as well as being electrically isolated from the gate electrode. There will be a In the memory element stored La tion compensated or the memory element loaded and the memory cell cleared.

A Another embodiment of the invention relates to an operating procedure for a non-volatile Memory cell with localized charge storage. The memory cell includes two separated by a substrate portion and source / drain regions formed in a semiconductor substrate. The source / drain regions have a doping of a first Conductivity type and the two source / drain regions spaced substrate portion doped by one of the first Conductivity type of opposite second conductivity type on. The first barrier layer insulates the substrate portion from a memory element of the memory cell. A second barrier layer isolates the memory element from a gate electrode for addressing the memory cell. The memory element has two mutually insulated and separately controllable memory zones, each are oriented to one of the two source / drain regions. In a central zone between the two storage zones may be due previous programming cycles to an accumulation of excess electrons do not come through the usual extinguishing methods more to remove or compensate. The threshold voltage the deleted memory cell will be permanently in the direction that of the programmed shifted.

According to the present embodiment, the pn junctions between the first and the second source / drain region on the one hand and ei On the other hand, a first voltage is applied in each case in the reverse direction to a substrate section adjoining the source / drain regions such that avalanche breakdown occurs at the pn junctions. In this case, electron / hole pairs are generated in the space charge zone of the respective pn junction by accelerated charge carriers.

are For example, the source / drain regions are n-doped and is the substrate portion p-doped, so are the holes generated in the space charge zone injected into the substrate section. Own the holes Enough energy to get there by impact ionization more To create electron / hole pairs. It comes to an enrichment of ionized electron / hole pairs in the substrate section. Between the gate electrode of the memory cell and the substrate portion becomes simultaneously or immediately thereafter a second voltage of negative polarity created so that the direct or indirect from the avalanche breach resulting holes in the substrate portion in the direction the gate electrode are deflected and thereby in between the Substrate portion and the gate electrode arranged storage element the memory cell to be injected. The holes will be there over the entire channel length between the two source / drain regions injected into the storage element.

A any remanent negative charge in the central zone between The storage zones will be affected by the positive charge of the holes at least compensated. The threshold voltage reached, depending from the duration of the voltage pulses, again at least the original one Value or a value below. The maximum operating time the memory cell or a semiconductor device, the on this Memory cell type is increased. The maximum possible Number of program / erase cycles (cyclo-strength) significantly increased. From the reduction of stress the memory cell due to the saved erase pulses is also the data retention in such a semiconductor device improved.

For example, the first voltage is chosen so that the field strength at the pn junction is between 0.3 and 1.2 MeV / cm ^-3 , but in any case sufficient to trigger avalanche breakdown.

The First and second voltages can be essentially synchronous or simultaneously for a period of about 10 msec to 50 msec be created. Optionally, the application of the first and second voltage extended or repeated until a threshold voltage determined for the memory cell is equal to or less than a predefined value. The predefined Value is for example the original output value the threshold voltage at the beginning of the life of the memory device is determined.

To In one embodiment, the refresh of the memory element still at the wafer level and before the first use of the memory executed in a product specific application to a Process-related accumulation of charge carriers in the Memory layer to compensate.

To Another embodiment is at every deletion the number of times for a complete erase cycle required clear pulses and determined with a predetermined Limit value for the number of erase pulses compared. exceeds the number of erase pulses just required exceeds the limit, Thus, the memory cell or the memory element by applying the first and second voltage "refreshed" or reset.

To In another embodiment, refreshing the Memory element cyclically after a predetermined number executed by programming cycles. This will be done before or after executing a programming operation, a current counter reading determined for programming operations. exceeds the current counter reading a predetermined limit counter reading for the number of programming cycles, so does the memory element refreshed by applying the first and second voltage and the Counter reading reset for programming cycles.

One Semiconductor component according to a further embodiment The invention includes memory cells each having a first and a second source / drain region, one between the two source / drain regions formed substrate portion, a storage element isolated from the substrate portion and a gate electrode isolated from the memory element. The semiconductor device comprises Furthermore, a first power supply unit, one for triggering the avalanche breakdown between the source / drain regions on the one hand and the substrate portion, on the other hand, suitable first voltage to generate or impose a corresponding current able, as well as a second power supply unit, which between the Gate electrode and the substrate portion for injecting the in the avalanche generated carrier in the memory element is capable of generating suitable second voltage. Such a semiconductor device is advantageous for the above operating methods are suitable.

The source / drain regions and the substrate section can be made in the same semiconductor substrate be formed. The substrate portion may be isolated from the memory element by a first barrier layer and the memory element may be insulated from the gate electrode by a second barrier layer.

The Memory element may be a conductive floating gate or be a non-conductive trapping layer. The non-conductive For example, the trapping layer can be at least two spatial have separate and mutually isolated storage zones whose Charge states independently controllable are. Become during regular programming / deleting in the side effect also between the two storage zones charge carriers injected into the memory element, so is this semiconductor device advantageously for the above operating method for a non-volatile memory cell with localized Charge storage suitable, which is the compensation of these charge carriers allows.

in the Below are embodiments of the invention, which the common concept of avalanche breakdown available Asked charge carriers are connected, and their advantages the figures explained in more detail. Show it:

1A - 1B FIG. 2: schematic cross-sectional views of a non-volatile 2-bit trapping layer memory cell for explaining an operating method according to an embodiment; FIG.

2 FIG. 2 is a schematic cross-sectional view of a 2-bit trapping-layer memory cell for explaining a method of operating a non-volatile memory cell according to another embodiment; FIG.

3A - 3B : schematic cross-sectional representations of a floating gate memory cell for explaining a programming or erasing method according to another embodiment;

4 FIG. 4 is a schematic flowchart for explaining a method of operating a nonvolatile memory cell with localized charge storage and adaptive refresh cycles according to another embodiment; FIG.

5 FIG. 12 is a schematic flow diagram of a method of operation for a non-volatile memory cell with localized charge storage and cyclic refresh cycles, according to another embodiment; FIG.

6 FIG. 4 is a diagram showing the dependence of the number of required erase pulses on the number of program and refresh cycles for a memory cell according to another embodiment; FIG.

7 FIG. 2 is a simplified schematic block diagram of a semiconductor device according to another embodiment; FIG.

8th FIG. 2 is a schematic block diagram of a data storage system according to another embodiment; FIG.

9 FIG. 3 is a simplified flowchart for a method of operating a nonvolatile memory cell according to an embodiment of the invention; FIG.

10 FIG. 5 is a simplified flowchart for a programming method for a nonvolatile memory cell according to an embodiment of the invention; FIG.

11 FIG. 2 is a simplified flowchart for a nonvolatile memory cell erasing method according to an embodiment of the invention; FIG. and

12 FIG. 2: a simplified flowchart for a method of operation for a non-volatile memory cell with localized charge.

The 1A and 1B refer to an operating method for a 2-bit trapping layer memory cell 199 , The memory cell 199 includes two each, for example, in a semiconductor substrate 100 trained source / drain regions 112 . 122 , The two source / drain regions 112 . 122 are through a substrate section 130 spaced apart. The substrate section 130 is, for example, a p-doped well in the semiconductor substrate 100 , In order to bias independently selected regions of the semiconductor substrate from one another and from other p-doped regions, the p-doped well may be formed into an n-doped well 102 be embedded. For example, an entire cell array, individual segments of a cell array or even a circuit periphery may share a common p-doped well 130 include. The two source / drain regions are n ⁺ doped in this example. The substrate section 130 adjoins the substrate surface 110 of the semiconductor substrate 100 at. Above the substrate section 130 within the conductive state of the memory cell between the two source / drain regions 112 . 122 a conductive channel is formed is a storage element, such as a trapping layer 150 arranged through a first barrier layer 140 from the substrate section 130 is isolated.

Opposite a gate electrode 170 is the trapping layer 150 through a second dielectric barrier layer 160 electrically isolated. The first and second dielectric barriers layer 140 . 160 are for example silicon oxide layers. The second barrier layer 160 can also be formed as a layer system with layers of different dielectric materials. The gate electrode 170 comprises approximately at least in one of the second barrier layer 160 subsequent section a polysilicon layer or a metal layer. The trapping layer 150 according to this embodiment is a non-conductive layer with electrical charge traps, for example a silicon nitride layer or other non-conductive layer with deposits of conductive material. The layer thickness of the first barrier layer 140 is about 2 to 10 nm, that of the second barrier layer 160 5 to 20 nm and that of the trapping layer 150 about 2 to 10 nm.

The trapping layer 150 has two each to one of the source / drain regions 112 . 122 oriented storage zones 151 . 152 on, which are isolated from each other and independently controllable. When programming one of the bits of the memory cell 199 for example, within the storage zone 151 enriched negative electric charge, for example, through from the right source / drain region 122 exiting and towards the left source / drain region 112 accelerated, "hot" electrons, with sufficient energy in the left storage zone 151 through the lower barrier layer 140 tunnels and at trapping points within the storage zone 151 be fixed. The erasure is done, for example, by Fowler-Nordheim tunneling of the electrons to the left source / drain region 112 or by, for example by band-to-band tunneling, to compensate for "hot" holes in the storage zone 151 be injected.

Due to parasitic effects are also present in a central zone 153 between the two storage zones 151 . 152 so-called excess electrons (overspill electrons) 133 injected, whose charge is not fully compensated by conventional erase algorithms, so that there is a continuous shift of the threshold voltage of the memory cell to higher values.

By means of a first voltage supply unit 181 is in the course of a refresh cycle between the source / drain regions 112 . 122 on the one hand and the substrate section 130 on the other hand, a positive voltage is applied and each between the substrate sections 130 and the source / drain regions 112 . 122 trained pn transitions 114 . 124 operated in the reverse direction (reverse bias). The applied voltage corresponds at least to the breakdown voltage of both pn junctions 114 . 124 , Inside of the pn-transitions 114 . 124 extending space charge zones 116 . 126 With a sufficient width of the space charge zones and sufficiently large electric field strength, the minority charge carrier which determines the reverse current will absorb sufficient energy to generate an electron / hole pair in the event of a collision with the thermally disordered grid. The result is an avalanche-like increase in the number of charge carriers. It goes in the space charge zones 116 . 126 generated holes 132 in the negatively biased substrate section 130 over there and generate there by impact ionization more electron / hole pairs.

According to 1B is a second power supply unit 182 provided, in this embodiment, the gate electrode 170 against the substrate portion 130 negatively biased. Due to the resulting electric field, those due to avalanche breakdown along the pn junctions become 114 . 124 in the substrate section 130 passed or generated there holes 132 in the direction of the memory element 150 deflected. With sufficient voltage between the gate electrode 170 and the substrate portion 130 tunnels a part of the holes 132 between the two storage zones 151 . 152 through the lower barrier layer 140 and compensates for the charge between the storage zones 151 . 152 fixed excess electrons 133 ,

Applying the first voltage across the first voltage delay unit 181 and a second voltage across the second voltage delay unit 182 is largely synchronous.

Instead of the two voltage delay units 181 . 182 three voltage supply units with common reference potential can be provided. The first power supply unit 181 may be formed such that a corresponding current is impressed on the pn junctions.

The 2 shows a memory cell 299 , their first and second source / drain region 212 . 222 to a first power supply unit 281 , whose gate electrode 270 to a second power supply unit 282 and their two source / drain regions 212 . 222 spaced apart substrate portion 230 to a third power supply unit 283 are connected. The power supply units 281 . 282 . 283 generate voltages referenced to a common reference potential.

In this case, the first voltage supply unit is capable of delivering a first voltage pulse which is positive relative to the reference potential and having a length of, for example, between 10 ms and 50 ms, approximately 20 ms, and a voltage of, for example, 3 to 5 volts, approximately 4 volts , The second power supply unit is capable of a large extent at least for a period of 10 to 50 ms to deliver the positive first voltage pulse synchronized negative voltage pulse of -8 to -12 volts, about 10 volts. The third voltage supply unit 283 is able to generate a third voltage pulse of approximately -2 to -2 volts, approximately -4 volts and a duration of approximately 10 ms to 50 ms, which is largely synchronized with the other voltage pulses. The voltages are chosen so that both a sufficient drain avalanche drain or source-to-substrate voltage, as well as a suitable potential difference, z. B. a sufficiently positive for the injection of holes, between substrate and gate.

The three voltage pulses become approximately synchronous with each other at the gate electrode 270 , the source / drain regions 212 . 222 and to the substrate portion 230 created. The between the n ⁺ -doped source / drain regions 212 . 222 and the p-doped substrate portion 230 trained pn transitions 214 . 224 are applied in the reverse direction with a voltage corresponding to at least their breakdown voltage. Doing so in the along the pn junctions 214 . 224 trained space charge zones 216 . 226 Electron / hole pairs formed and holes 232 in the negatively biased substrate section 230 injected. Part of the holes 232 is in the direction of the opposite to the substrate portion 230 negatively biased gate electrode 270 deflected and occurs at full length of the distance between the two source / drain regions 212 . 214 through the first barrier layer 240 , This will both charges in the storage zones 251 and 252 as well as fixed charges 233 between the two storage zones 251 . 252 the trapping layer 250 compensated. The second barrier layer 260 prevents further tunneling of the charge carriers to the gate electrode 270 ,

The 3A to 3B refer to a programming or erasing method for a floating gate memory cell 399 , The method is illustrated for explanation in two figures. In fact, both steps are largely synchronized. The memory cell 399 includes two source / drain regions 312 . 322 which are in a semiconductor substrate 300 are formed as n ⁺ -doped regions or impurity regions. The two source / drain regions 312 . 322 be through one. substrate section 330 spaced apart. Between the source / drain regions 312 . 322 each yield pn transitions 314 . 324 , The two source / drain areas 312 . 322 spaced substrate portion 330 forms a substrate surface in sections 310 of the semiconductor substrate 300 out. above the substrate portion 330 is between the two source / drain regions 312 . 322 For example, a floating gate 350 provided by a on the substrate surface 310 overhead tunnel oxide 340 from the semiconductor substrate 300 is spaced. The tunnel oxide 340 is typically a silicon oxide layer with a thickness of 2 to 8 nm. The floating gate 350 is, for example, a conductive layer of doped polysilicon with a thickness of up to several 10 nm and is formed by a second barrier layer 360 from the gate electrode 370 isolated.

According to 3A is by means of a first power supply unit 381 the substrate section 330 negative against the right source / drain region 322 biased. The amount of voltage applied is at least the breakdown voltage of the pn junction 324 , In the process along the pn junction 324 extending space charge zone 326 become electrons / hole pairs 332 . 331 generated, with the holes 332 in the negatively biased substrate section 330 transgressed.

According to 3B is powered by a second power supply 382 between the gate electrode 370 and the substrate portion 330 a second voltage is applied to the gate electrode 370 opposite the substrate portion 330 negatively biased. The amount of the second voltage is sufficiently high to be in the substrate portion 330 passed or produced there in Sekundäref effect holes 332 through the first barrier layer 340 to let happen. The holes 332 enter the floating gate 350 over and change the threshold voltage of the memory cell 399 ,

Becomes the gate electrode is positive with respect to the substrate portion biased, may similarly be in the substrate Electronically generated electrons are transferred to the floating gate by shock ionization.

The 4 relates to an embodiment of an operating method for operating a non-volatile memory cell with localized charge storage, wherein a drift of the threshold value of the memory cell is determined directly and indirectly, and depending on the magnitude of the deviation from a standard value, a refresh of the memory cell in the manner described above ,

From a sequence control of the semiconductor device having such a memory cell, there is a delete call 402 , The initialization follows 404 a counter that registers the number of erase pulses executed within the respective erase call. The memory cell or one bit of the memory cell is supplied with an erase pulse 406 and the erase pulse counter increments 408 , Subsequently, it is checked 412 whether the memory cell or the bit of the memory cell to be erased has actually been erased. Is the result of this review 412 negative, more erase pulses are applied 406 and for every applied Lö pulse of the erase pulse counter is incremented 408 , Will in the course of review 412 it is checked that the memory cell is actually erased 422 whether the number of erase pulses has exceeded a predetermined pulse limit. In the event that the pulse limit has actually been exceeded, the charge of the excess electrons in the storage element will be replaced by a refresh cycle 424 comprising leveling the application of the first and second voltage as described above and thereby "refreshing" or reverting the threshold voltage of the memory element of the memory cell.

Through an optional regular program / erase cycle 426 The charge injected during refreshment into the storage zones is removed. The deletion procedure will then be terminated 430 ,

The 5 refers to a flowchart for a method of operation for a non-volatile memory cell with localized charge storage, in which the memory element is refreshed cyclically.

From a program sequence control in a memory cell having semiconductor device is a programming call 502 , Before the actual programming start is checked 512 whether the number of write cycles already executed is greater than a limit cycle number. If this is not the case, the actual programming process follows immediately 532 , Is the result of the review 512 positive, the charge in the storage element is leveled by applying the first and second voltages as described above 522 and the memory cell is "refreshed." The counter is then reset for the write cycles that have been carried out since the last refresh 524 , This is followed by the regular programming cycle 532 , After the programming process, the counter for the already executed write cycles is incremented 534 , and then stop programming 536 ,

The 6 shows a diagram 600 to illustrate the relationship between the number of erase pulses required per erase with the number of write cycles as a function of refresh pulses performed between the write cycles 601 . 602 . 603 . 604 , From the diagram 600 shows that averaged over several memory cells after every 10,000 write cycles on average about 7 erase pulses are required to completely erase the memory cells. After several 10,000 write cycles, the number of pulses required increases to 17. After a second refresh cycle 602 of the type described above, the number of erase pulses required initially drops below 13 and after another refresh cycle 603 after 100,000 write cycles again to less than 11. Through a fourth refresh cycle 604 After several 100,000 write cycles, the number of erase pulses required for a complete erase operation can be permanently reduced to less than 10 again.

The so-called cyclo-resistance of such memory cells becomes significant elevated. Due to the lower stress in the regular Programming or deletion procedures will also preserve the data (Data retention) in the memory cell significantly improved.

The 7 is a simplified block diagram of a semiconductor device 700 according to another embodiment.

The semiconductor device 700 includes to a memory cell array 710 arranged non-volatile memory cells 711 which are arranged, for example, in a "virtual ground array" 711 become over with the gate electrodes of the memory cells 711 connected word lines 713 addressed. The data intended for storage or that from the memory cells 711 data read out are over bit lines 712 each transmitted to the source / drain regions of the memory cells 711 are connected. The selection of bit lines 712 via a bit line selector 720 ,

The addressing of the word lines 713 via a word line selection device 730 ,

The potential of the gate electrodes of the memory cells 711 is from one with the word line selector 730 connected word line power supply unit 731 generated, which provides for the reference to a reference potential voltage of about -10 volts for refreshing. The potential on the bit lines is from one with the bit line selector 720 connected bit line power supply unit 721 which is capable of generating a voltage of about +4 volts with respect to the reference potential for refreshing the memory cells. A substrate power supply unit 741 provides the substrate portions, respectively, disposed between the source / drain regions, typically portions of a p-doped well embedded in an n-doped well (triple well) having a substrate potential for refresh with respect to the reference potential -4 volts. The substrate power supply unit 741 may also be formed as a current source, which impresses a constant current between the substrate and about the reference potential. The impressed current flows as a reverse current through the pn junctions of the associated memory cells and is chosen so that the selected pn junctions are operated in the breakthrough. A control unit 750 controls the chip voltage supply units 721 . 731 . 741 depending on the procedure to be performed, such as writing, reading, deleting or refreshing.

The 8th shows an electronic system 800 , The system 800 has a semiconductor device 802 with memory cells 804 on. The memory cells each have a first and a second source / drain region and a substrate section formed between the two source / drain regions. A first voltage supply unit is capable of generating a first voltage suitable for triggering avalanche breakdown between the source / drain regions and the substrate portion, on the other hand.

The system 800 is for example a memory card, a digital camera, a mobile phone, an audio system, a video system, a computer system or a part thereof, such as a memory module, a graphics card or a mobile data carrier with an interface for connection to one of said systems.

The 9 FIG. 10 is a flowchart illustrating a method of operating a memory cell, such as a floating gate or trapping layer memory cell. The method includes the operation 900 at least one reverse pn junction above the breakdown voltage and biasing 902 the gate electrode opposite to the substrate. An avalanche breakdown occurs at the pn junction, resulting in holes in a p-doped substrate and electrons in an n-doped substrate. The respective charge carriers that have entered the substrate can generate additional electron / hole pairs by means of collision. Depending on the polarity of the gate electrode bias voltage with respect to the substrate, electrons or holes are injected into a memory element disposed between the substrate and the gate electrode. Operating the reverse pn junction 900 or the biasing of the gate electrode 902 is essentially the same time.

The 10 refers to a programming method for a, e.g. B. nonvolatile, memory cell. At least one of the pn junctions of the memory cell is reverse biased above the breakdown voltage 904 , The gate electrode is biased against the substrate in this way 906 in that the charge carriers required for programming are injected into a storage element arranged between the gate electrode and the substrate. Operating 904 the reverse pn junction and biasing 906 the gate electrode occurs substantially simultaneously.

The 11 refers to an erasure method for a, e.g. B. nonvolatile, memory cell. One of the pn junctions or both pn junctions are reverse biased above the breakdown voltage 908 , The gate electrode is biased against the substrate in this way 910 in that the charge carriers required for erasing the nonvolatile memory cell are injected into a memory element arranged between the gate electrode and the substrate.

The 12 is a schematic flow diagram illustrating an operating method for a, z. Non-volatile memory cell with localized charge storage. Both pn junctions of the memory cell are operated in the reverse direction above the breakdown voltage 912 , The gate electrode is positively biased against the substrate 914 whereby holes resulting from the avalanche breakdown are injected into a storage element arranged between the gate electrode and the substrate, where they compensate the charge of excess electrons. Operating the reverse pn junctions and positively biasing the gate electrode 912 . 914 is largely simultaneous. The operating method corresponds to a refresh cycle that is performed in addition to the actual erase cycle.

QUOTES INCLUDE IN THE DESCRIPTION

This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.

Cited patent literature

• US 6243300 B1 [0006]
• US 6800493 B2 [0007]
• - US 6487121 B1 [0010]
• US 6930928 B2 [0011]
• - US 6490205 B1 [0012]
• - US 6744675 B1 [0013]
• US 6891760 B2 [0014]
• - US Pat. No. 6438031 B1 [0015]
• - US 6456531 B1 [0016]

Cited non-patent literature

• "A Novel 2-bit / cell Nitride Storage Flash Memory with Greater Than 1 M P / E-Cycle Endurance", Yen-Hao Shih et al., In IEDM (San Francisco, CA, USA), pp. 881-884 IEEE, 2004 [0008]
• - "Extending endurance of NROM memories to over 10 million program / erase cycles" by Yakov Roizin et al., 21st Non-Volatile Semiconductor Memory Workshop, (Montreal, CA, USA), pp. 74-75, IEEE 2006 [ 0009]
• "Simultaneous Hot-Hole Injection at Drain and Source for Efficient Erase and Excellent Endurance in SONGS Flash EEPROM Cells", Myung Kwan Cho and Dae M. Kim, IEEE Electron Device Letters, Vol. 24, No. 4, pp. 260- 262, 2003 [0017]

Claims (31)

A method of operating a memory cell, comprising: applying a first voltage to a pn junction ( 214 . 224 ) between a source / drain region ( 212 . 222 ) and a substrate section ( 230 ) such that at the respective pn junction ( 214 . 224 ) an avalanche breach occurs; and applying a second voltage between a gate electrode ( 270 ) and the substrate portion ( 230 ) such that generated by the avalanche breakdown and in the substrate section ( 230 ) injected charge carriers ( 232 ) in between the substrate portion ( 230 ) and the gate electrode ( 270 ) are injected memory element. Method according to Claim 1, characterized by applying the first voltage to a pn junction ( 224 . 214 ) between another source / drain region ( 212 . 222 ) of the memory cell ( 299 ) and the substrate portion ( 230 ). A method according to claim 1, characterized in that the first voltage of at least the breakdown voltage of the pn junction ( 214 . 224 ) corresponds. A method according to claim 1, characterized in that the first voltage is selected so that at the respective pn junction ( 214 . 224 ) gives a field strength of at least 0.3 MeV / cm ^-3 . A method according to claim 1, characterized in that the first voltage is selected so that at the respective pn junction ( 214 . 224 ) gives a field strength of at most 1.2 MeV / cm ^-3 . Method according to claim 1, characterized in that the respective source / drain region ( 212 . 222 ) a doping of 5 × 10 ¹⁸ cm ^-3 to 2 × 10 ¹⁹ and the substrate portion ( 203 ) have a doping of 5 × 10 ¹⁶ to 2 × 10 ¹⁷ cm ^-3 . Method according to claim 1, characterized in that that the first and the second voltage are applied simultaneously. Programming method for a memory cell ( 399 ) comprising: applying a first voltage to a pn junction ( 324 ) between a source / drain region ( 322 ) and one to the source / drain region ( 322 ) Subsequent substrate section ( 330 ) such that at the pn junction ( 324 ) an avalanche breach occurs; and applying a second voltage between a gate electrode ( 370 ) and the substrate portion ( 330 ) in such a way that charge carriers generated by the avalanche breakdown ( 332 ) in between the substrate portion ( 330 ) and the gate electrode ( 370 ) are injected, wherein the memory cell ( 399 ) is programmed. Extinguishing method for a memory cell ( 399 ) comprising: applying a first voltage to a pn junction ( 324 ) between a source / drain region ( 322 ) and one to the source / drain region ( 322 ) Subsequent substrate section ( 330 ) such that at the pn junction ( 324 ) an avalanche breach occurs; and applying a second voltage between a gate electrode ( 370 ) and the substrate portion ( 330 ) in such a way that charge carriers generated by the avalanche breakdown ( 332 ) in between the substrate portion ( 330 ) and the gate electrode ( 370 ) are injected, wherein the memory cell ( 399 ) is deleted. Method according to one of claims 8 or 9, characterized in that by applying the second voltage with negative polarity holes in the memory element be injected. Method according to one of claims 8 or 9, characterized in that by applying the second voltage with positive polarity electrons in the memory element be injected. Method according to one of claims 8 to 11, characterized in that the first and the second voltage simultaneously be created. A method of operating a memory cell with localized charge storage, comprising: applying a first voltage to pn junctions ( 214 . 224 ) between a first ( 212 ) and a second ( 222 ) Source / drain region on the one hand and one of the source / drain regions ( 212 . 222 ) Subsequent substrate section ( 230 ) on the other hand in the reverse direction such that at the pn junctions ( 214 . 224 ) an avalanche breach occurs; and applying a second voltage between a gate electrode ( 270 ) and the substrate portion ( 230 ) such that holes generated by the avalanche breakdown ( 232 ) in between the substrate portion ( 230 ) and the gate electrode ( 270 ) are memory element of the memory cell injected. A method according to claim 13, characterized in that through the injected holes between two storage zones ( 251 . 252 ) stored negative charges ( 233 ) are compensated. A method according to claim 13, characterized in that the first voltage of at least the higher breakdown voltage of the two pn junctions ( 214 . 224 ) corresponds. A method according to claim 13, characterized in that the first voltage is chosen so that at the pn junctions ( 214 . 224 ) gives a field strength between 0.3 and 1.2 MeV / cm ^-3 . Method according to claim 13, characterized in that that the first and second voltages are essentially synchronous and for a period of 10 to 50 ms. A method according to claim 13, characterized in that the application of the first and second voltage is repeated until a threshold voltage of the memory cell ( 299 ) is equal to or less than a predetermined value. Method according to Claim 13, characterized by determining a current threshold value of the memory cell ( 299 after executing an erase operation; and performing application of the first and second voltages when a predetermined threshold limit is exceeded by the current threshold. A method according to claim 13, characterized by Determine a current counter reading for programming operations before or after executing a programming operation; and To run Applying the first and second voltage and reset the count when exceeding a predetermined Limit counter reading by the current counter reading. Semiconductor device ( 700 ) having memory cells ( 711 ), each comprising: a first and a second source / drain region ( 212 . 222 ); and one between the two source / drain regions ( 212 . 222 ) formed substrate portion ( 230 ); and a first power supply unit ( 741 ), one for triggering an avalanche breakthrough between the source / drain regions ( 212 . 222 ) on the one hand and the substrate section ( 230 On the other hand, it is possible to produce suitable first stress. Semiconductor component according to claim 21, characterized in that the memory cells each have a substrate section ( 230 ) isolated memory element and a memory element isolated from the gate electrode ( 270 ); and the semiconductor device has a second voltage supply unit ( 731 . 741 ), which between the gate electrode ( 270 ) and the substrate portion ( 230 ) one for injecting the charge carriers generated by the avalanche breakdown ( 232 ) is capable of generating in the memory element suitable second voltage. Semiconductor component according to Claim 21, characterized in that the first voltage supply unit ( 741 ) can be operated as a current source and is able to impress a constant reverse current in pn junctions of selected memory elements. Semiconductor component according to Claim 22, characterized in that the memory cells each have a substrate section ( 230 ) isolating from the memory element first barrier layer ( 240 ) exhibit. Semiconductor component according to Claim 22, characterized in that the memory cells each have a memory element from the gate electrode ( 270 ) insulating second barrier layer ( 260 ) exhibit. Semiconductor component according to Claim 22, characterized in that the memory elements are each in the form of a conductive floating gate ( 350 ) are formed. Semiconductor component according to claim 22, characterized in that the memory elements each as a non-conductive trapping layer ( 250 ) are formed. Semiconductor component according to Claim 27, characterized in that the trapping layer ( 250 ) at least two spatially separated and isolated storage zones ( 251 . 252 ), wherein the charge carriers ( 232 ) at least partially between the two storage zones ( 251 . 252 ) into the trapping layer ( 250 ) are injectable. Semiconductor component according to Claim 26, characterized by a control unit ( 750 ) which is capable of controlling a multilevel operation of the memory cells. Electronic system comprising a semiconductor component ( 800 ), comprising memory cells ( 804 ), each comprising: a first and a second source / drain region ( 212 . 222 ) and one between the two source / drain regions ( 212 . 222 ) formed substrate portion ( 230 ); and a first power supply unit ( 221 ), one for triggering an avalanche breakthrough between the source / drain regions ( 212 . 222 ) on the one hand and the substrate section ( 230 On the other hand, it is possible to produce suitable first stress. System according to claim 30, characterized in that that the system has a memory card, a digital camera, an audio system, a video system, a mobile phone, a computer system, a graphics card, a memory module or a portable disk with a Data interface for connection to one of the systems mentioned is.