DE102006051151A1 - Method of forming multi-layer bumps on a substrate - Google Patents
Method of forming multi-layer bumps on a substrate Download PDFInfo
- Publication number
- DE102006051151A1 DE102006051151A1 DE102006051151A DE102006051151A DE102006051151A1 DE 102006051151 A1 DE102006051151 A1 DE 102006051151A1 DE 102006051151 A DE102006051151 A DE 102006051151A DE 102006051151 A DE102006051151 A DE 102006051151A DE 102006051151 A1 DE102006051151 A1 DE 102006051151A1
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- Germany
- Prior art keywords
- metal powder
- hump
- substrate
- forming
- melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H05K2203/14—Related to the order of processing steps
- H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3494—Heating methods for reflowing of solder
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Ein Verfahren zum Ausbilden mehrschichtiger Höcker auf einem Substrat umfasst Aufbringen eines ersten Metallpulvers auf dem Substrat und selektives Schmelzen oder Wiederverflüssigen eines Bereichs des ersten Metallpulvers, um erste Höcker auszubilden. Ein zweites Metallpulver wird auf den ersten Höckern aufgebracht und geschmolzen, um zweite Höcker auf den ersten Höckern zu bilden. Eine Maskierungsplatte wird über dem Substrat angebracht, um diejenigen Bereiche der Metallpulver auszuwählen, die geschmolzen werden, und die Metallpulver werden mittels eines Bestrahlungsstrahls geschmolzen. Der mehrschichtige Höcker wird ohne die Notwendigkeit irgendwelcher Nasschemikalien ausgebildet.A method of forming multilayer bumps on a substrate comprises depositing a first metal powder on the substrate and selectively melting or re-liquefying a portion of the first metal powder to form first bumps. A second metal powder is applied to the first bumps and melted to form second bumps on the first bumps. A masking plate is applied over the substrate to select those portions of the metal powders which are melted, and the metal powders are melted by means of an irradiation jet. The multi-layered bump is formed without the need for any wet chemicals.
Description
Hintergrund der Erfindungbackground the invention
Die vorliegende Erfindung bezieht sich auf ein Verfahren zum Ausbilden von Höckern auf einer Halbleiterchip- oder Leiterplatten-(PCB-: printed circuit board)Umgebung. Insbesondere bezieht sich die vorliegende Erfindung auf ein Verfahren zum Ausbilden von mehrschichtigen Kontaktstellen zur Flip-Chip-Kontaktierung unter Verwendung von Metallpulvern und lokalisierter Bestrahlung.The The present invention relates to a method of forming of humps on a semiconductor chip or printed circuit board (PCB) board) environment. In particular, the present invention relates to a method of forming multi-layer pads for flip-chip contacting using metal powders and localized irradiation.
Eine typische Flip-Chip-Anordnung verwendet eine direkte elektrische Kontaktierung eines Kopf über angeordneten Halbleiterchips auf einem Substrat oder einer Leiterplatte mittels leitfähiger Höcker. Im Allgemeinen wird eine Flip-Chip-Anordnung in drei Stufen ausgebildet, d.h. Ausbilden von Höckern auf einem Chip, Anbringen des behöckerten Chips an einer Platine oder einem Substrat und Auffül len des unter dem behöckerten Chip verbleibenden Raumes mit einem elektrisch nicht leitfähigen Material.A typical flip-chip arrangement uses a direct electrical Contacting a head over arranged semiconductor chips on a substrate or a printed circuit board by means of conductive Cusps. in the Generally, a flip-chip assembly is formed in three stages, i.e. Forming bumps on a chip, attaching the humped Chips on a board or a substrate and Auffül len of the the humped Chip remaining space with an electrically non-conductive material.
Ein leitfähiger Höcker hat in einer Flip-Chip-Anordnung mehrere Funktionen, wie etwa Bereitstellen einer elektrischen Verbindung zwischen einem Halbleiterchip und einem Substrat und Bereitstellen eines thermisch leitfähigen Pfades, um Wärme von dem Halbleiterchip an das Substrat abzuführen. Der Höcker stellt auch einen Teil der mechanischen Anbringung auf dem Substrat dar und wirkt als ein Abstandshalter zum Verhindern eines elektrischen Kontaktes zwischen dem Halbleiterchip und den Leitern des Substrats.One conductive cusp has in a flip-chip arrangement several functions, such as providing an electrical connection between a semiconductor chip and a substrate and providing a thermally conductive Path to heat dissipate from the semiconductor chip to the substrate. The cusp also provides a part the mechanical attachment to the substrate and acts as a Spacer for preventing electrical contact between the semiconductor chip and the conductors of the substrate.
Es gibt viele Verfahren zum Ausbilden von Höckern auf einem Wafer-Substrat. Ein Verfahren zum Ausbilden von Höckern umfasst ein Ausbilden einer Photoresistschicht, die Öffnungen aufweist, die mit Bondflecken auf dem Wafer-Substrat fluchten, Anbringen einer Lötpaste in den Öffnungen mittels Siebdruck und Schmelzen oder Wiederverflüssigen der Lötpaste, um einen Höcker auszubilden. Die Öffnungen können durch Bestrahlen und Entwickeln des Photoresist ausgebildet werden.It There are many methods of forming bumps on a wafer substrate. A method of forming bumps includes forming a bump Photoresist layer, the openings which are aligned with bonding pads on the wafer substrate, attaching a soldering paste in the openings by screen printing and melting or re-liquefying the solder paste, around a cusp train. The openings can be formed by irradiating and developing the photoresist.
Das Problem dieses Verfahrens ist, dass zur Bearbeitung jedes Stücks des Wafer-Substrats eine neue Photoresistschicht erforderlich ist. Ein weiteres Problem ist die Notwendigkeit, die Photoresistschicht durch chemische Lösungen zu entfernen, was Chemieabfall erzeugt. Ein noch weiteres Problem ist, dass der Höckerüberstand (Höckerhöhe) von der Dicke der Photoresistmaske abhängt. Um einen höhe ren Überstand zu erreichen, ist eine dickere Photoresistschicht erforderlich.The Problem of this procedure is that to process each piece of the Wafer substrate a new photoresist layer is required. One Another problem is the need to penetrate the photoresist layer chemical solutions to remove what generates chemical waste. Another problem is that the bump supernatant (Hump height) of the thickness of the photoresist mask depends. To a higher supernatant To achieve this, a thicker photoresist layer is required.
Wenn jedoch eine kleine oder feine Teilung (Höckerabstand) gefordert ist, ist die maximal mögliche Dicke der Photoresistschicht beschränkt. In der Praxis haben die Öffnungen in der Photoresistschicht typischerweise eine umgekehrt konische Form, d.h. die Öffnungen laufen auf ein schmales Ende bei den Bondflecken zu. Es gibt daher eine Abwägung zwischen hohem Überstand und einer kleinen Teilung.If However, a small or fine pitch (cusp spacing) is required, is the maximum possible Thickness of the photoresist layer limited. In practice, the openings have in the photoresist layer, typically a reverse conical Form, i. the openings run towards a narrow end at the bond spots. There are therefore a tradeoff between high supernatant and a small division.
Ein weiteres Verfahren zum Ausbilden von Höckern bezieht ein Mustern einer auf ein Wafer-Substat aufgebrachten zum Ausbilden von Höckerstellen sowie Photoresistschicht, Elektroplattieren einer Lötlegierung auf die Höckerstellen ein. Die Photoresistschicht wird dann entfernt, bevor die Lötverbindung wieder verflüssigt wird, um eine Kugel zu bilden. Obgleich diese Elektroplattierungsmethode eine kleine Teilung liefert, ist es ein Problem, dass nasse Chemikalien und/oder Plattierungsbadlösungen erforderlich sind. Weiter beziehen solche chemischen Prozesse gefährliche Materialien ein und müssen sorgfältig kontrolliert werden.One Another method of forming bumps involves patterning a bump on a wafer substrate applied to form bumps and photoresist layer, electroplating a solder alloy on the cusp places one. The photoresist layer is then removed before the solder joint liquefied again is to form a ball. Although this electroplating method is a Small division supplies, it is a problem that wet chemicals and / or plating bath solutions required are. Further, such chemical processes involve dangerous ones Materials and must careful to be controlled.
Im Hinblick auf das Vorangehende wäre es wünschenswert, ein Verfahren zum Ausbilden von Höckern zu haben, das kostengünstig ist und keine nassen Chemikalien einbezieht. Außerdem wäre es wünschenswert, ein Verfahren zu haben, das einen hohen Überstand (Höckerhöhe) und eine kleine oder feine Teilung (Höckerabstand) liefert.in the With regard to the foregoing it desirable to have a method of forming bumps which is inexpensive and does not involve wet chemicals. In addition, it would be desirable to have a method to have that a high supernatant (Hump height) and a small or fine pitch (bump distance) provides.
Kurze Beschreibung der ZeichnungenShort description the drawings
Die vorliegende Erfindung wird einfacher verstanden werden anhand der folgenden detaillierten Beschreibung in Verbindung mit den begleitenden Zeichnungen. Zur Vereinfachung dieser Beschreibung bezeichnen gleiche Bezugszeichen gleiche Strukturelemente.The The present invention will be understood more readily with reference to FIGS following detailed description in conjunction with the accompanying Drawings. To simplify this description, the same Reference numerals same structural elements.
Detaillierte Beschreibung der Erfindungdetailed Description of the invention
Es wird ein Verfahren zum Ausbilden mehrschichtiger Höcker oder Kontaktstellen auf einem Substrat in einer Halbleiterchip- oder Leiterplatten-(PCB-)Umgebung zur Verfügung gestellt. In der folgenden Beschreibung werden zahlreiche spezielle Details angegeben, um ein gründliches Verständnis der vorliegenden Erfindung zu ermöglichen. Der Fachmann wird jedoch verstehen, dass die vorliegende Erfindung ohne einige oder sämtliche dieser speziellen Details praktiziert werden kann. In anderen Fällen wurden wohlbekannte Bearbeitungsoperationen nicht im Detail beschrieben, um die vorliegende Erfindung nicht unnötig zu verdunkeln.It is a method for forming multilayer bumps or Contact points on a substrate in a semiconductor chip or Circuit board (PCB) environment provided. In the following Description, numerous special details are given to one thorough Understanding of to enable the present invention. However, those skilled in the art will understand that the present invention without some or all of these specific details can be practiced. In other cases were well-known machining operations are not described in detail, so as not to obscure the present invention unnecessarily.
Es
wird nun Bezug genommen auf
Um
eine solche Reinigung durchzuführen wird
eine mit einer oder mehreren Öffnungen
Die Öffnungen
Es
wird nun Bezug genommen auf
Das
erste Metallpulver
Es
wird Bezug genommen auf
Es
wird nun Bezug genommen auf
Das
zweite Metallpulver
Es
wird nun Bezug genommen auf
Der
zweite Bestrahlungsstrahl
Bei
einer anderen Ausführungsform
der vorliegenden Erfindung können
die Höcker
auf einer Fleckenmetallurgie ausgebildet werden, die auf den Bondflecken
Bei
einer anderen Ausführungsform
kann der oben beschriebene Bestrahlungsstrahl zum Schmelzen oder
Wiederverflüssigen
der Metallpulver (
Es
wird Bezug genommen auf
Obgleich
der obige Prozess in Beziehung zum Ausbilden von Höckern auf
einem Substrat
Die vorliegende Erfindung ist insbesondere vorteilhaft, um Prozesskosten zu reduzieren, da sie minimales Werkzeug erfordert, keine nasschemischen Prozesse einbezieht und eine wiederverwendbare Maskierungsplatte benutzt. Die Maskierungsplatte kann eliminiert werden, wenn ein programmierbarer Einzellaserstrahl verwendet wird, um die Metallpulver selektiv zu schmelzen.The The present invention is particularly advantageous for process costs because it requires minimal tools, no wet chemical Involves processes and a reusable masking plate used. The masking plate can be eliminated if a Programmable single laser beam is used to make the metal powder to selectively melt.
Ein weiterer Vorteil der vorliegenden Erfindung ist der hohe Überstand, der durch zwei- oder mehrschichtige Höcker im Vergleich zu einschichtigen Höckern erreicht werden kann. Bei hohen Temperaturen werden der Siliziumwafer und die Höcker thermisch-mechanischer Spannung, verursacht durch unterschiedliche Ausdehnungsraten in dem Siliziumwafer und einer externen Oberfläche, wie etwa einer PCB, ausgesetzt. Die unterschiedlichen Ausdehnungsraten sind verursacht durch Fehlanpassung von thermischen Ausdehnungskoeffizienten (CTE: coefficients of thermal expansion) in unterschiedlichen Materialien. Exzessive Spannung kann Siliziumbruch oder Höckerbruch verursachen. Ein hoher Überstand mildert die durch CTE-Fehlanpassung verursachte Spannung und verbessert daher die Zuverlässigkeit der Höckerverbindung.Another advantage of the present invention is the high supernatant that can be achieved by bilayer or multilayer bumps compared to single layer bumps. At high temperatures, the silicon wafer and bumps are subjected to thermal-mechanical stress caused by different rates of expansion in the silicon wafer and an external surface, such as a PCB. The different expansion rates are caused by mismatch of thermal expansion coefficients (CTE: coefficients of thermal expansion) in different materials. Excessive stress can cause silicon breakage or bump failure. A high protrusion mitigates the stress caused by CTE mismatch and therefore improves the reliability of the bump bond.
Ein
weiterer Vorteil der vorliegenden Erfindung sind reduzierte Höckergröße und Höckerteilung.
Durch Ausbilden des zweiten Höckers
Weitere Ausführungsformen der Erfindung sind für den Fachmann aus den Überlegungen der Beschreibung der Praxis der Erfindung erkennbar. Weiter wurde eine bestimmte Terminologie zum Zwecke der Beschreibungsklarheit verwendet und nicht, um die vorliegende Erfindung zu beschränken. Die oben beschriebenen Ausführungsformen und bevorzugten Merkmale sollten als beispielhaft betrachtet werden, wobei die Erfindung durch die anhängenden Ansprüche definiert wird.Further embodiments of the invention are for the expert from the considerations the description of the practice of the invention recognizable. Next was a certain terminology for the purpose of descriptive clarity used and not to limit the present invention. The above described embodiments and preferred features should be considered exemplary the invention being defined by the appended claims becomes.
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/263,440 US7279409B2 (en) | 2005-10-31 | 2005-10-31 | Method for forming multi-layer bumps on a substrate |
US11/263,440 | 2005-10-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE102006051151A1 true DE102006051151A1 (en) | 2007-06-06 |
Family
ID=37996971
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE102006051151A Withdrawn DE102006051151A1 (en) | 2005-10-31 | 2006-10-30 | Method of forming multi-layer bumps on a substrate |
Country Status (7)
Country | Link |
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US (1) | US7279409B2 (en) |
JP (1) | JP5079304B2 (en) |
KR (1) | KR101279234B1 (en) |
CN (1) | CN1959531A (en) |
DE (1) | DE102006051151A1 (en) |
SG (1) | SG131913A1 (en) |
TW (1) | TWI330876B (en) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
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EP2387803B1 (en) | 2009-01-14 | 2016-07-13 | Philips Lighting Holding B.V. | A method for deposition of at least one electrically conducting film on a substrate |
JP5316261B2 (en) * | 2009-06-30 | 2013-10-16 | 富士通株式会社 | Multichip module, printed circuit board unit and electronic device |
TW201133745A (en) * | 2009-08-27 | 2011-10-01 | Advanpack Solutions Private Ltd | Stacked bump interconnection structure and semiconductor package formed using the same |
JP5397243B2 (en) * | 2010-01-28 | 2014-01-22 | 日立化成株式会社 | Manufacturing method of semiconductor device and adhesive sheet for connecting circuit member |
US9636782B2 (en) | 2012-11-28 | 2017-05-02 | International Business Machines Corporation | Wafer debonding using mid-wavelength infrared radiation ablation |
US20140144593A1 (en) | 2012-11-28 | 2014-05-29 | International Business Machiness Corporation | Wafer debonding using long-wavelength infrared radiation ablation |
TWI610374B (en) * | 2013-08-01 | 2018-01-01 | 格芯公司 | Adhesives for bonding handler wafers to device wafers and enabling mid-wavelength infrared laser ablation release |
DE102013220886A1 (en) * | 2013-10-15 | 2015-04-16 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method for producing a metallic contacting structure on a semiconductor substrate |
US9474162B2 (en) | 2014-01-10 | 2016-10-18 | Freescale Semiocnductor, Inc. | Circuit substrate and method of manufacturing same |
CN105632910B (en) * | 2015-03-31 | 2021-04-30 | 中国科学院微电子研究所 | Gate conductor layer and manufacturing method thereof |
CN108807202B (en) * | 2018-06-11 | 2019-11-12 | 广东海洋大学 | A kind of method of laser production solder bump |
CN112599642A (en) * | 2020-12-18 | 2021-04-02 | 泰州隆基乐叶光伏科技有限公司 | Welding method of battery piece and photovoltaic module |
Family Cites Families (13)
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JPH05110241A (en) * | 1991-10-18 | 1993-04-30 | Mitsubishi Electric Corp | Method of supplying solder to printed board |
JP3193100B2 (en) * | 1992-03-13 | 2001-07-30 | 富士通株式会社 | Semiconductor device |
JP2586811B2 (en) | 1993-11-29 | 1997-03-05 | 日本電気株式会社 | Solder bump formation method |
US5470787A (en) | 1994-05-02 | 1995-11-28 | Motorola, Inc. | Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same |
JPH07321444A (en) * | 1994-05-24 | 1995-12-08 | Fujitsu Ltd | Metal pattern forming method |
US5539153A (en) | 1994-08-08 | 1996-07-23 | Hewlett-Packard Company | Method of bumping substrates by contained paste deposition |
JPH08204322A (en) * | 1995-01-26 | 1996-08-09 | Ibiden Co Ltd | Forming method for bump |
JPH11145176A (en) * | 1997-11-11 | 1999-05-28 | Fujitsu Ltd | Method for forming solder bump and method for forming preliminary solder |
JP2000228576A (en) * | 1999-02-08 | 2000-08-15 | Ricoh Co Ltd | Circuit board with bump and its manufacture |
JP2000252313A (en) * | 1999-02-25 | 2000-09-14 | Sony Corp | Formation of plating film and fabrication of semiconductor device |
JP2002026056A (en) | 2000-07-12 | 2002-01-25 | Sony Corp | Method for forming solder bump and method for manufacturing semiconductor device |
JP2002076043A (en) | 2000-08-28 | 2002-03-15 | Mitsubishi Electric Corp | Bump forming method, semiconductor device, and bump forming device |
JP2005235856A (en) * | 2004-02-17 | 2005-09-02 | Matsushita Electric Ind Co Ltd | Flip chip packaging method and apparatus thereof |
-
2005
- 2005-10-31 US US11/263,440 patent/US7279409B2/en not_active Expired - Fee Related
-
2006
- 2006-10-27 SG SG200607481-9A patent/SG131913A1/en unknown
- 2006-10-30 DE DE102006051151A patent/DE102006051151A1/en not_active Withdrawn
- 2006-10-30 JP JP2006294279A patent/JP5079304B2/en not_active Expired - Fee Related
- 2006-10-31 KR KR1020060106196A patent/KR101279234B1/en active IP Right Grant
- 2006-10-31 TW TW095140238A patent/TWI330876B/en not_active IP Right Cessation
- 2006-10-31 CN CNA200610148685XA patent/CN1959531A/en active Pending
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US20070099413A1 (en) | 2007-05-03 |
KR101279234B1 (en) | 2013-06-26 |
TW200725768A (en) | 2007-07-01 |
KR20070046756A (en) | 2007-05-03 |
JP5079304B2 (en) | 2012-11-21 |
US7279409B2 (en) | 2007-10-09 |
SG131913A1 (en) | 2007-05-28 |
JP2007129220A (en) | 2007-05-24 |
CN1959531A (en) | 2007-05-09 |
TWI330876B (en) | 2010-09-21 |
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