DE102006043668A1 - Controller for controlling semiconductor memory chip of semiconductor memory module, has control device for generating control signals, for controlling reading-and writing access to semiconductor memory chip - Google Patents

Abstract

The controller (SB) has a control device for generating control signals, for controlling a reading-and writing access to a semiconductor memory chip (HB), for generating address signals for addressing memory cells of the semiconductor memory chip for reading-and writing access. An address signal is produced by multiple address connections. The control device has a selector switch, with the address connections that is supplied by the selector switch selectively of an address signal or a control signal. Independent claims are also included for the following: (1) a semiconductor memory module with a controller, which has several semiconductor memory components (2) a method for operating a semiconductor memory module, which involves making a semiconductor memory module.

Description

The The invention relates to a control module for controlling a semiconductor memory module a semiconductor memory module, wherein the control module via various Buses for transmission of control and address signals with semiconductor memory devices the semiconductor memory module is connected. Furthermore it concerns The invention relates to a semiconductor memory module in which a control module via various Buses for transmission of control and address signals connected to semiconductor memory devices is. The invention also relates to a method for operating a such semiconductor memory module.

In a semiconductor memory module, a plurality of semiconductor memory modules are arranged on a module board, which communicate via a control module with the environment of the memory module. 1 shows a module board MP on which a control block SB is arranged. The control module SB is placed in a middle position on an upper side of the module board. On its left and right side semiconductor memory devices HB and on the underside of the module board further semiconductor memory devices HB are arranged on the top of the module board. The semiconductor memory modules are connected via different buses for the transmission of clock, control, address and data signals to the control module. The control module has for this purpose a number of clock, control, address and data connections.

Each of the semiconductor memory devices HB contains one or more memory chips C. 2A shows a semiconductor memory device HB, in which four memory chips C are placed in a stack arrangement. Each of the memory chips comprises a memory cell array in which a plurality of memory cells are contained. 2 B shows a memory chip with a memory cell array in an enlarged view. The memory cells are arranged along word lines WL for activating one of the memory cells and bit lines BL for writing a memory state into one of the memory cells or for reading out a memory state from one of the memory cells.

in the Case of Dynamic Random Access Memory (DRAM) memory cells a memory cell, a selection transistor AT and a storage capacitor SC. The storage capacitor SC leaves over a corresponding control signal on the word line WL conductive with the bit line BL for connect a memory access. To improve the signal integrity at a Write access becomes a termination resistor on the memory chip (On-The Termination Resistor) ODTW, over which a data bus is for transmission the data from the memory chip is terminated, switched active.

to Activation of the termination resistor will be the corresponding one Semiconductor memory module or contained therein Memory chip from the control block SB with a control signal ODTS (On-the-termination signal) controlled. Furthermore, the Semiconductor memory modules for selecting one of them Memory chips with a control signal CS (Chip Select Signal) driven. Address signals are generated at address terminals of the control block SB and over Address busses the memory chips for selecting egg ner memory cells of the memory cell array for the memory access supplied.

For a memory module of the 2Rx4 module configuration, there are a total of 36 memory chips on a semiconductor memory module. A rank indicates the number of memory blocks necessary to provide the bus width to the control block. Since the bus width generally comprises 72 bits, an organization form x4 of the semiconductor memory belongs to a rank 18 memory chips. If the semiconductor memory module of 1 is operated in a configuration 2Rx4, two memory chips are arranged in each of the semiconductor memory devices, so that a total of 36 memory chips are located on the module board.

Since, in particular, the control components SB have a high power consumption, it is endeavored to reduce the number of semiconductor memory modules for realizing a memory with a specific capacity. For example, a memory capacity of 8 GB can be realized with a semiconductor memory module of the module configuration 4Rx4, which contains semiconductor memory components with two memory chips of 1 Gbit stacked, while a memory module of the module configuration 2Rx4, the semiconductor memory modules with two memory chips stacked in each case, the memory density 1 Gbit, can only reach a storage capacity of 4 GB. This reduces the power consumption of a memory by about half if instead of using memory modules of the configuration 2Rx4 memory modules of the configuration 4Rx4 are used. In this case, for example, to build up a 64 GB memory, only eight memory modules of the 4Rx4 configuration are required, whereas to build such a memory, sixteen 2Rx4 semiconductor memory modules would be required. Since the number of control modules is thus reduced by half, the use of eight 4Rx4 semiconductor memory modules also reduces power consumption compared with the use of sixteen memory modules reduce the module configuration 2Rx4 by half.

If the semiconductor memory module of 1 In a 4Rx4 module configuration, a total of 72 memory chips are present on the module board. In each of the semiconductor memory devices, as in 2A represented, each four memory chips arranged in a stack arrangement. In order to control such a semiconductor memory module, further control signals must be generated by the control component SB in comparison to a semiconductor memory module of the configuration 2Rx4. Thus, in particular for controlling the two additional tendrils, further control signals CS (chip select) for selecting the memory chips of the additional tendrils and additional control signals ODTS for activating the termination resistors for the memory chips of the additional tendrils are required. However, the provision of additional output terminals for providing the additional control signals is associated with an increase in the chip size of the control module and an increase in the power consumption of the control module.

The The object of the present invention is a control module for controlling a semiconductor memory module of a semiconductor memory module indicate that at an increase the storage capacity of the semiconductor memory module, the number of control terminals for Generation of control signals for controlling the semiconductor memory device unchanged remains. Another object of the present invention is a semiconductor memory module with such a control module indicate that at an increase the storage capacity of the semiconductor memory module, the number of control connections to Generation of control signals for controlling the semiconductor memory device unchanged remains. Another object of the present invention is a method of operating such a semiconductor memory module specify the number of control connections of a control block for controlling a semiconductor memory device of the semiconductor memory module at an increase the storage capacity the semiconductor memory module remains unchanged.

The Invention with respect to the control module is solved by a control block for controlling a semiconductor memory device a semiconductor memory module with a control device for generating control signals for controlling a read and write access on the semiconductor memory device and for generating address signals for addressing memory cells of the semiconductor memory device for one Read and write access. The control module also has several address connections for providing the address signals. The control device has at least one selection circuit. By means of at least one Selection circuit is the at least one of the address terminals optional one of the address signals or one of the control signals can be fed.

In dependence of whether the semiconductor memory module in a configuration 2Rx4 or in a configuration 4Rx4 is operated, can thus be generate different signals at an address port. Thereby it is possible to use the control module both with a 2Rx4 configuration memory module as well as with a semiconductor memory module of the configuration 4Rx4 to use. Although to operate a semiconductor memory module in the configuration 4Rx4 additional Control signals (chip select signals) for selecting memory chips, the two additional ones Belong to tendrils, and further at least one further control signal (on-the-termination signal) for Activation of on-die termination resistors of Memory chips of the two additional tendrils are required, the number of control outputs for generating these signals not increased at the control block. Thus, for example, a control module, the only previously for a 2 tendril support was provided, even for a 4-rank semiconductor memory module can be used.

According to one Further development of the control module, the semiconductor memory module several memory chips on. By means of the control device is a first of the control signals can be generated. By means of the first of the control signals let yourself one of the memory chips for select a read and write access.

According to one another embodiment the control module is a second by means of the control device the control signals generated. The memory chips each include an activatable termination resistor suitable for a Write access to the respective memory chip is activated. through the second of the control signals is the termination resistor one of the multiple memory chips activatable.

Of the Control module preferably comprises a first of the address terminals. The Control device has a first selection circuit. through the first selection circuit is the first of the address terminals of a the address signals or the first of the control signals can be fed.

According to another feature of the control module, it has a second one of the address terminals. The control device comprises a second selection circuit. By means of the second selection circuit is the second of Adressanschlüs se one of the address signals or the second of the control signals supplied.

According to one another embodiment of the control module, the control module comprises a plurality of control terminals for Providing the control signals. The control device has a third selection circuit. By means of the third selection circuit a first of the control terminals is optionally the first of the Control signals or the second of the control signals fed.

In a preferred embodiment the control device comprises a fourth selection circuit. through the fourth selection circuit is a second of the control terminals of a of several of the second control signals, each of which is different the memory chips for select a read and write access, can be fed.

in the The following is a semiconductor memory module is also given solves the task. The semiconductor memory module comprises a control module according to a the above embodiments. The semiconductor memory module further comprises a plurality of semiconductor memory devices. Furthermore, a module board is provided, on which the control module and the plurality of semiconductor memory devices are arranged such that the plurality of Halbleiterspeicherbau stones to a left and right Side of the control block are arranged. The address connections of the Control blocks are each about a bus connected to the semiconductor memory devices. one the bus connected to the first of the address terminals connects the semiconductor memory modules on the left and right side of the control module with the control module. The semiconductor memory modules are preferably operated in a module configuration 4Rx4 or 4Rx8.

in the The following will be a method of operating a semiconductor memory module specified. The method provides for providing a semiconductor memory module according to the embodiment given above in front. The semiconductor memory module is in a first configuration operated when the semiconductor memory module a first number of Has tendrils, and operated in a second configuration, though the semiconductor memory module has a second number of vines. One of the control signals for controlling a read and write access on the semiconductor memory device is at one of the address terminals of the Control module of the semiconductor memory module generated when the semiconductor memory module is operated in the first configuration. One of the address signals, a floating potential or a reference potential is applied to the one the address connections generated when the semiconductor memory module in the second configuration is operated.

Further embodiments the control module, the semiconductor memory module and the method for operating the semiconductor memory module are the subclaims remove.

The Invention will be described below with reference to figures, the embodiments of the present invention, explained in more detail.

It demonstrate:

1 an embodiment of a semiconductor memory module with a control module and semiconductor memory devices,

2A an embodiment of a semiconductor memory device with memory chips,

2 B an embodiment of a memory chip of a semiconductor memory device,

3 an embodiment of a control module for controlling semiconductor memory devices of a semiconductor memory module,

4 A first embodiment of a control device of a control module for controlling semiconductor memory devices of a semiconductor memory module,

5 a first arrangement of bus lines for transmitting control signals from a control module to semiconductor memory modules of a semiconductor memory module,

6 a second embodiment of a control device of a control module for controlling semiconductor memory devices of a semiconductor memory module,

7 a second arrangement of bus lines for transmitting control signals from a control module to semiconductor memory modules of a semiconductor memory module,

8th A third embodiment of a control device of a control module for controlling semiconductor memory devices of a semiconductor memory module,

9 a third arrangement of bus lines for transmitting control signals from a control device to semiconductor memory devices of a semiconductor memory module.

3 shows an embodiment of a control block SB for controlling semiconductor memory devices of a semiconductor memory module. The control module SB has a control device CAD for generating control and address signals. The control device CAD is connected to external terminals of the control module. For example, control signals SCS for selecting memory chips which are arranged stacked in the semiconductor memory modules can be generated at the external terminals CS0,... CSn. Furthermore, a control signal ODTS for activating a termination resistance of the memory chips during a write access can be generated in each case at external connections ODT0,..., ODTn, which are connected to the control device CAD. Address signals SA can be generated at address terminals A0, ... An.

Of the Control block SB points over it In addition, a control device DQD, the generation and the Reception of data signals controls that transmit to the semiconductor memory devices are received or from the semiconductor memory devices become. The control device DQD is for this purpose with data connections DQ0, ..., DQn connected. To a crosstalk between the control and address signals on the one hand and the data signals On the other hand, to avoid the control devices DQD and CAD arranged separately.

4 shows an embodiment of a control device CAD a control module for controlling a semiconductor memory module with memory chips memory density 1 Gbit. On the output side, the control device generates various control signals, which are generated at external terminals of the control module. The control module has external address terminals A0L, ..., A15L to the left and address terminals A0R, ..., A15R to the right. Furthermore, the control module has external connections CS0L, CS1L to the left and CS0R, CS1R to the right, at which control signals for selecting the memory chips of the rack 0 and the rack 1 can be generated.

One Control signal SCS0L for activating the memory chips of the bank 0, which are located on the left side of the module board is supplied to a control terminal CS0L, on which a bus BCS0L is arranged. For selecting memory chips of Ranks 0, which is placed on the right side of the control block are at a control terminal CS0R, which is connected to a bus BCS0R connected to the right side of the control block, a control signal SCS0R generated. To select memory chips that belong to the rank 1 belong, At a control terminal CS1L on the left side, a control signal is generated SCS1L generates that over a bus BCS1L the memory chips on the left side of the module board supplied becomes. At a control connection CS1R on the right side of the control module a control signal SCS1R is generated, which via a bus BCS1R the semiconductor memory devices, which are placed on the right side of the control module, is supplied.

to Activation of the termination resistance of the memory chips Tanks 0 and 1 will be on a control port ODTL on the left Side of the control block generates a control signal SODT0L, which via a Bus BODT0L the memory chips of tendril 0 and 1 on the left side fed to the control module becomes. Similarly, on the right side of the control block at a Control terminal ODTR generates a control signal SODT0R, which via a Bus BODT0R the memory chips of tendril 0 and 1 on the right side of the control module for activating the termination resistor supplied becomes.

to Selection of memory chips of tendrils 2 and 3 are further control signals SCS2 and SCS3 required generated by the control device CAD Need to become. According to the invention, the control signal SCS2 for selecting memory chips of rank 2 and the control signal SCS3 for selecting Rank 3 memory chips at an address port A15L and an address terminal A15R generated for generating Address signals SA15L and SA15R are provided, in particular at a semiconductor memory module with memory chips of memory density 1 Gbit but not used.

the Address connection A15L can be via a selection circuit M1A supply the control signal SCS2 or the address signal SA15L. The address connection A15R can be over a selection circuit M2A the control signal SCS3 or the address signal Feed SA15R. When the address terminal A15L or the address terminal A15R, the control signals SA15L or SA15R are supplied to the output terminals A15L or A15R a BA15L bus leading to the memory chips on the leads left side of the module board, or a bus BA15R, which connects to the memory chips on the right side of the module board, connected. When the address terminal A15L, the control signal SCS2 supplied if a bus BCS2 is connected to the address connection A15L, the control signal SCS2 for selecting the memory chips of the rank 2 the memory chips on the left and right side of the control module supplies. When the control signal SCS3 is supplied to the address terminal A15R, is connected to the address terminal A15R, a bus SCS3, the the control signal SCS3 for selecting memory chips of the ranks 3 leads to the memory chips on the left and right side of the control module.

In a semiconductor memory module with Spei Also, the memory chips 1 Gbit, the address terminal A14L, which is arranged on the left side of the control block SB, and the address terminal A14R, which is arranged on the right side of the control block, not used. Therefore, according to the invention, the control signals SODT1L and SODT1R for activating the termination resistances of the memory chips of the ranks 2 and 3 are generated at these address terminals. The address signal SA14L and the control signal SODT1 may be supplied via a selection circuit M3A to the address terminal A14L to which an address bus BA14L for transmitting the address signal SA14L or a control bus BODT1L for transmitting the control signal SODT1L is connected.

As well is the address connection A14R on the right side of the control module connected to a selection circuit M4A. Via selection circuit M4A can be the address terminal A14R either the address signal SA14R feed that over one Bus BA14R the memory chips on the right side of the control block is fed or feed the control signal SODT1R. In the latter case, a control bus is to the address terminal A14R BODT1R for transmission the control signal SODT1R to the memory chips of the ranks 2 and Ranks 3 connected to the right side of the control block.

The Control of the selection circuits, which are designed as multiplexers could be, done via a Control circuit CTR. In a possible embodiment reads the control circuit CTR upon activation of the semiconductor memory module a memory circuit EP arranged on the memory chip, out. A memory state stored in the memory circuit EP indicates whether the control block SB in a module configuration 2Rx4 or in a module configuration 4Rx4 or 4Rx8 is operated.

in the the latter case becomes the selection circuits M1A, M2A, M3A and M4A controlled such that the control signal SCS2 the address terminal A15L, the control signal SCS3 to the address terminal A15R and the control signal SODT1L the address terminal A14L and the control signal SODT1R the address terminal Fed to A14R becomes. If the semiconductor memory module in a configuration with two Tendrils, the address signals SA14L, SA14R, SA15L or SA15R address terminals A14L, A14R, A15L and A15R fed. If these address signals due to the small storage capacity of the semiconductor memory module not used, the address terminals A14L, A14R, A15L and A15R become on a floating potential or a reference potential, for example a ground potential, laid.

5 shows a first arrangement of bus lines for transmitting the control signals SCS to select memory chips of different tendril. The buses BCS0L and BCS1L run from the control module to the semiconductor memory modules on the left side of the control module and are each terminated at their ends with a terminating resistor AW. Buses BCS0R and BCS1R run from the control block to semiconductor memory blocks, which are located on the right side of the control block. They are each terminated with a terminator. The buses BCS2 and BCS3 run from the address terminals A15L and A15R of the control module to semiconductor memory modules, which are arranged on the left and right side of the control module. The buses BCS2 and BCS3 are each terminated at their two ends with a terminating resistor AW.

The Buses BODT0L and BODT1L connect the semiconductor memory devices on the left side of the control block with the control block. The buses BODT0R and BODT1R are connected to the semiconductor memory devices, which are arranged to the right of the control block, connected. All buses BODT0L, BODT0R, BODT1L and BODT1R are each terminated completed.

6 shows an embodiment of a control device CAD a control module for controlling a semiconductor memory module with memory chips memory density 2 Gbit. Due to the opposite to the embodiment in 4 With double storage density, the address connections A14L, A14R, A15L and A15R not used in a semiconductor memory module with memory chips of the memory density 1 Gbit are not all available for a memory module with memory chips of the memory density 2 Gbit in the configuration 4Rx4 or 4Rx8. In a semiconductor memory module with memory chips of memory density 2 Gbit and the module configuration 4Rx4 or 4Rx8 only the address terminals A15L and A15R are not used.

According to the invention Selection circuits M1B, ..., M6B to the control terminals CS0L, CS1L, CS0R and CS1R and connected to the two address terminals A15L and A15R, by means of which either two different signals can be fed to the control and address terminals.

Similar to a semiconductor memory module of configuration 4Rx4 or 4Rx8 with memory chips of memory capacity 1 Gbit is in a semiconductor memory module of the configuration 4Rx4 or 4Rx8 with memory chips of the Storage Capacity 2 Gbit at the address terminal A15L optionally the address signal SA15L or the control signal SCS2 for selecting the memory chips belonging to the rank 2 selected. When the address signal SA15L is supplied to the address terminal A15L, a bus line BA15L is connected to the address terminal A15L, via which the memory chips on the left side of the control module are driven with the address signal SA15L. When the control signal SCS2 is supplied to the address terminal A15L during operation of the semiconductor memory module in the memory configuration 4Rx4, a bus line BCS2 which connects the control signal SCS2 to both the memory chips on the left side of the control module and the memory chips on the right side of the controller is connected to the address terminal A15L Feeds control module.

the Address connection A15R is dependent from the memory configuration 2Rx4 or 4Rx4 or 4Rx8 either the address signal SA15R or the control signal SCS3 for selection the memory chips belonging to the Rank 3, supplied. The address connection A15R is in the first case with a bus BA15R for the transmission of the address signal SA15R connected to the memory chips on the right of the control module is connected. In the second case is the address connection A15R is connected to a bus BCS3 which receives the control signal SCS3 both the memory chips on the left as well as the memory chips on the right side of the control block, which belong to the rank 3 supplies.

The control terminals CS1L and CS1R leaves over the selection circuits M3B and M4B optionally the control signal SCS1L to select memory chips of Rank 1, which is on the left of the control module, or the control signal SCS0 for selection of memory chips of rank 0, both on the left and on the right side of the control module. If the control terminal CS1L is supplied with the control signal SCS1L, is connected to the control terminal CS1L a bus BCS1L, the the control signal SCS1L supplies the memory chips of rank 1, the are placed on the left side of the control block. If that Semiconductor memory module in configuration 4Rx4 respectively 4Rx8 is operated, the control signal SCS0, with which the Select Memory Chips of Rank 0 let, the control terminal CS1L supplied. In this case is on the control terminal CS1L a bus BCS0 connected to all Memory chips of rank 0 on the left and right side of the control module connected is.

At the Operation of the semiconductor memory module in the configuration 2Rx4 the control terminal CS1R, the control signal SCS1R supplied via the Bus BCS1R the memory chips on the right side of the control block supplied that belongs to Rank 1. When operating the semiconductor memory module in the configuration 4Rx4 or 4Rx8, the control connection CS1R becomes the control signal Supplied to SCS1, with which all memory chips of Rank 1 to let. In this case, a bus BCS1 is connected to the control terminal CS1R connected to all the semiconductor memory devices of the Rank 1 connected on the left and right side of the control block is.

the Control connection CS0L, when operating the semiconductor memory module in the memory configuration 2Rx4 the control signal SCS0L is supplied, with the memory chips of rank 0, which is on the left of the control module let, be over the selection circuit M1B supplies the control signal SODT1L when the semiconductor memory module in configuration 4Rx4 respectively 4Rx8 is operated. By means of the control signal SODT1L can be the termination resistors the memory chips of Rank 2 and Rank 3 activate on the left side of the control module are connected. In this case is connected to the control terminal CS0L a bus BODT1L, the with the memory chips of Rank 0 and Rank 1 on the left the control module is connected. When the control terminal CS0L by means of a suitable control of the selection circuit M1B the Control signal SCS0L supplied If a bus BCS0L is connected to the control terminal CS0L, to the memory chips of Rank 0, which is on the left side of the Control blocks are connected, is connected.

the Control terminal CS0R is the control signal SCS0R on the Selection circuit M2B supplied, if the semiconductor memory module in the configuration 2Rx4 operated becomes. By means of the control signal SCS0R, via the bus BCS0R the memory chips on the left side of the control module, the memory chips of the Rank 0 for select a read or write access. If the semiconductor memory module in the configuration 4Rx4 or 4Rx8 is, is the control terminal CS0R, the control signal SODT1R on the Selection circuit M2B supplied. By means of the control signal SODT1R, the termination resistances of the Memory chips of Rank 2 and Rank 3, those on the right of the control module are activated.

The control signals SODT0L and SODT0R, which are provided for activating the termination resistors of the memory chips belonging to the 0 and 1 tendrils, are further supplied to control terminals ODTL and ODTR to which the buses BODT0L and BODT0R are connected. The control connections ODTL and ODTR are thus intended exclusively for the generation of the ODT control signals. The control signal SODT0L is forwarded via the bus BODT0L to the memory chips of rank 0 and rank 1, which are arranged to the left of the control module. Via the bus BODT0R the control signal SODT0R is forwarded to all semiconductor memory modules of the rank 0 and the rank 1, which are placed on the right side of the control module.

The Type of configuration in which the semiconductor memory module operates is in a memory circuit EP, which is on the module board MP is stored. The memory circuit EP can, for example as an electrically programmable memory circuit (EPROM memory circuit) is formed be. When activating the semiconductor memory module reads a Control circuit CTR the memory state of the memory circuit EP out. If the semiconductor memory module in the configuration 4Rx4 or 4Rx8 is operated, the selection circuits M1B, ..., M6B then controlled by the control circuit CTR, that the control signal SODT1L the control terminal CS0L, the control signal SODT1R the control terminal CS0R, the control signal SCS0 the control terminal CS1L, the control signal SCS1 the control terminal CS1R and the control signals SCS2 and SCS3 address connections Fed to A15L and A15R become.

If the semiconductor memory module with memory chips of a storage capacity of 2 Gbit is operated in the configuration type 2Rx4, the selection circuits M1B, ..., M6B after reading the memory state of the memory circuit EP controlled by the control circuit CTR such that the control signal SCS0L the control terminal CS0L, the control signal SCS0R the control terminal CS0R, the control signal SCS1L the control terminal CS1L and the control signal SCS1R is supplied to the control terminal CS1R. In a semiconductor memory module 2Rx4 configuration with memory chips of 2 Gbit storage capacity the address signals SA15L and SA15R are not needed. In In this case, the address terminals A15L and A15R are on one floating potential or a ground potential. Such potentials can also be, for example, via the selection circuits the address connections respectively. If the storage capacity of the semiconductor memory module is increased in the configuration type 2Rx4, address signals SA15L and SA15R can be applied to address terminals A15L and A15R.

7 shows the bus lines for transmitting the control signals SCS and SODT to the semiconductor memory devices, which are arranged on the left and right of the control module. Starting from the control connections CS1L, CS1R, A15L and A15R, the buses BCS0, BCS1, BCS2 and BCS3 each connect semiconductor memory modules on the left and right side of the control module. Each of the bus lines is terminated at its two ends with a terminating resistor AW. Further shows 7 the course of the bus lines BODT0L, BODT0R, BODT1L and BODT1R, the course as in 5 described, corresponds.

8th shows a further embodiment of a control block SB, are generated at the control signals SCS for selecting memory chips of various tendrils and control signals SODT for activating termination resistors for the memory chips. Unlike in the 4 to 7 For each rank, own control signals SODT0,..., SODT3 are generated for activating the respective termination resistors. The control connections CS0L, CS0R, CS1L, CS1R, ODTL, ODTR, A15L and A15R are each connected to selection circuits M1C,..., M8C, to which different signals can be applied, depending on whether the semiconductor memory module is in a configuration 2Rx4 or 4Rx4 or 4Rx8, to the control and address terminals.

If the semiconductor memory module is operated in a 2Rx4 configuration are, for example, which are designed as multiplexer circuits Selection circuits M1C, ..., M8C switched such that the control signal SCS0L the control terminal CS0L, the control signal SCS0R the control terminal CS0R, the control signal SCS1L the control terminal CS1L, the control signal SCS1R the control terminal CS1R, the control signal SODTL the control terminal ODTL, the control signal SODTR the control terminal ODTR and the address signals SA15L and SA15R the control terminals Fed to A15L and A15R become.

If the semiconductor memory module in a configuration 4Rx4 respectively 4Rx8 is operated, the multiplexer circuits M1C, ..., M8C are such switched, that the control signal SCS0 the control terminal CS0L, the control signal SCS2 the control terminal CS0R, the control signal SCS1 the control terminal CS1L, the control signal SCS3 the control terminal CS1R, the control signal SODT0 the control terminal ODTL, the control signal SODT2 the control terminal ODTR and the control signals SODT1 and SODT3 the Control terminals A15L and fed to A15R become. about the control signals SCS1, ..., SCS3 are each the memory chips the tendril 0, ..., 3 select. About the control signals SODT0, ..., SODT3 let each of the termination resistors of Enable memory chips that belong to the vines 0, ..., 3.

9 shows the course of the bus line BODT0, which is connected to the control terminal ODTL, the profile of the bus line BODT1, which is connected to the control terminal A15L, the profile of the bus line BODT2, which is connected to the control terminal ODTR, and the course of the bus line BODT3, which is connected to the control terminal A15R connected. All buses BODT0, BODT1, BODT2 and BODT2 connect both semiconductor memory devices on the left and on the right side of the control module and are each terminated at their ends with a terminating resistor.

With the in the 4 to 9 According to embodiments of the control module, the control module SB can be operated both in the memory configuration 2Rx4 and in the memory configuration 4Rx4 or also 4Rx8 without additional control connections for generating control signals for selecting the memory chips of rank 2 and rank 3 and additional control connections for generating the Control signals for activating the termination resistors for the memory chips of tendrils 2 and 3 must be provided.

The Multiplexing of the control signals SCS and SODT takes place exclusively in the control device CAD and thus within the CA domain of the control module. This will cause crosstalk into the DQ-Dömane, which is formed by the control device DQD and separated from it is prevented.

HM

Semiconductor memory module

SB

control module

MP

module board

HB

Semiconductor memory device

CAD

control device for generating control signals

DQD

control device for generating data signals

ODT

control signal to activate resistors

CS

control signal for selecting memory chips

CTR

control circuit

EP

memory circuit

A14, A15

address connections

Bodt

bus for transmission the control signal ODT

BCS

bus for transmission the control signal CS

Claims (20)

Control block for controlling a semiconductor memory module a semiconductor memory module - With a control device (CAD) for generating control signals (SODT1L, SODT1R) for control a read and write access to the semiconductor memory device (HB) and for generating address signals (SA14L, SA14R, SA15L, SA15R) for addressing memory cells (SZ) of the semiconductor memory device for one Read and write access, - With several address connections (A14L, A14R, A15L, A15R) for providing the address signals (SA14L, ..., SA15R), - at the control device (CAD) at least one selection circuit (M1A, M3A), - at the at least one of the address connections (A14L, A14R, A15L, A15R) by means of the at least one selection circuit optionally one of Address signals (SA14L) or one of the control signals (SODT1L) can be fed. Control module according to claim 1, - in which the semiconductor memory module (HB) has a plurality of memory chips (C), - in which by means of the control device (CAD), a first of the control signals (SCS0L, SCS2) can be generated, - in which by means of first of the control signals (SCS2) of one of the memory chips for one Select read and write access leaves. Control module according to claim 2, - in which by means of the control device (CAD) a second of the control signals (SODT1L) can be generated, - at the memory chips each have an activatable termination resistor (ODTW), which for a write access to the respective memory chip is activated, - in which by means of the second of the control signals (SODT1L, SODT1R) the termination resistor (ODTW) can be activated on one of the several memory chips. Control module according to one of claims 1 to 3, - With a first of the address terminals (A15L) - at the control device (CAD) has a first selection circuit (M1A) having, - at the first of the address ports (A15L) by means of the first selection circuit (M1A) of one of the address signals (SA15L) or the first of the control signals (SCS2) can be fed. Control module according to claim 4, - with a second of the address terminals (A14L) - at the control device (CAD) has a second selection circuit (M3A) having, - at the second of the address terminals (A14L) by means of the second selection circuit (M3A) of one of the address signals (SA14L) or the second of the control signals (SODT1L) can be fed. Control module according to one of Claims 3 to 5, - with several control terminals (CS0L, CS1L) for providing the control signals, - in which the control device (CAD) has a third selection circuit (M1B), - in which a first of the control terminals (CS0L) by means of the third selection circuit (M3B) optionally, the first of the control signals (SCS0L) or the second of the control signals (SODT1L) can be fed. Control module according to claim 6, - in which the control device (CAD) has a fourth selection circuit (M3B), - in which a second of the control terminals (CS1L) by means of the fourth selection circuit one of several of the second Control signals (SCS0, SC1L), with each of which different the memory chips for select a read and write access, can be supplied. Control module according to one of claims 1 to 7, - With a control circuit (CTR), the input side, a configuration signal (KS) can be fed is - at the selection circuits (M1A, ..., M6B) depending on from the configuration signal (KS) from the control circuit (CTR) for selecting one of the selection circuits (M1A, M3A, M1B, M3B) supplied Signals are controlled. Control module according to one of claims 1 to 8, in which the selection circuits are each represented as a multiplexer (M1A, ..., M4A, M1B, ..., M6B) are formed. Semiconductor memory module - with a control block (SB) according to one of the claims 1 to 9, - With several semiconductor memory devices (HB), - with a Module board (MP) on which the control block and the plurality of semiconductor memory devices in such a way are arranged that the plurality of semiconductor memory devices to a left and right side of the control block are arranged - in which the address connections (A15L, A15R) of the control module via a bus (BCS2, BCS3) are connected to the semiconductor memory devices, - in which one of the buses (BCS2) connected to the first of the address ports (A15L) is connected, the semiconductor memory devices on the left and right side of the control block with the control block (SB) combines. A semiconductor memory module according to claim 10, - in which the control connections (CS1L, CS1R) of the control module via one of the buses (BCS0, BCS1) are connected to the semiconductor memory devices, - in which one of the buses (BCS0) connected to the second of the control terminals (CS1L) is connected, the semiconductor memory devices on the left and the right side of the control module connects to the control module. Semiconductor memory module according to one of claims 10 or 11, in which at a respective end of the buses (BCS0, BCS2) a Terminating resistor (AW) is arranged. Semiconductor memory module according to one of claims 10 to 12 - With a memory circuit (EP) for storing a configuration state dependent on of tendrils arranged on the semiconductor memory module, - in which the control circuit (CTR) of the control module, the selection circuits dependent on from the configuration state stored in the memory circuit (EP) for selecting one of the signals supplied to the selection circuits controls. Semiconductor memory module according to one of claims 10 to 13, wherein the semiconductor memory devices in a module configuration 4Rx4 or 4Rx8 are operated. Semiconductor memory module according to one of claims 13 or 14, wherein the memory circuit as an electrically programmable Memory is formed. Method for operating a semiconductor memory module, comprising the following steps: - Providing a semiconductor memory module according to one of the claims 10 to 15, - operate of the semiconductor memory module in a first configuration when the semiconductor memory module has a first number of tendrils, and operate the semiconductor memory module in a second configuration, if the semiconductor memory module has a second number of tendrils, - Produce one of the control signals (SCS2, SODT1L, SODT1) for controlling a Read and write access to the semiconductor memory device one of the address ports (A14L, A15L) of the control module of the semiconductor memory module when the semiconductor memory module is operated in the first configuration and generate one of the address signals (SA14L, SA15L), one floating potential or a reference potential at one of the address connections (A14L, A15L) when the semiconductor memory module in the second configuration is operated. The method of claim 16, comprising the following steps: - generating the first of the control signals (SCS2) for selecting a memory chip (C) of a semiconductor memory block for read or write access to the first of the address latch (A15L) of the control module of the semiconductor memory module when the semiconductor memory module is operated in the first configuration and generate one of the address signals (SA15L), the floating potential or the reference potential at the first one the address terminal (A15L) when the semiconductor memory module is operated in the second configuration, generating the second one of the control signals (SODT1L) at the second of the address terminals (A14L) when the semiconductor memory module is operated in the first configuration, and generating another one of the address signals (A14L), the floating potential or the reference potential at the second of the address terminals (A14L) when the semiconductor memory module is operated in the second configuration. The method of claim 16, comprising the following Steps: - Provide A semiconductor memory module according to any one of claims 10 to 15 - operate of the semiconductor memory module in a first configuration when the semiconductor memory module has a first number of vines and operating the semiconductor memory module in a second configuration, if the semiconductor memory module has a second number of tendrils, - Produce the first of the control signals (SCS2) at the first of the address terminals (A15L), when the semiconductor memory module is operated in the first configuration and generate one of the address signals (SA15L) of a floating one Potential or a reference potential at the first of the address terminals (A15L), when the semiconductor memory module is operated in the second configuration becomes, - Produce the second of the control signals (SODT1L) at the first of the control terminals (CS0L), when the semiconductor memory module is operated in the first configuration and generate a first one of the control signals (SCS0L) at the first of the control terminals (CS0L) when the semiconductor memory module in the second configuration is operated. Method for operating a semiconductor memory module, according to one of the claims 16 to 18, comprising the following steps: Determine the Number of tendrils on the semiconductor memory module by evaluation a memory state of the memory circuit (EP), wherein the memory state indicates the number of tendrils on the semiconductor memory module. Method according to one of claims 16 to 19, - in which the semiconductor memory module is operated in the first configuration when the semiconductor memory module has a number of four tendrils having, - at the semiconductor memory module is operated in the second configuration when the semiconductor memory module has a number of two tendrils having.