DE102007032780B4 - Integrated semiconductor memory, semiconductor memory module and method with adjustment of operating parameters - Google Patents

Abstract

Integrated semiconductor memory, comprising: - a terminal (IO) for external input and output of a date, - at least a first register (221) for storing a date, wherein an operating parameter of the integrated semiconductor memory is adjustable depending on the stored date, - at in which, in the case of a write access to the at least one first register (221), the data present at the connection (IO) can be written into the at least one first register, - in which, in the case of a read access to the at least one first register (221), the at least one first register at least one irreversibly programmable memory unit (231, 232) stores a second register (222), the datum in the second register (222) being dependent on a state of the first stored register on the port (IO) Memory unit (231, 232) is stored, and wherein depending on the stored in the second register (222) Da an operating parameter of the integrated semiconductor memory is settable, - a selection circuit (240) to which the data stored in the at least one first register (221) and the data stored in the second register (222) are fed on the input side, - in which the selection circuit ( 240) selects a date of the data stored in the at least one first register (221) and in the second register (222), - wherein the operating parameter of the integrated semiconductor memory is set in dependence on the date selected by the selection circuit (240), and a third register (223) for storing a datum indicating normal operation or a test and analysis operation, the selection circuit selecting in dependence on the datum stored in the third register (223).

Description

The invention relates to an integrated semiconductor memory in which operating parameters that influence the operating behavior of the integrated semiconductor memory are adjustable. The invention also relates to a semiconductor memory module in which operating parameters which influence the operating behavior of integrated semiconductor memories of the semiconductor memory module are adjustable. Furthermore, the invention relates to a method for operating an integrated semiconductor memory, in which operating parameters that influence the performance of the integrated semiconductor memory, are adjustable.

The DE 10 2004053316 A1 describes a method for inputting and outputting operating parameters of an integrated semiconductor memory, wherein the semiconductor memory has a plurality of registers for storing the operating parameters. The operating parameters can be read or written via corresponding read and write accesses.

The US 6,424,593 B1 describes a semiconductor memory device wherein internal control parameters are set based on fuse elements.

The object of the present invention is to provide an integrated semiconductor memory, a method for operating the same, and a semiconductor memory module which allow a simple operation, starting from a predetermined configuration, a test and an analysis operation without a modification of the already made as intended configurations required goods.

This object is achieved by an integrated semiconductor memory according to claim 1 and by a method according to claim 12.

Furthermore, the present invention provides a semiconductor memory module according to claim 11 comprising a plurality of semiconductor memories according to the invention.

The invention will be explained in more detail below with reference to figures showing exemplary embodiments of the present invention. Show it:

1 an integrated semiconductor memory having registers which are connected to a control circuit via a bus system,

2 an integrated semiconductor memory having a memory device for setting operating parameters of the integrated semiconductor memory,

3 an embodiment of an integrated semiconductor memory with a plurality of memory circuits for setting operating parameters of a circuit component of an integrated semiconductor memory,

4 a semiconductor memory module with a control module and a plurality of semiconductor memories.

1 shows an integrated semiconductor memory HS1, in which memory cells in a memory cell array B1, for example, a memory bank, the integrated semiconductor memory are arranged. In the memory cell array is exemplified a memory cell SZ, which is connected to a word line WL and a bit line BL. The memory cell is designed as a DRAM (Dynamic Random Access Memory) memory cell. The memory cell comprises a selection transistor AT and a storage capacitor SC. The selection transistor AT is connected to a control terminal to the word line WL. To read or write a date in the memory cell of the selection transistor AT is controlled by a high potential VPP on the word line WL, so that the storage capacitor SC is connected via the controllable path of the selection transistor to the bit line BL. An amplifier circuit, for example a sense amplifier LV, is connected to the bit line BL. The sense amplifier has a terminal for applying a voltage VBH and a terminal for applying a voltage VBL.

When reading in a data with the data value 0, the sense amplifier feeds the bit line BL, for example, the voltage VBL, which has a low potential. As a result, a low charge level representing a datum of 0 is stored in the storage capacitor of the memory cell. For writing a data having a data value of 1 into the memory cell, the sense amplifier feeds to the bit line BL the voltage VBH having a high potential level. As a result, a high charge level is stored in the storage capacitor.

For setting operating parameters of the integrated semiconductor memory, the semiconductor memory has a memory device 200 comprising a plurality of memory circuits. In 1 among others, the memory circuits are in the semiconductor memory HS1 221 and 222 intended. The memory circuits can be embodied, for example, as register circuits in which at least one datum is stored.

Depending on the data stored in the memory circuits, the operating parameters, for example the levels of the voltages VPP, VBH or VBL, are predetermined. The control voltage VPP serves, for example, for controlling a selection transistor of a memory cell or in particular also for switching a multiplexer in order, for example, to design a data flow differently. The voltage VBH indicates the level of the bit line high voltage. The voltage VBL represents the level of the bit line low voltage VBL. Furthermore, settings of receiver and transmitter circuits (RX and TX circuits), coding and decoding logic circuits including DfT (Design for Testability) circuits are determined by the data stored in the memory circuits.

The individual memory or register circuits are via a register bus 400 with a control circuit 100 connected. The memory circuits are, for example, as in 1 represented in a so-called fly-by topology connected to the register bus. In addition to the fly-by topology, other bus structures can be used.

By applying a write command SK, data can be written into the memory circuits. For writing a date in one of the memory circuits, the data to be written is applied, for example, to an external data terminal IO. By driving the control circuit 100 With a write command SK at a control terminal S100, the data applied to the data terminal IO is written into one of the memory circuits.

To read a date from one of the memory circuits, a read command LK is applied to the control terminal S100. Thereby, a in one of the memory circuits of the memory device 200 stored data read from the corresponding memory circuit and output to the data terminal IO.

For selecting one of the memory circuits, the integrated semiconductor memory HS1 has an address connection A100 for applying an address signal AS. Depending on the applied address signal, the memory circuit assigned to the address is generated by the control circuit when a read command LK or a write command SK is applied 100 selected for read or write access.

The writing and reading out of data into and out of the memory circuits as well as the addressing of the memory circuits for a read or write access can also be achieved by the driving of the control circuit 100 done with a signal protocol. This makes it possible that the control takes place via a single connection or wire. The code for a command is issued for example by a duty-cycle variation.

The to the register bus 400 connected memory circuits are partly externally readable, externally writable or designed both externally readable and externally writable. The data can be accessed both via a main interface, via which the regular functional data input and output takes place, for example via data connections (DQ connections), as well as via a side input, typically for Test purposes, be read in and out. In particular, those memory circuits which can be accessed both read and write are suitable for setting operating parameters for carrying out a functional test of the integrated semiconductor memory. In a functional test of the integrated semiconductor memory, for example, data is stored in one of the memory circuits with which an operating parameter can be set above or below the range of the operating parameter specified in a specification of the integrated semiconductor memory. As a result, for example, limit ranges can be tested when setting the operating parameters.

2 shows an integrated semiconductor memory HS2 with different memory banks B1, B2, B3 and B4. In the so-called spin region SP of the integrated semiconductor memory is a control circuit 100 arranged. The control circuit 100 is connected to the data terminal IO for inputting and outputting data. Furthermore, the control circuit 100 to the address terminal A100 for applying an address signal AS and connected to the control terminal S100 for applying a read command LK and a write command SK.

For setting operating parameters, for example for setting control voltages within the memory banks, for setting operating parameters of receiving circuits (RX circuits), transmitting circuits (TX circuits), coding and decoding logic circuits including DfT logic circuits arranged in a narrow horizontal band in the Center of the memory chip, in the spin area SP, are arranged, memory / register circuits are provided. In 2 is a storage device 200 which includes a plurality of such memory / register circuits. The memory circuits are assigned to the memory bank B1. By applying a write command SK to the control circuit 100 can be created data, which are applied to the data port IO, in the memory circuits of the memory device 200 enroll.

For selecting one of the memory circuits of the memory device 200 Address signals AS are applied to the address terminal A100. The memory circuits can thus be selected via corresponding addresses. By applying a read command LK to the control terminal S100 and an address to the address terminal A100, the individual memory / register circuits can be selected, for example, for a read access. The data read out are output externally at the data connection IO.

By such a read access to a memory circuit can be determined, for example, whether a previously written into the memory circuit date has been stored there with the correct data. To control the memory circuit 200 with internal read and write commands, with address signals and the data to be written is a bus system 400 intended.

In dependence on the data stored in the memory circuits, operating parameters of circuit components which generate, for example, control voltages for a memory bank or a memory cell array are set. For example, by storing a datum in one of the memory circuits, the levels of the control voltages VPP, VBH or VBL can be determined by a controllable voltage generator 300 be set. In addition to voltage levels, further operating parameters of circuit components of the integrated semiconductor memory can be set by storing a datum in the memory circuits. For example, delay times can be variably set or resistors and capacitances tuned, or multiplexers switched via the stored data.

3 shows the control circuit 100 , the storage device 200 and the controllable voltage generator 300 in an enlarged view. The control circuit 100 has a data terminal IO for inputting and outputting a date D. Furthermore, the control circuit 100 to an address terminal A100 for applying an address signal AS and to a control terminal S100 for applying a write command SK or a read command LK connected. The control circuit 100 is via a bus system 400 with the memory circuits 221 . 222 and 223 a storage device 200 connected. The bus system 400 has an address line 410 for transmission of address signals AS, a data line 420 for the transmission of data D and a control line 430 for transmitting a read signal RS and a control line 440 for transmitting a write signal WS.

The storage device 200 includes the memory circuits 221 . 222 and 223 as well as the storage unit 230 with the foot circuits 231 . 232 , The memory circuits 221 . 222 and 223 are each one of the decoder circuits 211 . 212 and 213 assigned. The decoder circuits are provided for decoding the address signals, the data as well as the read and write signals.

The individual memory circuits 221 . 222 and 223 can be selected via addresses that are to be applied to the address port A100. In this case, the memory circuits are assigned different addresses. The memory circuit 221 For example, the address 01h is assigned while the memory circuits 222 and 223 can be addressed via the addresses 00h or 02h. The addresses are assigned to the memory circuits in such a way that the memory circuits can be addressed via addresses of a common address space. Since the individual memory circuits within the address space are assigned different addresses, the access to the individual memory circuits can be independent of each other.

In the memory circuit 221 At least one date can be entered and read out. To describe the memory circuit 221 a date D is applied to the data connection IO. An address signal AS is applied to the address terminal A100, wherein the address of the memory circuit encoded by the address signal 221 assigned. According to the addresses exemplified above for the memory circuits, the memory circuit is selected 221 the address 01h is applied to the address terminal A100. To carry out a write access, the control connection S100 is actuated by the write command SK. The control circuit 100 then generates a write signal WS, that of the decoder circuit 211 over the control line 440 is supplied to indicate a write operation. By the address signals AS, via the address line 410 are transmitted, the memory circuit 221 addressed for the writing process. The data D to be written is applied to the data terminal IO and via the data line 420 to the memory circuit 221 transferred and into the memory circuit 221 enrolled.

To read out the written date, the memory circuit 221 again addressed via an address signal AS applied to the address terminal A100. A read command LK is applied to the control connection S100. That in the memory circuit 221 stored date is via the decoder circuit 211 and the data line 420 the control circuit 100 supplied and output at the data terminal IO.

Next to the memory circuit 221 is another memory circuit 222 intended. The memory circuit 222 is trained as a so-called Fuseregister. The memory circuit 222 is with a storage unit 230 that the foot circuits 231 and 232 includes, connected. The foot circuits 231 and 232 include fuse elements, for example, in each case a fuse wire which is severed by a laser beam to program a state of the Fuseschaltungen. The storage unit 230 is therefore designed as an irreversibly programmable memory unit.

The states of the foot circuits 231 and 232 be in the memory circuit 222 cached. The memory circuit 222 For example, it can contain latches with the footswitches 231 and 232 are connected.

For reading the memory circuit 222 the memory circuit is addressed by means of an address signal AS, which is applied to the address terminal A100. To select the memory circuit 222 For example, the address terminal A100 is driven by the address 00h. By means of a read command LK, which is applied to the control terminal S100, the read access is initiated. That from the memory circuit 222 read datum D is read by the control circuit 100 output at the data terminal IO.

In the memory circuit 223 Data can be both written in and read out. The writing of a date is performed by applying the date to be written to the data terminal IO and by driving the address terminal AS with an address signal through which the memory circuit 223 is addressed. The write command SK is applied to the control terminal S100.

For reading the in the memory circuit 223 stored date, the memory circuit is addressed by applying the corresponding address signal, for example, the address 02h to the address terminal A100. The read access is triggered by applying the read command LK to the control terminal S100. That from the memory circuit 223 read-out date can be tapped on the data port IO.

The memory circuits 221 and 222 are with a selection circuit 240 connected. The selection circuit 240 may be formed, for example, as a multiplexer. The multiplexer 240 is the output side with a circuit component 300 the integrated semiconductor memory, for example, connected to a controllable voltage generator. A control terminal S240 of the selection circuit becomes that in the memory circuit 223 stored date. Depending on the in the memory circuit 223 stored date selects the selection circuit either in the memory circuit 221 saved date or in the memory circuit 222 stored date and leads the selected date a control terminal S300 of the controllable voltage generator 300 to.

Depending on the data value of the date selected by the selection circuit 240 selected and the circuit component 300 is supplied, operating parameters of the circuit component 300 set. If the circuit component 300 is designed as a controllable voltage generator, can be adjusted by the supplied date, for example, the voltage level generated by the controllable voltage generator. In the circuit component 300 it can also be a circuit, for example a DLL or PLL circuit of an integrated semiconductor memory, in which parameters, such as a delay time or the values of controllable resistors and capacitors, over those in the memory circuits 221 and 222 stored data can be set.

In the embodiment of 3 is the memory circuit 222 For example, formed as Fuseregisterschaltung. With the in the register circuit 222 stored data may be the voltage level provided by the controllable voltage generator 300 is generated, be balanced. For this purpose, in the manufacture of the integrated semiconductor memory, the Fuseschaltungen 231 and 232 shot or shot in accordance with the voltage level to be set by a laser beam. As a result, the foot circuits are programmed irreversibly. Depending on the state of the fuse circuits are in the memory circuit 222 Data saved. By a read access to the memory circuit 222 The stored data can be read externally at the data connection IO.

The reading of the stored data can be done in particular for testing and analysis purposes. In the foot circuits 231 and 232 In addition to the control parameters for setting the operating behavior of circuit groups of an integrated semiconductor memory, an identification number for chip identification (chip ID) can also be programmed. The chip ID is in the memory circuit 222 cached. Through a read access on the memory circuit 222 the chip ID can be output at the data connection IO.

Also the memory circuit 221 can be used for test purposes. Through the memory circuit 221 makes it possible to variably set and test operating parameters of circuit components of the integrated semiconductor memory. In particular, can be in the memory circuit 221 Store data that adjusts the limits of operating parameters, for example, above or below the values specified in a specification. By the possibility on the memory circuit 221 Thus, it is possible to access operating parameters independently of those by programming the footer circuits 231 and 232 to change the default settings. This must be in the memory circuit 223 a date stored by the selection circuit 240 that in the memory circuit 221 saved date selects.

In a default setting can be in the memory circuit 223 a date should be stored so that the selection circuit 240 in the memory circuit 222 stored data for forwarding to the circuit component 300 selects. This generally corresponds to the setting in the intended operation of the semiconductor memory. For test and analysis purposes, write access to the memory circuit is possible 223 overwrite the default data value stored in it. Thus, a date in the memory circuit 223 be enrolled by the selection circuit 240 instead of in the memory circuit 222 stored data in the memory circuit 221 stored data of the circuit component 300 supplies. As a result, in particular in the test mode of the integrated semiconductor memory, different values of operating parameters, for example upper and lower limit levels of voltages generated by a controllable voltage generator, can be tested.

By a read access to the memory circuit 221 This can be done in the memory circuit 221 output stored data to the data port IO. It can be determined by whether in the memory circuit 221 in fact, the date has been saved with the correct data value.

In an alternative embodiment of the integrated semiconductor memory, a read access to the memory circuit 222 also be such that in the memory circuit 222 stored data first in the memory circuit 221 be enrolled. For this purpose, for example, between the memory circuits 221 and 222 a physical connection 500 consist.

In another embodiment, those in the memory circuit 222 stored data immediately after shooting the Fuseelemente the Fuseschaltungen 231 and 232 in the memory circuit 221 enrolled. By a read access to the memory circuit 221 can then be output to the data terminal IO those data previously from the memory circuit 222 in the memory circuit 221 were transferred mirrored.

4 shows a semiconductor memory module M, in which a control module 1000 is arranged on a module board MP. The control module 1000 is connected via a bus system BS with semiconductor memories HS. The semiconductor memories HS each contain a memory device 200 each comprising a plurality of memory circuits for storing data, and circuit components 300 , The circuit components 300 generate for their associated semiconductor memory operating parameters, such as voltage level, in dependence on the stored in the respective memory circuits of a semiconductor memory data.

The storage devices 200 The semiconductor memory include, for example, in 3 shown memory circuits 221 . 222 and 223 , About the data terminal IO of the semiconductor memory module can be controlled by the control circuit 100 Data in the storage device 200 the semiconductor memory write. This makes it possible to operate the arranged on a module board semiconductor memory with different values of operating parameters, as with those values of operating parameters that have been irreversibly programmed, for example, in the production by the shooting of Fuseelementen.

LIST OF REFERENCE NUMBERS

100

control circuit

200

storage device

211, 212, 213

decoder circuit

221, 222, 223

memory circuit

230

Irreversible programmable memory unit

231, 232

Fuseschaltung

240

select circuit

300

circuit component

400

bus system

410, 420, 430, 440

bus lines

500

connecting line

1000

control module

HS

Integrated semiconductor memory

SK

write command

LK

read command

AS

address signal

D

date

RS

read signal

WS

write signal

M

Semiconductor memory module

MP

module board

BS

bus structure

IO

data port

Claims (13)

Integrated semiconductor memory, comprising: - a connector (IO) for external input and output of a data, - at least a first register ( 221 ) for storing a datum, wherein an operating parameter of the integrated semiconductor memory can be set as a function of the stored datum, - in the case of a write access to the at least one first register ( 221 ) the data present at the port (IO) can be written into the at least one first register, - in the case of a read access to the at least one first register ( 221 ) the data stored in the at least one first register is externally output at the connection (IO), - at least one irreversibly programmable memory unit ( 231 . 232 ) a second register ( 222 ), the date in the second register ( 222 ) depending on a state of the storage unit ( 231 . 232 ) and depending on the one in the second register ( 222 ) an operating parameter of the integrated semiconductor memory is settable, - a selection circuit ( 240 ), the input side in the at least one first register ( 221 ) and that in the second register ( 222 ) stored date, - in which the selection circuit ( 240 ) a date of the in the at least one first register ( 221 ) and in the second register ( 222 ), in which the operating parameter of the integrated semiconductor memory depends on that of the selection circuit ( 240 ) and a third register ( 223 ) for storing a date which indicates a normal operation or a test and analysis operation, the selection circuit being dependent on that in the third register ( 223 ) selects the saved date. An integrated semiconductor memory according to claim 1, wherein said in the second register ( 222 ) stored data upon a read access to the second register at the port ( 10 ) is output to external. Integrated semiconductor memory according to Claim 1 or 2, in which, in the case of a write access to the third register ( 223 ) on the connection ( 10 ) can be written to the third register, - in the case of a read access to the third register ( 223 ) a date stored in the third register at the port ( 10 ) is output to external. Integrated semiconductor memory according to one of Claims 1 to 3, in which the signal from the selection circuit ( 240 ) selected date a controllable voltage generator ( 300 ), in which an operating parameter of the controllable voltage generator ( 300 ) depending on the selected date. Integrated semiconductor memory according to one of Claims 1 to 4, in which the irreversibly programmable memory unit is used as a fuse circuit ( 231 . 232 ) is trained. Integrated semiconductor memory according to one of claims 1 to 5, comprising: - a terminal (S100) for external application of a control command (LK, SK), - in which the date in dependence on the externally applied control command (LK, SK) in the first register ( 221 ) or from the first register ( 221 ), and - a circuit component ( 300 ) for generating a control signal (VPP, VBL, VBH) of the integrated semiconductor memory. Integrated semiconductor memory according to Claim 6, in which, when a first external control signal (SK) is applied, that at the terminal ( 10 ) date in the first register ( 221 ) is written, - in which when applying a second external control signal (LK) in the first register ( 221 ) stored date on the port ( 10 ) is output to external. Integrated semiconductor memory according to one of Claims 6 or 7, comprising: - a control circuit ( 100 ) for generating a write and read signal (RS, WS) for writing the date in the first register ( 221 ) and to read out in the first register ( 221 ) stored date, - a bus system ( 400 ) with several lines ( 410 . 420 . 430 . 440 ), - in which the read and write signals (RS, WS) via one of the lines ( 430 . 440 ) of the bus system are transmitted. Integrated semiconductor memory according to Claim 8, in which the first register ( 221 ) and the second register ( 222 ) via in each case an address (AS) from the control circuit ( 100 ) are addressable for respective access to the memory circuits, wherein the respective addresses are located in a common address space. An integrated semiconductor memory according to claim 9, comprising: - a plurality of decoder circuits ( 211 . 212 ), wherein in each case one of the decoder circuits is a register ( 221 . 222 ) is assigned to the respective decoding of an address (AS), - in which the decoder circuits in each case between one of the registers ( 221 . 222 ) and the bus system ( 400 ) are switched. A semiconductor memory module, comprising: - a connector ( 10 ) for the external input and output of a data, - a plurality of integrated semiconductor memories (HS) according to one of claims 1 to 10, and - a control module ( 1000 ) for controlling access to the semiconductor memories (HS). Method for operating an integrated semiconductor memory according to one of Claims 1 to 10, comprising: storing a first datum in the second register ( 222 ) depending on a state of the irreversibly programmable memory unit ( 231 . 232 ), - applying a second date and a third date to the at least one port (IO), - writing the second date into the first register ( 221 ) and writing the third date, which indicates a normal operation or a test and analysis operation, into the third register ( 223 ), - selecting the first and second registers ( 222 . 221 ) depending on the data stored in the third register ( 223 ) for setting an operating parameter of a circuit component ( 300 ) of the integrated semiconductor memory, - readout in the registers ( 222 . 221 . 223 ) and externally output the stored data to the at least one port ( 10 ). Method according to Claim 12, in which, depending on the selected datum, a voltage level of one of a controllable voltage generator ( 300 ) voltage is adjusted.

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