DE102006027826B4 - circuitry - Google Patents

Abstract

Circuitry that includes
A power inverter (INV) to which a pulse-width-modulated drive signal (PWM) can be fed on the input side and which at the output provides a blocking signal (LSIG) with low resistance and inverse to the pulse-width-modulated drive signal (PWM),
- A potential shifter (LSHIFT), the input side of the pulse width modulated drive signal (PWM) or a differential pulse signal (DSIG) can be fed, which is derived from the pulse width modulated drive signal (PWM), and which can be activated and deactivated depending on the lock signal (LSIG) and the provides a switching signal (SSIG) on the output side, which is related to an increased auxiliary potential (VEE), depending on the pulse-width-modulated drive signal (PWM) or differential pulse signal (DSIG) supplied on the input side, if the potential shifter (LSHIFT) is activated by the blocking signal (LSIG), wherein the potential shifter (LSHIFT) comprises a potential shifter resistor coupled at its first end to the boosted auxiliary potential (VEE) and coupled at its second end to a potential shifter switch (X8), the potential shifter switch (X8) being connected to the output of the power inverter (X8). INV) and the potential slide switch (X8) ...

Description

The invention relates to a circuit arrangement, which in particular forms a half-bridge driver for driving an upper switch and possibly a lower switch of a half-bridge arrangement.

Such half-bridge arrangements are used, for example, in DC-DC switching regulators in buck converter or boost converter arrangements or in motor controllers in order to convert electrical energy with high efficiency or to drive electric motors with high efficiency. These half-bridge arrangements can be designed for powers of a few watts up to several thousand watts. For driving the upper switch and the optionally provided lower switch of the half-bridge arrangement, drivers are required in each case, which enable a fast switching on and off of the switches. Furthermore, it must be ensured that the upper switch and the lower switch of the half-bridge arrangement are not switched on at the same time in order to avoid a short circuit and damage to the switches.

The DE 101 47 882 A1 discloses a half-bridge circuit having upper and lower switches, wherein the upper switch is turned on in response to a discharge current of the lower switch and the lower switch is turned on depending on the discharge current of the upper switch, such that the upper and / or lower switches only be turned on when the other switch is safely turned off.

The publication "An integrated level shifter for use in high frequency half-bridges" by DR H Carter and RA McMahon, New Developments in Power Semiconductor Devices, published in 1996 discloses an integrated power driver with a device for adjusting a voltage level for operating a half-bridge circuit in the megahertz range ,

From "Control Integrated Circuit Designers' Manual", International Rectifier, 1996, data sheet IR2111 half-bridge driver is known an integrated driver for a half-bridge circuit having an integrated device for adjusting a voltage level for driving an upper switch of a half-bridge circuit.

The object of the invention is to provide a circuit arrangement which is simple and reliable.

The object is solved by the features of the independent claims. Advantageous developments of the invention are characterized in the subclaims.

The invention is characterized by a circuit arrangement comprising a power inverter, a potential shifter and a power driver. The power inverter on the input side, a pulse width modulated drive signal can be fed. On the output side, the power inverter provides a blocking signal of low resistance and inverse to the pulse-width-modulated activation signal. The potential shifter on the input side, the pulse width modulated drive signal or a differential pulse signal can be fed. The differential pulse signal is derived from the pulse width modulated drive signal. The potential shifter can be activated and deactivated depending on the blocking signal. The potential shifter provides a switching signal from the output, which is related to an increased auxiliary potential. The potential shifter provides the switching signal, depending on the pulse width modulated drive signal or differential pulse signal supplied on the input side, when the potential shifter is activated by the blocking signal. The potential shifter includes a potential shifter resistor coupled at its first end to the boosted auxiliary potential and coupled at its second end to a potential shifter switch. The potential shifter switch is further coupled to the output of the power inverter. The potential slide switch can be switched on and off as a function of the pulse-width-modulated drive signal or the differential pulse signal. The switching signal is provided at a tap between the potential shifter resistor and the potential slide switch depending on the inhibit signal when the potential shifter is activated. The potential slide is activated when the potential slide switch is switched on. The output driver can be coupled with an upper switch on the output side to control the upper switch. The power driver turns on the upper switch depending on the switching signal. The power driver also turns off the upper switch when the potential shifter is disabled by the inhibit signal.

The advantage is that such a circuit arrangement is very simple and requires only a small number of components. Furthermore, a low-resistance structure of the circuit arrangement is possible. As a result, the circuit arrangement is very reliable and insensitive, in particular to contamination or to moisture, which can lead to undesirable parasitic capacitances between the components of the circuit arrangement. As a result, the circuit arrangement can be operated particularly safely. Furthermore, the switching signal can only be generated if the potential shifter is activated by the blocking signal. This will allow the top switch only be turned on when the lower switch is turned off. The control of the upper and lower switch are so reliably locked against each other. Furthermore, the circuit arrangement is also suitable for high clock frequencies of the pulse width modulated drive signal, for example for clock frequencies of more than one megahertz.

The circuit arrangement can be constructed by the low required number of components very simple and inexpensive discreet. The reliability and reliability of the circuit is not significantly affected. This has the advantage that by suitable choice of the components, in particular of the semiconductor components, a dielectric strength of the circuit arrangement can be specified very easily. Even with discrete structure of the circuit arrangement, the circuit arrangement requires only a small area. However, the circuit arrangement may also be formed as an integrated circuit.

The circuit arrangement is suitable for different power topologies, in particular for buck converter, boost converter or buck-boost converter. Furthermore, the circuit arrangement is particularly suitable for class D amplifier. Due to the high reliability and reliability, the circuit arrangement is also particularly well suited for use in a motor vehicle.

In an advantageous embodiment, the circuit arrangement comprises a one-way dead time element, which is coupled on the input side with the power inverter and the input side, the blocking signal is supplied. The one-way deadtime element is the output side coupled to a lower switch for driving the lower switch. The one-way deadtime timer turns on the lower switch in response to a first parameter value of the inhibit signal and turns off the lower switch in response to a second parameter value of the inhibit signal.

The first and / or the second parameter value of the blocking signal relate in particular to a rising or falling edge of the blocking signal or for example to an exceeding or falling below a predetermined threshold by the blocking signal. A dead time of the one-way dead time member is constituted by a period between a time of a change of the inhibit signal for turning on the lower switch and a time of actually turning on the lower switch. By suitable dimensioning of the dead time can be ensured that the upper switch is already turned off before the lower switch is turned on. As a result, a short circuit is reliably prevented, which otherwise caused by the simultaneously switched upper and lower switches and can lead to destruction of the upper and / or lower switch. The circuit arrangement thus forms a very reliable and reliable half-bridge driver, which is insensitive to dirt and moisture. Furthermore, it is ensured that the dead time is at least maintained. In particular, this is true regardless of a direction of current flow out of or into a half-bridge center node electrically formed between the upper and lower switches. As a result, the circuit arrangement is particularly suitable for use in a class D amplifier. Another advantage is that the blocking signal activates the activation of the upper and lower switches in such a way that they can not be switched on simultaneously. This locking is done selbstregelnd, that is, in the presence of unwanted, parasitic capacitances between the components of the circuit, for example by pollution or moisture, possibly increases the dead time, but the overlapping switching on the upper and lower switch is thereby particularly reliably prevented.

In this connection, it is advantageous if the one-way dead-time element comprises a delay transistor and a tuning resistor. The adjustment resistor is connected to a control terminal of the delay transistor. An input terminal of the delay transistor forms an input of the one-way dead time element. An output terminal of the delay transistor forms an output of the one-way dead time element. The dead time of the one-way dead time element is predetermined depending on a Millerkapazität of the delay transistor and a resistance value of the adjustment resistor.

The control terminal of the delay transistor is in particular formed by a gate terminal or a base terminal. The input terminal is in particular formed by a drain terminal or a collector terminal. The output terminal is in particular formed by a source terminal or an emitter terminal. The advantage of the circuit arrangement is that such a reliable delay of a change of the blocking signal for switching on the lower switch and the actual switching on of the lower switch is possible. Furthermore, the desired delay or dead time can be specified very simply by selecting the resistance value of the adjustment resistor. Another advantage is that only the switching on of the lower switch is delayed by the one-way deadtime, but switching off is essentially instantaneous. This will ensure that the bottom switch is turned off before the top switch is turned on. Furthermore, only a small number of components for the one-way deadtime required and the circuit arrangement is characterized very simple and inexpensive.

In this context, it is also advantageous if the control terminal of the delay transistor, a control signal can be supplied via the adjustment resistor for activating or deactivating the one-way dead time element depending on the control signal. This has the advantage that the one-way deadtime can be easily switched by the control signal. In a deactivated state, the lower switch remains switched off independently of a course of the blocking signal. In an activated state, the lower switch forms a synchronous rectifier, which can be switched off in a delayed manner and can be switched off substantially instantaneously, depending on the blocking signal. As a result of the control signal, a different operating mode of the circuit arrangement can be predetermined for different loads, which in each case enables a favorable efficiency of the circuit arrangement.

In a further advantageous embodiment of the circuit arrangement, an output of the potential shifter is coupled to an upper pre-driver switch. The upper pre-driver switch can thereby be supplied with the switching signal for switching on or off the upper pre-driver switch depending on the switching signal. The upper pre-drive switch is arranged electrically between the increased auxiliary potential and an input of the power driver. A lower pre-driver switch is electrically arranged between the input of the power driver and a reference potential. The lower pre-driver switch is coupled to the output of the power inverter. The lower pre-driver switch is thereby the blocking signal supplied to turn on or off the lower pre-driver switch depending on the inhibit signal. The advantage is that the circuit arrangement has a simple structure and only a few components are required. The upper switch can be quickly and reliably turned on by the upper pre-driver switch and the power driver depending on the switching signal. Furthermore, the upper switch can be switched off quickly and reliably by the lower pre-driver switch depending on the inhibit signal. This ensures that the top switch is safely turned off when the bottom switch is turned on.

In a further advantageous embodiment of the circuit arrangement, a compensation capacitor is provided in each case between a control connection and a control reference connection of the upper switch and / or of the lower switch. High-frequency oscillations, which may occur in particular due to the switching operations of the upper and / or the lower switch, may possibly reach the control terminal of the respectively switched-off switch via a miller capacitance of the upper and / or the lower switch and lead to an undesired, parasitic switching on of this switch , By providing the compensation capacitor, the high-frequency oscillations can be compensated or reduced so far that the undesired, parasitic switching is reliably prevented. As a result, the circuit arrangement is particularly reliable and reliable. The control terminal is in particular a gate terminal or a base terminal of the respective switch. The control reference terminal is in particular a source terminal or an emitter terminal of the respective switch.

Embodiments of the invention are explained below with reference to the schematic drawings. Show it:

1 a block diagram of a circuit arrangement,

2 a first embodiment of the circuit arrangement as a half-bridge driver in a buck converter arrangement,

3A a time characteristic of an output voltage and an output current in a first direction of the output current,

3B a time characteristic of the output voltage and the output current in a second direction of the output current,

4 a second embodiment of the circuit arrangement as a half-bridge driver in the buck converter arrangement,

5 a third embodiment of the circuit arrangement as a half-bridge driver in the buck converter arrangement,

6 a first variant of a fourth embodiment of the circuit arrangement as a half-bridge driver in the buck converter arrangement,

7 an application example of the first variant of the fourth embodiment,

8th a second variant of the fourth embodiment of the circuit arrangement as a half-bridge driver in the buck converter assembly and

9 A fifth embodiment of the circuit arrangement as a half-bridge driver in the buck converter.

Elements of the same construction or function are provided across the figures with the same reference numerals.

A circuit arrangement, which is designed in particular as a half-bridge driver for driving a half-bridge with an upper switch X2 and a lower switch X3, has a power inverter INV (FIG. 1 ). The upper switch X2 and the lower switch X3 are in a half-bridge center node acting as a node 10 is referred to, coupled together and are arranged electrically in series with each other between a supply potential VCC and a reference potential GND. The reference potential GND is preferably a ground potential. A voltage between the supply potential VCC and the reference potential GND is for example about twelve volts, but may also be larger or smaller.

The upper switch X2 and the lower switch X3 are preferably field-effect transistors, in particular MOS field-effect transistors. Preferably, the upper and lower switches X2, X3 have a low on-resistance even at a low gate-to-source voltage, for example about 26 milliohms at a gate-source voltage of about 4.5 volts. However, the upper switch X2 and the lower switch X3 can also be designed differently.

The power inverter INV input side, a pulse width modulated drive signal PWM can be fed. The pulse width modulated drive signal PWM is clocked, for example, with a clock frequency of 300 kilohertz, but may also be clocked at a higher or lower clock frequency. In particular, the clock frequency may be more than one megahertz. The power inverter INV inverts the pulse-width-modulated drive signal PWM and sets this output low-impedance at a node 18 ready as a blocking signal LSIG. Preferably, an output resistance of the power inverter INV is less than 100 ohms. It is particularly advantageous if the output resistance is less than ten ohms. For example, the output resistance is about 1 to 10 ohms. However, the output resistance may be lower or higher. The pulse width modulated drive signal PWM is related to the reference potential GND and has, for example, an amplitude of about five volts. However, the amplitude of the pulse width modulated drive signal PWM may also be greater or less than five volts.

The power inverter INV is electrically disposed between an auxiliary potential VDD and the reference potential and switches its output to an H level when the pulse width modulated drive signal PWM has an L level, and switches its output to an L level when the pulse width modulated drive signal PWM a H level has. For example, the auxiliary potential VDD is about five volts. The H level is then for example about five volts and the L level is about zero volts. However, the auxiliary potential VDD and the high level may also be coarser or smaller than five volts.

The output of the power inverter INV can be coupled to a control terminal of the lower switch K3. If the lower switch X3 is formed as a field effect transistor, then a threshold voltage of the lower switch X3 is to be selected so that it is smaller than the H level of the lock signal LSIG, to safely turn on the lower switch X3 in the presence of the H level of the lock signal To be able to guarantee LSIG. Electrically between the output of the power inverter INV and the control terminal of the lower switch X3 is preferably provided a one-way dead time TDEAD1 having a dead time TDEAD2 acting in a direction from the output of the power inverter INV to the control terminal of the lower switch X3. Further, the one-way dead time TDEAD1 includes a bypass diode X13 which bypasses the dead time TDEAD2 in a direction from the control terminal of the lower switch X3 to the output of the power inverter INV. As a result, when the blocking signal LSIG changes from the L level to the H level, the lower switch X3 can be switched on delayed by the dead time element TDEAD2 and switched off substantially instantaneously when the blocking signal LSIG changes from the H level to the L level. However, the one-way deadtime TDEAD1 can also be designed differently.

The circuit arrangement further comprises a potential shifter LSHIFT, the dependent on the pulse-width modulated drive signal PWM a related to an increased auxiliary potential VEE switching signal SSIG generated to turn on the upper switch X2. The potential shifter LSHIFT can be supplied with the pulse-width-modulated drive signal PWM or a differential pulse signal DSIG for this purpose. The differential pulse signal DSIG is related to one pulse of the pulse-width-modulated drive signal PWM and can be generated, for example, as a function of the pulse-width-modulated drive signal PWM or a clock signal of the pulse-width-modulated drive signal PWM. The potential shifter LSHIFT is further coupled to the output of the power inverter INV such that the potential shifter LSHIFT can be activated and deactivated depending on the blocking signal LSIG. For example, the potential shifter LSHIFT is activated when the inhibit signal LSIG has the L level, and deactivated when the inhibit signal LSIG has the H level. The switching signal SSIG is generated as a function of the pulse-width-modulated drive signal PWM or the differential pulse signal DSIG when the potential shifter LSHIFT is activated by the blocking signal LSIG. The switching signal SSIG is not generated when the potential shifter LSHIFT is deactivated.

The circuitry further includes a power driver DRIV that electrically connects between the boosted auxiliary potential VEE and the node 10 is arranged. The output driver DRIV is output coupled to a control terminal of the upper switch X2 for low-impedance driving of the upper switch X2. On the input side, the power driver DRIV is coupled to an upper and a lower pre-drive switch X1, X9, which are arranged in series with one another electrically between the increased auxiliary potential VEE and the reference potential GND. A control terminal of the upper pre-driver switch X1 is coupled to the output of the potential shifter LSHIFT. The control connection of the upper predriver switch X1 can thus be supplied with the switching signal SSIG.

Depending on the switching signal SSIG, the upper pre-driver switch X1 turns on, thereby raising the input of the power driver DRIV to a high potential towards the increased auxiliary potential VEE. The power driver DRIV is designed to switch on the upper switch X2 by raising a potential above the turn-on threshold of the upper switch X2 on the output side of the power driver DRIV. The upper pre-driver switch X1 is turned off by deactivating the potential shifter LSHIFT. However, the upper pre-driver switch X1 can be switched off, for example, even when the potential shifter LSHIFT is activated, if no differential pulse is supplied to the potential shifter LSHIFT.

A control terminal of the lower pre-driver switch X9 is coupled to the output of the power inverter INV. The blocking connection signal LSIG can therefore be fed to the control connection of the lower predriver switch X9. If the blocking signal LSIG has the H level, the lower pre-driver switch X9 switches on and supplies the input of the power driver DRIV with a low potential which corresponds approximately to the reference potential GND. The power driver DRIV is designed to switch off the upper switch X2 in that, on the output side of the power driver DRIV, the potential is lowered below the switch-on threshold of the upper switch X2. The lower pre-driver switch X9 is turned off when the inhibit signal LSIG has the L level.

By a boosting diode X10 and a boosting capacitor C2, a boosting circuit is formed, which may also be referred to as a boosting circuit. The boosting capacitor C2 is between a node 4 to which the increased auxiliary potential VEE is assigned, and the node 10 arranged. The boosting diode X10 is electrically arranged between the auxiliary potential VDD and the boosted auxiliary potential VEE. The boosting capacitor C2 is charged via the boosting diode X10 to a boosting voltage approximately equal to the auxiliary potential VDD minus a forward voltage of the boosting diode X10 when the upper switch X2 is turned off and the lower switch X3 is turned on. The knot 10 then has approximately the reference potential GND. The increased auxiliary potential VEE is formed from a current potential of the node 10 plus the boost voltage of the boost capacitor C2. If the upper switch X2 is turned on and the lower switch X3 is off, then the node points 10 about the supply potential VCC on. Accordingly, the increased auxiliary potential VEE is then approximately the supply potential VCC plus the boosting voltage of the boosting capacitor C2. By suitable dimensioning of the boosting capacitor C2, it can be ensured that the control terminal of the upper switch X2 has a sufficiently high voltage with respect to the node 10 can be supplied to keep the upper switch X2 turned on, as long as the switching signal SSIG is generated. Instead of the booster circuit, however, for example, a voltage source can be provided which provides the required increased auxiliary potential VEE with respect to the reference potential GND.

2 shows a first embodiment of the circuit arrangement as a half-bridge driver in a buck converter arrangement. The pulse width modulated drive signal PWM is generated by a signal source V2, which has a first source internal resistance R5. The signal source V2 is formed for example by a gate output. The source internal resistance R5 is, for example, approximately 400 ohms. The pulse-width-modulated drive signal PWM is decoupled via the power inverter INV, which is formed by a first and a second inverter transistor X11, X12. The power inverter INV has the task to provide the required high current pulses for driving the lower switch X3 and to logically invert the pulse width modulated drive signal PWM. The lower switch X3 forms a synchronous rectifier. The required current pulses for driving the lower switch X3, for example, about one ampere, but may also be larger or smaller. It is provided that the half-bridge center node, that is, the node 10 , which has low potential at about the reference potential GND when the pulse width modulated drive signal PWM has the L level, and the node 10 the high potential at about the Supply potential VCC when the pulse width modulated drive signal PWM has the H level. However, the circuit arrangement can also be designed so that there is a reverse assignment of the levels and potentials.

The auxiliary voltage VDD is provided by an auxiliary voltage source V4 having a second source internal resistance R8. A supply line of the auxiliary voltage source V4 to the circuit arrangement further has a first line inductance L2. To avoid electrical oscillations, a first blocking capacitor C5 is provided which has a parasitic resistance R10. The first blocking capacitor C5 is electrically arranged between the auxiliary potential VDD and the reference potential GND. The power inverter INV may be supplied with the auxiliary voltage VDD by another auxiliary power source V10, however, the power inverter INV may be supplied with the auxiliary voltage VDD by the auxiliary power source V4.

The supply potential VCC is provided by a supply voltage source V5. A supply line of the supply voltage source V5 to the upper switch X2 has a second line inductance L3 and a line resistance R9. In order to avoid electrical oscillations, a second blocking capacitor C5 is furthermore provided electrically between the supply potential VCC and the reference potential GND.

For operation as a buck converter, an inductance L1 is provided, which is electrically connected between the half-bridge center node, that is, the node 10 , and a load is arranged. The load is constituted by a load current source I1 and a load resistor R11 electrically connected in parallel with the load current source I1. The load is electrically arranged between the inductance L1 and the reference potential GND. Furthermore, a capacitor C3 is arranged electrically parallel to the load for operation as a step-down converter.

The potential shifter LSHIFT is formed by a voltage divider and by a potential slide switch X8. The voltage divider is electrically connected between the node 4 and the potential slide switch X8, and is formed by first and second voltage dividing resistors R1, R2. For example, a resistance value of the first voltage dividing resistor R1 is about 200 ohms, and a resistance value of the second voltage dividing resistor R2 is about 470 ohms, for example. However, the voltage divider can also be designed as a capacitive voltage divider. Furthermore, it is also possible to dispense with the first voltage divider resistor R1, in particular if it is ensured that a maximum between the control terminal of the predriver switch X1 and the node 4 prevailing voltage is so low that it can not lead to damage to the Vortreiberschalters X1. In particular, the first voltage divider resistor R1 can be dispensed with if the predriver switch is designed as a bipolar transistor. The second voltage divider resistor R2 may also be referred to as a potential shifter resistor.

The potential slide switch X8 is preferably formed by a field effect transistor whose source terminal is coupled to the output of the power inverter INV. The control terminal of the potential shifter switch X8 is coupled to the input of the power inverter INV. The control terminal of the potential shifter switch X8 is formed by a gate terminal of the potential shifter switch X8. A center tap of the voltage divider is coupled to the control terminal of the upper pre-driver switch X1 for supplying the switching signal SSIG. The switching signal SSIG drops as a switching voltage across the second voltage dividing resistor R2 when the potential shifter switch X8 is turned on and the inhibit signal is at the L level. The switching signal SSIG is thereby related to the increased auxiliary potential VEE.

The predriver switch X1 is preferably formed by a p-channel field effect transistor and the control terminal of the predriver switch X1 is formed by a gate terminal of the p-channel field effect transistor. Therefore, the upper pre-driver switch X1 turns on when the switching voltage across the second voltage dividing resistor R2 drops, that is, the switching signal SSIG is generated. Accordingly, the upper pre-driver switch X1 is turned off when the switching signal SSIG is not generated.

However, the switching signal SSIG can be generated only when the potential slide switch X8 is turned on, that is, the potential shifter LSHIFT is activated by the lock signal LSIG at the L level. As a result, a current flow through the voltage divider is possible, which results in the switching voltage, which leads to the switching on of the upper pre-driver switch X1.

Between the upper and lower pre-driver switches X1, X9, there is provided a limiting resistor R3 having, for example, a resistance of about 22 ohms. In the event of a momentarily overlapping switching on of the upper and lower pre-driver switches X1, X9, any short-circuit current through them is limited by the limiting resistor R3 to a harmless value. Of the Limiting resistor R3 is not mandatory, but increases the reliability and reliability of the circuit.

The power driver DRIV is formed by a first driver transistor Q1 and a second driver transistor Q2, which are formed as bipolar transistors. A respective base terminal of the first and second driver transistors Q1, Q2 is connected to a node 7 coupled, which is formed by a drain terminal of the lower Vortreibertransistors X9, which is coupled to the limiting resistor R3. A respective emitter terminal of the first and second driver transistors Q1, Q2 is coupled to the control terminal of the upper switch X2. A collector terminal of the first driver transistor Q1 is connected to the node 4 and a collector terminal of the second driver transistor Q2 is connected across a block diode X5 to the node 10 coupled. Block diode X5 prevents current flow from the node 10 towards the DRIV power driver.

The one-way dead-band TDEAD1 is constituted by a delay transistor X7 and a variable resistor R7. The delay transistor X7 is formed by another p-channel field effect transistor whose drain terminal forms an input terminal of the one-way dead time TDEAD1 and whose source terminal constitutes an output terminal of the one-way dead time TDEAD1. An unillustrated substrate diode of the delay transistor X7 forms the bypass diode X13. The adjustment resistor R7 is electrically arranged between a control terminal of the delay transistor X7 and the reference potential GND. The control terminal of the delay transistor X7 is formed by a gate terminal of the further p-channel field effect transistor.

By a so-called Miller capacitance, not shown, of the further p-channel field effect transistor, which is formed between the drain terminal and the gate terminal of the further p-channel field effect transistor, a negative feedback is effected, the output side to a tilting of an input side, rising edge of the blocking signal LSIG leads.

As a result, a gate-source voltage of the lower switch X3 increases slowed down, so that the threshold voltage of the lower switch X3 with respect to the rising edge of the blocking signal LSIG is delayed exceeded and the lower switch X3 thus turned on delayed. With respect to the rising edge of the inhibit signal LSIG, the turn-on of the lower switch X3 occurs only after a dead time has elapsed which is predetermined by a value of the Miller capacitance and a resistance value of the variable resistor R7. By selecting the resistance value of the adjustment resistor R7, the dead time can be specified very easily. For example, the resistance value of the adjustment resistor R7 is about 1.24 kiloohms, and the dead time is about 100 nanoseconds, for example. However, a charge on the gate terminal of the lower switch X3 can be rapidly discharged through the substrate diode of the delay transistor X7 when the latch signal LSIG has the L level. The switching off of the lower switch X3 thus takes place substantially instantaneously. The dead time to turn on the lower switch X3 must be such that it is greater than a time required for turning off the upper switch X2. The lower switch X3 only turns on when the upper switch is turned off.

Does the potential at the node increase? 10 quickly, for example, by turning on the upper switch X2, a current can flow to the gate terminal of the lower switch X3 via a Millerkapazität not shown of the lower switch X3. This current is derived in principle by the power inverter INV to the reference potential GND. However, due to the distance between the power inverter INV to the gate terminal of the lower switch X3 and the associated line inductance, the current may not be dissipated sufficiently fast to the reference potential GND. As a result, the gate-source voltage of the lower switch X3 may rise and possibly lead to parasitic switching on of the lower switch X3. However, this may cause the upper and lower switches X2, X3 to be turned on simultaneously. By providing a compensation capacitor C4 directly between the gate terminal and the source terminal of the lower switch X3, the voltage increase of the gate-source voltage of the lower switch X3 can be reduced so as to avoid the undesired switching-on of the lower switch X3.

Accordingly, in the presence of a negative output current IOUT in the node 10 Turn on the lower switch X3 also lead to an unwanted, parasitic turning on the upper switch X2. By providing a further, not shown compensation capacitor C4 between the gate terminal and the source terminal of the upper switch X2 can be avoided according to the unwanted switching on of the upper switch X2.

In the following, four different operating situations are explained. In a first operating situation, the turn-off operation of the lower switch X3 and the turn-on of the upper switch X2 is considered at a positive output current IOUT, that is at a current from the node 10 out through the inductor L1 and a non-latching buck converter operation.

The lower pre-driver switch X9 keeps the upper switch X2 turned off until the gate-source voltage of the lower switch X3 has fallen below the threshold voltage of the lower pre-driver switch X9 in accordance with the inhibit signal LSIG. This threshold voltage is for example about one volt. The lower switch X3 then already no longer allows a high current flow. By the L level of the blocking signal LSIG so on the one hand, the gate-source voltage of the lower switch X3 is reduced, so that the lower switch X3 turns off, and on the other hand, the activation of the upper switch X2 for switching on the upper switch X2 enabled. The blocking signal LSIG thus locks the control of the upper and lower switches X2, X3 against each other.

For the upper switch K2 and the lower switch X3, different transistor types with different parasitic capacitances can be used. Furthermore, compensation capacitors C4 can additionally be provided as external gate-source capacitors. These parasitic or additional capacitances and other parasitic capacitances, which are formed for example by contamination of the circuit arrangement or by moisture on the circuit arrangement, have only a small influence on the function of the circuit arrangement. This is achieved essentially by the low-resistance structure of the circuit arrangement and in particular by the low-resistance provision of the blocking signal LSIG at the output of the power inverter INV. As a result, a switch-off time of the lower switch X3 is largely independent of the capacitances of the circuit arrangement on the blocking signal LSIG recognizable, in particular independent of capacitances in a range of the lower Vortreiberschalters X9 and the potential slide switch X8. The detection of the switch-off of the lower switch X3 for the release of the upper switch X2 is therefore extremely reliable.

Shortly before the lower pre-driver switch X9 turns off, the potential slide switch X8 turns on. As a result, a current predetermined by the voltage divider flows through the first and second voltage divider resistors R1, R2. This current causes the voltage drop across the second voltage divider resistor R2. The signal related to the reference potential GND in the node 18 This way it will be on the node 4 converted switching signal SSIG implemented.

A voltage increase across the second voltage divider resistor R2 is optionally delayed by parallel capacitances, which are formed for example by parasitic capacitances of the upper pre-driver switch X1. By this delay, the lower pre-driver switch X9 is already off when the upper pre-driver switch X1 turns on, so that no cross-current flows through the upper and lower pre-driver switches X1, X9. However, due to the influence of component tolerances, such a crossflow may possibly occur for a short time, which is then limited by the limiting resistor R3.

The source impedance in the node 7 is further reduced via the downstream, non-inverting complement driver, which forms the DRIV power driver. The gate terminal of the upper switch X2 is quickly charged via the power driver DRIV, but delayed by the potential shifter LSHIFT with respect to the pulse width modulated drive signal PWM. However, the protection against the overlapping switching on of the upper and lower switches X2, X3 by the locking by the blocking signal LSIG also acts independently of a signal passage time of the potential shifter LSHIFT.

If, before switching on the upper switch X2, a positive output current IOUT flows through the inductance L1 in the direction of the capacitor C3, the lower switch X3 first switches off. The output current IOUT substantially continues to flow through a substrate diode of the lower switch X3, which forms a lower freewheeling diode D3. An output voltage UOUT between the potential at the node 10 and the reference potential GND thereby jumps to a forward voltage of the lower freewheeling diode D3, which is for example about one volt. The upper switch X2 then turns on hard, that is, the potential at the node 10 quickly rises to about the supply potential VCC.

In a second operating situation, the turn-off operation of the lower switch X3 and the turn-on operation of the upper switch X2 at a negative output current IOUT from the inductance L1 into the node 10 looked into it. This operating situation occurs, for example, in a lulling buck converter operation or in a Class D amplifier. In this operating situation, too, the protection explained above acts against the overlapping switching on of the upper and lower switches X2, X3.

However, the output voltage UOUT does not increase until the upper switch X2 is switched on, but already during the switch-off of the lower switch X3. The reason for this is that the negative output current IOUT causes charging of parasitic and elementary capacitances that are connected to the node 10 are connected. The output voltage UOUT therefore increases linearly. After charging the capacitances, the negative output current IOUT substantially flows through a substrate diode of the upper switch X2, which forms an upper freewheeling diode D2 when the upper switch X2 is still off. Due to the voltage drop across the upper freewheeling diode D2 corresponds to the potential at the node 10 about the supply potential VCC plus the forward voltage of the upper freewheeling diode D2, which is about one volt.

The signal delay of the potential shifter LSHIFT is preferably dimensioned by suitably selecting the resistance values of the first and second voltage divider resistors R1, R2 such that the upper switch X2 does not switch on until the negative output current IOUT has flowed through the upper freewheeling diode D2 for a period of time sufficient, the capacity at the node 10 through the negative output current IOUT so far that the potential at the node 10 close to the supply potential VCC, for example, down to about one to two volts. The upper switch X2 can then be turned on particularly low loss. This is also referred to as soft-switching or soft-switching.

Parasitic capacities, for example due to contamination or moisture, cause an additional signal delay in the potential shifter LSHIFT and thus a longer conduction phase of the upper freewheeling diode D2. Although this has a reduction in the overall efficiency of the buck converter result. However, the circuit arrangement is thus in a safe operating point. The overlapping switching on of the upper and lower switches X2, X3 is thus particularly reliably prevented.

Even if the delay of the potential shifter LSHIFT were very small, the overlapping switching on of the upper and lower switches X2, X3 by the blocking signal LSIG would be reliably prevented. With very little delay of the potential shifter LSHIFT, the soft switching on of the upper switch X2 may be omitted.

In a third operating situation, the turn-off operation of the upper switch X2 and the turn-on operation of the lower switch X3 are considered at the positive output current IOUT in the non-latching buck converter operation. Even in this operating situation is ensured by the blocking signal LSIG that the upper and lower switches X2, X3 are not turned on simultaneously.

The rising edge of the inhibit signal LSIG causes the lower pre-driver switch X9 to rapidly turn on when its threshold voltage is exceeded. The gate terminal of the lower switch X2 is discharged very quickly via the power driver DRIV and via the block diode X5. Due to the positive output current IOUT, the output voltage UOUT decreases rapidly with the switching off of the upper switch X2. The output current IOUT then continues to flow essentially via the lower freewheeling diode D3. The lower switch X3 is still off, since the increase of the gate-source voltage of the lower switch X3 is slowed down by the delay transistor X7 and the adjustment resistor R7. The compensation capacitor C4 and the gate-source capacitance of the lower switch X3 are therefore charged slowed and the lower switch X2 is thereby delayed. Due to the voltage drop across the lower freewheeling diode D3, the output voltage UOUT is about -1 volts. Due to the low output voltage UOUT, the lower switch X3 turns on soft, raising the output voltage UOUT to about zero volts. Switching on the lower switch X3 is therefore lossy.

For reliable operation of the circuit arrangement, the circuit arrangement must be formed by suitably selecting the respective threshold voltage so that the lower predriver switch X9 is already switched on before the gate-source voltage of the lower switch X3 reaches its threshold voltage. For this purpose, the threshold voltage of Vortreiberschalters X9 is to be selected lower than the threshold voltage of the lower switch X3.

In a fourth operating situation, the turn-off operation of the upper switch X2 and the turn-on operation of the lower switch X3 are considered at the negative output current IOUT. During the turn-off operation of the upper switch X2, the negative output current IOUT flows into the node 10 into it, the potential remains at the node 10 during turn-off of the upper switch X2 approximately at the supply potential VCC plus the forward voltage of the upper freewheeling diode D2. The upper switch X2 therefore turns off soft and low loss. The switching on of the lower switch X3 is delayed by the delay transistor X7 and the adjusting resistor R7. The lower switch X3 therefore turns on only hard after the upper switch X2 is turned off. The hard turning on of the lower switch X3 drops the potential at the node 10 approximately to the reference potential GND.

An advantage of the circuit arrangement is that in all four operating situations, that is to say independent of the direction of the output current IOUT, the locking of the activation of the upper and lower switches X2, X3 by the blocking signal LSIG is effective.

3A shows a time course of the output voltage UOUT at the negative output current IOUT. At a first time tA, the lower switch X3 turns off, thereby the output voltage UOUT rises rapidly from about zero volts to about the supply potential VCC plus about one volt, the upper freewheeling diode D3 conducts. At the second time tB, the upper switch X2 switches on softly, the output voltage UOUT thereby drops by about one volt to approximately the supply potential VCC. At a third time tC, the upper switch X2 switches off, the upper freewheeling diode D2 conducts and the output voltage UOUT rises again to approximately the supply potential VCC plus approximately one volt. After the dead time expires, the lower switch X3 turns on hard at a fourth time tD. The output voltage UOUT falls quickly to about zero volts.

3B shows correspondingly a time course of the output voltage UOUT at the positive output current IOUT. At a fifth time tE, the upper switch X2 switches off and the output voltage UOUT drops rapidly to about -1 volt, the lower freewheeling diode D3 conducts. After the dead time has elapsed, the lower switch X3 switches on softly at a sixth instant tF and the output voltage UOUT rises to approximately zero volts. At a seventh point in time tG, the lower switch X3 switches off, the lower freewheeling diode D3 conducts and the output voltage drops to about -1 volt. At an eighth time tH, the upper switch X2 turns on hard. As a result, the output voltage UOUT rises rapidly to approximately the supply potential VCC.

4 shows a second embodiment of the circuit arrangement, which differs from the first embodiment in that the delay transistor X7 and the adjusting resistor R7 are replaced by a charging resistor R12 and the separately formed bypass diode X13. The charging resistor R12 causes slower charging of the gate-source capacitance of the lower switch X3 and the compensation capacitor C4 when the rising edge of the latch signal LSIG occurs. As a result, the lower switch X3 is switched on with a corresponding delay. By suitable choice of the resistance value, for example about ten ohms, the desired dead time can be specified. The circuit arrangement is so very simple and inexpensive to produce.

5 shows a third embodiment of the circuit arrangement, which differs from the first embodiment in that the one-way deadtime TDEAD1 and the compensation capacitor C4 are not required. The lower switch X3 is replaced by a freewheeling diode D1, that is, the synchronous rectifier function of the lower switch X3 is eliminated. This circuit is particularly simple and inexpensive to produce.

6 shows a first variant of a fourth embodiment of the circuit arrangement, which differs from the first embodiment in that the control terminal of the potential shifter switch X8 is not coupled to the input of the power inverter INV, the control terminal of the potential shifter switch X8 so the pulse width modulated drive signal PWM is not supplied, but the control terminal of the potential shifter switch X8 is coupled to a differential pulse source V11 through which the differential pulse signal DSIG is supplied to the control terminal of the potential shifter switch X8. With each differential pulse, the gate-source capacitance of the upper switch X2 is charged when the inhibit signal LSIG simultaneously has the L level. Due to the pulsed activation of the potential slide switch X8, a current flows through the voltage divider of the potential shifter LSHIFT only for a very short period of time of the differential pulse. As a result, only small losses occur in the potential shifter LSHIFT and an energy requirement of the circuit arrangement is thereby reduced. Furthermore, the circuit arrangement thereby has a higher efficiency. This allows in particular a low-loss operation at high supply potential VCC.

7 shows an application example of the first variant of the fourth embodiment of the circuit arrangement. Two or even more than two of the circuit arrangements, for example in each case in a step-down converter arrangement for respectively different voltages, are operated synchronously with one another. The buck converter assemblies are each supplied to the common differential pulse signal DSIG. Furthermore, the respective step-down converter arrangement is supplied with the respective pulse width modulated drive signal PWM, for example a first pulse width modulated drive signal PWM1 for generating a voltage of five volts or a second pulse width modulated drive signal PWM2 for generating a voltage of 3.3 volts. By synchronously operating the buck converter assemblies, unwanted interference between them can be avoided.

8th shows a second variant of the fourth embodiment of the circuit arrangement in which the differential pulse signal DSIG is generated by a differentiating circuit of the pulse width modulated drive signal PWM. The differentiating circuit comprises a differentiating capacitor C7 and a differentiating resistor R13. The differentiating capacitor C7 is supplied with the pulse-width-modulated drive signal PWM at a first terminal. The second terminal of the differentiating capacitor C7 is coupled to the reference potential GND via the differentiating resistor R13. Furthermore, a first inverter X14 and a second inverter X15 are provided electrically in series one behind the other, via which the second terminal of the differentiating capacitor C7 is coupled to the control terminal of the potential shifter switch X8. The first and second inverters X14, X15 ensure that the differential pulse signal DSIG is supplied to the control terminal of the potential shifter switch X8 in a low-resistance manner in order to avoid signal distortions.

9 shows a fifth embodiment of the circuit arrangement, which differs from the first embodiment in that the control terminal of the delay transistor X7 via the adjustment resistor R7, a control signal CSIG is supplied. The control signal CSIG is generated, for example, by a control signal source V12 which provides either an L level or an H level depending on a desired switching state of the delay transistor X7. In the presence of the L level, the delay transistor X7 is turned on and thereby activated. The circuit arrangement then corresponds in its function to the first embodiment of the circuit arrangement. However, if the H level is present, then the delay transistor X7 is turned off and thereby deactivated. The lower switch X3 then remains off regardless of a course of the blocking signal LSIG. The circuit arrangement then corresponds in its function to the third embodiment, that is, only the substrate diode of the lower switch X3 or the lower free-wheeling diode D3 is used. The synchronous rectifier function of the lower switch X3 is eliminated. Depending on the control signal CSIG, the synchronous rectifier function of the lower switch X3 can thus be activated or deactivated simply and dynamically during the operation of the circuit arrangement.

The use of the synchronous rectifier function of the lower switch X3 is particularly advantageous when the output current IOUT is large in magnitude, for example greater than about one ampere. However, with absolute low output current IOUT, for example less than about one ampere, operation without the synchronous rectifier function of the lower switch X3 is advantageous. By appropriately activating or deactivating the synchronous rectifier function of the lower switch X3 by the control signal CSIG, the circuit arrangement can each be operated with a favorable efficiency.

The insensitivity of the circuit to parasitic influences such as moisture and other creepage distances has been demonstrated experimentally in a water bath with distilled water. The circuit arrangement showed no loss of function even with the high parasitic capacitances occurring during this process. In particular, overlapping switching on of the upper and lower switches X2, X3 did not occur. It was only a high load of the power inverter INV, but this can be countered by suitable dimensioning of the power inverter INV. Due to this particular reliability and reliability, the circuit arrangement is particularly suitable for use in motor vehicles. For example, the circuitry may be constructed of discrete components on an area of only about one square centimeter. However, the circuit arrangement can also be designed as an integrated circuit.

The circuit arrangement is described by way of example as a half-bridge driver in a buck converter arrangement. However, the circuitry is also useful in a boost converter or boost converter arrangement or in a class D amplifier. Furthermore, the circuit arrangement can be used as a half-bridge driver for other applications.

Claims (6)

Circuit arrangement which comprises - a power inverter (INV) to which a pulse width modulated drive signal (PWM) can be supplied and which provides a blocking signal (LSIG) with low resistance and inverse to the pulse width modulated drive signal (PWM) on the output side, - a potential shifter (LSHIFT) on the input side the pulse width modulated drive signal (PWM) or a differential pulse signal (DSIG) can be supplied, which is derived from the pulse width modulated drive signal (PWM) and which can be activated and deactivated as a function of the blocking signal (LSIG) and which provides a switching signal (SSIG) on the output side is related to an increased auxiliary potential (VEE), depending on the input side supplied pulse width modulated drive signal (PWM) or differential pulse signal (DSIG), when the potential shifter (LSHIFT) by the inhibit signal (LSIG) is activated, wherein the potential shifter (LSHIFT) comprises a Potentialschieberwiderstand . coupled to its first end with the boosted auxiliary potential (VEE) and its second end coupled to a potential shifter switch (X8), the potential shifter switch (X8) being coupled to the output of the power inverter (INV) and the potential shifter switch (X8) depending on the pulse width modulated drive signal (PWM) or the differential pulse signal (DSIG) can be switched on and off, wherein the switching signal (SSIG) at a tap between the potential shifter resistor and the Potential slide switch (X8) can be provided depending on the blocking signal (LSIG), when the potential shifter (LSHIFT) is activated, the potential shifter (LSHIFT) is activated when the potential shifter switch (X8) is switched on, - a power driver (DRIV), the output side with an upper switch (X2) can be coupled to drive the upper switch (X2) and depending on the switching signal (SSIG) the upper switch (X2) turns on and off the upper switch (X2), when the potential shifter (LSHIFT) by the blocking signal (LSIG) is deactivated, Circuit arrangement according to Claim 1, which comprises a one-way dead time element (TDEAD1) which is coupled on the input side to the power inverter (INV) and to which the blocking signal (LSIG) can be supplied on the input side and whose output side can be coupled to a lower switch (X3) for driving of the lower switch (X3) and which, depending on a first parameter value of the blocking signal (LSIG), switches on the lower switch (X3) in a delayed manner and switches off the lower switch (X3) as a function of a second parameter value of the blocking signal (LSIG). Circuit arrangement according to Claim 2, in which The one-way dead-time element (TDEAD1) comprises a delay transistor (X7) and an adjustment resistor (R7), The adjustment resistor (R7) is connected to a control terminal of the delay transistor (X7), An input terminal of the delay transistor (X7) forms an input of the one-way dead time element (TDEAD1), - An output terminal of the delay transistor (X7) forms an output of the one-way deadtime (TDEAD1) and - A dead time of the one-way dead time element (TDEAD1) is given depending on a Millerkapazität of the delay transistor (X7) and the adjustment resistor (R7). Circuit arrangement according to Claim 3, in which a control signal (CSIG) can be fed via the setting resistor (R7) to the control terminal of the delay transistor (X7) for activating or deactivating the one-way dead time element (TDEAD1) in dependence on the control signal (CSIG). Circuit arrangement according to one of the preceding claims, in which An output of the potential shifter (LSHIFT) is coupled to an upper pre-driver switch (X1), The upper pre-driver switch (X1) can be supplied with the switching signal (SSIG) for switching on or off the upper pre-driver switch (X1) as a function of the switching signal (SSIG), The upper pre-driver switch (X1) is arranged electrically between the increased auxiliary potential (VEE) and an input of the power driver (DRIV), A lower pre-driver switch (X9) is electrically arranged between the input of the power driver (DRIV) and a reference potential (GND), and The lower pre-driver switch (X9) is coupled to the output of the power inverter (INV) and the lower pre-driver switch (X9) is thereby supplied with the inhibit signal (LSIG) to turn on or off the lower pre-driver switch (X9) in response to the inhibit signal (LSIG). Circuit arrangement according to one of the preceding claims, wherein between a control terminal and a control reference terminal of the upper switch (X2) and / or the lower switch (X3) in each case a compensation capacitor (C4) is provided.

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