DE102006015131B4 - Semiconductor structure with sinker contact and method for its production - Google Patents

Abstract

The invention relates to a semiconductor structure comprising a semiconductor substrate, a heavily doped buried layer formed in at least portions of the semiconductor substrate, a monocrystalline semiconductor layer ("epilayer") disposed on the semiconductor substrate and the buried layer, and a surface of the semiconductor substrate Semiconductor layer to the buried layer reaching low-resistance contact in the form of a "sinker contact", wherein a sinker trench isolation substantially framing the sinker contact is arranged, which electrically isolates the sinker contact of adjacent areas of the epilayer.

Description

The The present invention is in the field of semiconductor devices and more particularly relates to a semiconductor structure having a buried layer contacting sinker contact, as well as a method for their production.

modern Integrated circuits contain a variety of electrically isolated Circuit elements. In the course of a progressive miniaturization These circuit elements are getting smaller, so that too electrical insulation between the circuit elements in a corresponding manner have to get smaller.

In today's common Smart Power Technology (SPT) products, which the functionality CMOS, bipolar and DMOS devices different circuit elements on a semiconductor chip, for example electrically insulated from each other by diffusion insulation. Around To produce such a diffusion insulation, for example, by a masked implantation suitable dopants in the semiconductor are introduced, which is electrically activated by subsequent annealing become.

Around to act as insulation, the generated doping region of the conductivity type of the substrate or the monocrystalline epi layer applied thereto is different be. For example, a p-doped doping region becomes one n-doped substrate or epi layer generated. Also known is the formation of a trench isolation, in which from the epi layer to the semiconductor substrate reaching deep trenches be etched ("deep trenches"), the following with an insulating material (for example silicon dioxide) filled become. Such trench isolations usually frame the semiconductor devices or lateral areas in which houses a plurality of such semiconductor devices are to electrically isolate them from each other.

Some integrated circuits, such as bipolar and DMOS transistors, which are also used in SPT products used, use a highly doped buried layer ("buried layer") as a collector or drainage area. To make a low-resistance contact to the buried Layer is, for example, one to buried Layer-reaching diffusion region ("sinker contact") generated. The production of such Sinker contact can be achieved by implantation of suitable dopants and annealing, the annealing serving to provide the dopants to drive into the epoch layer until this buried layer reach, and to activate them electrically. The dopants are chosen here that the sinker contact a doping of the same conductivity type as the buried layer has, while the doping is of the conductivity type the epi-layer is different in order to achieve that sinker contact across from the epi layer is electrically isolated.

adversely when producing a diffusion insulation, such as a Sinker contact for contacting a buried layer is in particular the fact that during tempering always a lateral Outdiffusion of the dopants takes place, so that the space requirement of a such diffusion insulation is comparatively high. In addition, must the diffusion insulation to achieve a sufficient dielectric strength the formation of a space charge zone with a sufficient lateral Allow dimension, so that there is enough space around the diffusion area must be kept. In this respect, require conventional diffusion insulation comparatively much space, which is disadvantageous in terms of a Miniaturization of the semiconductor devices is.

In detail is from the US 5,146,304 a bipolar transistor with a buried collector layer and an epitaxial layer with a base and an emitter and a sinker contact known. This sinker contact is surrounded on all sides by dielectric isolation regions and separated from the base. These dielectric isolation regions have the same depth to the base and in the opposite direction as to beyond the buried layer, but the isolation regions are shown slightly wider in the opposite direction than at the base.

Furthermore, the treated US 5,187,109 the production of lateral bipolar transistors and shows on a substrate a buried layer and thereon an epitaxial layer and a contact made by implantation and annealing, which is isolated by internal trenches to the buried layer and by external trenches to the substrate.

It Object of the invention, a semiconductor structure and a method specify for their production, by which a sinker contact for contacting a buried layer with a lower one lateral space requirement can be realized so far, without the Forfeit the dielectric strength of the diffusion insulation.

These The object is according to the proposal of the invention by a semiconductor structure of claim 1 or a process for their preparation with the features of claim 4 solved. Advantageous embodiments The invention are characterized by the features of claims 2 and 3 indicated.

According to the invention is a Semiconductor structure shown, which in a conventional manner, a semiconductor substrate and a highly doped buried layer, at least in part of the semiconductor substrate is formed. The highly doped buried layer can be used as a collector or drain of a bipolar or DMOS transistor serve. On the semiconductor substrate and the buried layer is, as usual, a monocrystalline semiconductor layer (epi-layer) is arranged, the usually is deposited by molecular beam epitaxy. Furthermore, the Semiconductor structure with one from one surface of the epi layer to the buried layer reaching low-resistance contact in the form of a Diffusion area (sinker contact) provided to an electrical To create connection to the buried layer.

The inventive semiconductor structure records Now, in a significant way, that the sinker contact essentially surrounding trench isolation ("sinker trench isolation"), which is the sinker contact isolated from adjacent (doped) areas of the epilayer demarcates. To an electrical insulation of the sinker contact of the To reach adjacent areas of the epistoleate, the trenches are the trench isolation with an insulating material, such as silica, filled. however Any other suitable insulating material may also be used.

By the sinker trench isolation can advantageously be a spatial Limitation of the sinker contact can be achieved because in the production the sinker contact the dopants when driving into the epilayer only up to the sinker trench isolation can diffuse. Through the sinker trench isolation Thus, a sinker contact with desired dimensions can be realized become. In addition, due to the insulating properties of the sinker trench insulation the sinker contact only its function as a low-impedance connection meet the buried layer. In contrast to a diffusion insulation is thus unnecessary in terms a sufficient one Dielectric strength sufficient space to form a space charge zone in the vicinity of the sinker contact so that the space requirement of the sinker contact compared to a diffusion insulation is reduced.

By the chosen one Expression "essentially" with respect to Surrounding the sinker contact by the sinker trench isolation is to be indicated that it is not necessary that the sinker trench isolation the Sinker contact on its whole, the epi layer crossing (vertical) dimension surrounds. Rather, it is enough it when the sinker trench isolation the sinker contact with respect to its vertical dimension so far surrounds that outdiffusion of the dopants from the sinker contact prevented in the surrounding doped regions of the epilayer so far is that the electrical properties of the surrounding doped Areas or the dielectric strength of the insulation is not essential impaired become. For example, the numerical value of an electrical Property by the outdiffusion of the dopants by not more than 20%, preferably not more than 10% change. A certain small Outdiffusion of the dopants from the sinker contact into the surrounding doped regions of the epilayer is thus harmless.

In Advantageously, however, the sinker trench isolation surrounding the sinker contact is sufficient at least up to the height the buried layer, to an outdiffusion of the dopants of the sinker contact in the surrounding areas of the epilayer or a reduction the dielectric strength throughout to avoid. The sinker trench isolation can be buried in the buried Dip layer, but only so far that electrical properties the buried layer are not significantly affected. Part of the sinker trench isolation can also sever the buried layer, with the sinker trench isolation at the desired Contact point not complete may be severed.

has the semiconductor structure a deep trench isolation to the electric Isolation of active structures, such as bipolar or DMOS transistors, or of lateral Areas containing such active structures, at which the trenches from the surface the epi layer to at least extend to the semiconductor substrate, so it is extremely beneficial if part of the deep trench isolation forms part of the sinker contact framing sinker trench isolation shaped. A complete sheath However, the sinker contact through the deep trench structure is not makes sense, because the buried layer otherwise at the desired Contact point would be severed. For example, the deep trench structure, the sinker contact with respect to three spatial directions surrounded while in terms of a fourth spatial direction only one to the buried layer reaching isolation trench is provided. For the sake of one simple production, the deep trench isolation has a greater width on as the only reaching to the buried layer isolation trench the sinker trench isolation.

• a) Bereitstellen eines Halbleiter-Schichtstapels, der ein Halbleitersubstrat, eine hochdotierte vergrabene Schicht, die wenigstens in Teilen des Halbleitersubstrats ausgebildet ist, und eine einkristalline Halbleiterschicht, die auf dem Halbleitersubstrat und der vergrabenen Schicht angeordnet ist, umfasst;
• b) Herstellen einer laterale Bereiche des Halbleitersubstrats voneinander elektrisch isolierenden, bis in das Halbleitersubstrat reichenden Tiefgrabenisolierung;
• c) Herstellen einer Grabenisolierung ("Sinker-Kontakt-Fenster"), welche ein von der Oberfläche der Halbleiterschicht im Wesentlichen (oder mindestens) bis zur vergrabenen Schicht reichendes Gebiet umrahmt, das als Sinker-Kontakt zur vergrabenen Schicht vorgesehen ist;
• d) Herstellen eines Diffusionsgebiets (Sinker-Kontakt) innerhalb des Sinker-Kontakt-Fensters, was in herkömmlicher Weise beispielsweise durch maskierte Implantation von geeigneten Dotierstoffen und anschließendes Tempern erfolgen kann.

Furthermore, according to the invention, a method for producing a semiconductor structure having a buried contact contacted by a sinker contact is shown, which comprises the following steps:

• a) providing a semiconductor layer stack, comprising a semiconductor substrate, a heavily doped buried layer, at least in parts of Semiconductor substrate is formed, and a monocrystalline semiconductor layer, which is disposed on the semiconductor substrate and the buried layer comprises;
• b) producing a lateral regions of the semiconductor substrate from each other electrically insulating deep trench isolation extending into the semiconductor substrate;
• c) forming a trench isolation ("sinker contact window") framing an area substantially (or at least) to the buried layer, which is provided as sinker contact with the buried layer, from the surface of the semiconductor layer;
• d) forming a sinker contact within the sinker contact window, which can be done in a conventional manner, for example by masked implantation of suitable dopants and subsequent annealing.

The Tiefgrabenisolierung and the sinker contact window (or their ditches) are in a same etching step produced. The depth of the sinker contact window or at least a part of it leaves in an advantageous way about specify the trench width.

The Invention will now be explained in more detail with reference to an embodiment, wherein Reference to the attached Drawings is taken. Show it:

1A - 1B a supervision ( 1A ) and a side view ( 1B ) of an embodiment of a semiconductor structure according to the invention;

2 a diagram illustrating the relationship between trench depth T and trench width W during the etching of an isolation trench.

Same or equivalent elements are in the figures with the same reference numerals designated.

First, reference to the 1A and 1B taken in which a supervisor ( 1A ) and a side view ( 1B ) of an embodiment of a semiconductor structure according to the invention are shown. Accordingly, a semiconductor structure according to the invention comprises a semiconductor substrate not shown in detail 1 , For example, n-doped silicon, which with a, for example p-highly doped, buried layer 2 is provided. On the semiconductor substrate 1 and the buried layer 2 is a monocrystalline semiconductor layer (epilayer) 6 arranged, which is not shown in detail in the figures. In the episode 6 is one of the surface 7 to the buried layer 2 reaching low-ohmic sinker contact 3 shaped in the form of a (for example p-doped) diffusion region. The buried layer 2 serves as a collector or drain region of a bipolar or DMOS transistor.

Furthermore, one of the surface 7 the epoch 6 to the semiconductor substrate 1 reaching deep trench isolation 4 arranged, which serves to a buried layer 2 use semiconductor device such as a bipolar or DMOS transistor, or a lateral region in which a plurality of semiconductor devices is housed to electrically isolate. The deep trench isolation 4 comprises a trench arranged in the yz plane, as well as two trenches arranged in the xz plane, all of which are the buried layer 2 cut.

The sinker contact 3 becomes on three sides of the trenches of the deep trench isolation 4 limited. On a fourth page is another isolation trench 5 provided, which of the surface 7 the epoch 6 to the buried layer 2 is enough without cutting through them. The isolation trench 5 is in contact with the two trenches of the deep trench isolation 4 and forms with them an insulation frame (sinker contact window) around the sinker contact 3 ,

Using the sinker contact 3 surrounding insulating frame, the sinker contact in a simple manner by introducing dopants in the epilayer 6 For example, by means of masked implantation, and then driving the dopants into the epilayer and their electrical activation by means of annealing (as in 1B schematically represented by the arrows), without having to accept an unwanted outdiffusion of the dopants and concomitant lateral broadening of the sinker contact in purchasing. The introduced dopants can only diffuse to the isolation frame.

In the embodiment shown, the sinker contact 3 in a space-saving way at the very edge of an already existing deep trench isolation 4 been placed. However, the sinker contact window could also be on its own, away from the deep trench isolation 4 to be placed at any other place.

How out 2 , A diagram illustrating the relationship between trench depth T and trench width W during the etching of an isolation trench, can be achieved by selecting a suitable width of the trench a desired depth can be achieved. In the in the 1A and 1B In the embodiment shown, the sinker contact window comprises three trenches with a width W ₁ of approximately 2 μm, which forms part of the trench isolation 4 are, as well as a ditch 5 with a width W ₂ of approx. 0.7 μm. While the deeper trenches of deep trench isolation the buried layer 2 cut through, the narrower isolation trench only extends to the buried layer without severing it. By a suitable choice of the trench width of the respective trenches, the sinker contact window is thus produced in a single etching step together with the deep trench insulation in a simple manner. The trenches are then filled with an insulating material, such as silicon dioxide.

In the semiconductor structure according to the invention can advantageously a conventional sinker contact assignment be used. A lateral outdiffusion of the dopants during the Driving and electrical activation is through the sinker contact window prevented. Advantageously, only trenches for Used for isolation purposes.

1

Semiconductor substrate

2

buried layer

3

Sinker Contact

4

Deep grave insulation

5

isolation trench

6

epilayer

7

surface

T

grave depth

W

grave width

Claims (4)

Semiconductor structure comprising a semiconductor substrate ( 1 ), a highly doped buried layer ( 2 ), which at least in parts of the semiconductor substrate ( 1 ) is formed, a monocrystalline semiconductor layer ( 6 ) on the semiconductor substrate ( 1 ) and the buried layer ( 2 ) is arranged, one from a surface of the semiconductor layer ( 6 ) to the buried layer reaching low-resistance sinker contact ( 3 ) in the form of a diffusion region and the sinker contact ( 3 ) substantially framing sinker trench isolation ( 4 . 5 ) which the sinker contact ( 3 ) of adjacent regions of the semiconductor layer ( 6 ), characterized in that a deep trench isolation ( 4 ) has a larger trench width than at least one trench of the sinker contact ( 3 ) surrounding sinker trench isolation ( 5 ). Semiconductor structure according to claim 1, characterized in that the sinker contact ( 3 ) bordering sinker trench isolation ( 5 ) at least until the buried layer ( 2 ) enough. Semiconductor structure according to claim 1 or 2, characterized in that the sinker trench isolation ( 5 ) partially electrically insulated from the lateral areas of the semiconductor structure, into the semiconductor substrate ( 1 ) reaching deep trench isolation ( 4 ) is shaped. A method of fabricating a semiconductor structure comprising the steps of: providing a semiconductor layer stack comprising a semiconductor substrate ( 1 ), a highly doped buried layer ( 2 ), which at least in parts of the semiconductor substrate ( 1 ), and a monocrystalline semiconductor layer ( 6 ) on the semiconductor substrate ( 1 ) and the buried layer ( 2 ) is arranged; Producing a lateral region of the semiconductor substrate ( 1 ) electrically insulating, into the semiconductor substrate ( 1 ) reaching deep trench isolation ( 4 ); Manufacturing a sinker insulation frame formed from isolation trenches ( 5 ), which from the surface of the semiconductor layer ( 6 ) to substantially the buried layer ( 2 ) enough; and - producing a sinker diffusion area ( 3 ) within the sinker isolation frame ( 5 ), characterized in that the trenches of the deep trench isolation ( 4 ) and the sinker insulation cream ( 5 ) are produced in a same etching step.