DE102006012007A1 - Power semiconductor module, has insulation layer covering upper and edge sides of chip, and inner housing section under release of source and gate contact surfaces of chip and contact terminal surfaces on source and gate outer contacts - Google Patents

Abstract

The module has a power semiconductor chip (6) with a drain contact surface fixed on upper sides (10) of flat outer contacts. An insulation layer (14) covers upper and edge sides of the chip, and an inner housing section under release of source and gate contact surfaces of the chip and contact terminal surfaces on upper sides of source and gate outer contacts. The layer bridges an intermediate space between the contacts in the section. Independent claims are also included for the following: (1) a method of producing a power semiconductor module with surface mountable flat outer contacts (2) an application of a method for producing a power semiconductor module with surface mountable flat outer contacts in a plastic thin dual small outline non leaded package (P-TDSON)-housings and/or modifications of these type of housings and plastic very thin profile quad flat non leaded package (P-VQFN)-housings and/or modifications of these type of housings.

Description

The The invention relates to a power semiconductor module in a plastic housing surface mount flat external contacts and a method for producing the same using a planar connection technology on a metal circuit carrier (leadframe). In such a power semiconductor module with surface mountable flat external contacts are the external contact surfaces of external contacts arranged on the bottom of the semiconductor module. Such a thing Power semiconductor module has at least one power semiconductor chip on, wherein the upper side of the power semiconductor chip source contact surfaces and Gate contact areas has and the back of the semiconductor chip has a drain contact surface.

The Contacting of power semiconductor components, in particular of Power semiconductor modules with high current density in a plastic housing problematic because of the high loss of heat development. This heat loss must be within the plastic housing via connections with preferably high electrical and thermal conductivity of the contact surfaces of the Semiconductor chips to corresponding terminals of a metal Circuit carrier, which also under the keyword "lead frame "is known dissipated become.

A Conventional connection technology is wire bonding. there The connections are made by so-called bonding wires of gold or aluminum produced, wherein the contact between the bonding wires and the contact surfaces on the semiconductor chip and the contact surfaces on a circuit carrier Alloying of the involved metals under energy supply arises. however are the relatively small cross-sectional areas of the wire connections authoritative for one high connection resistance. Furthermore such wire connections are a further reduction the contact surfaces the top of the semiconductor chip, a progressive chip miniaturization and an increasing integration in the way.

Further Disadvantages of such bonding wire technologies are the thermomechanical loads of the semiconductor chip during the contacting and the possible bonding wire drift in the pressing mass coating the module components when embedded in a plastic housing composition. Further Another weak point for bond wire tears are the molten ones and later recrystallized areas at the contact surfaces. There are aging processes of the Alloy compounds observed, with diffusion processes a creeping increase the contact resistance and thus a reliability problem for the power semiconductor module represent.

A Alternative was for the so-called P-TDSON housing (Plastic Thin Dual Small Outline Non-leaded package). This alternative contacting method is also known by the term "clamp strap method", wherein a metal bracket instead of the bonding wires due to its larger cross-sectional area one large-area contacting the source contact surfaces allows which leads to a reduction of electrical resistance. simultaneously becomes with the clamp strap method the heat dissipation from the chip tops by a reduced thermal resistance and an increased Heat buffer capacity one such clamp connection improved. However, the strap structure limits due to its dimensions a progressive and improved integration of power semiconductor chips in corresponding power semiconductor modules.

The flexibility such strap structures is small in terms of the arrangement of the bonding pads, which is why a change each a new bracket construction required. The contact on the contact surfaces of the Semiconductor chips or on the contact pads of the so-called "lead frame" by soldering with a solder paste. Here eliminates the removal of flux residues a subsequent cleaning step a critical process. The flux residues have a perfect adhesion to the components when embedding and adversely affect the reliability of the power semiconductor module. In addition, fatigue cracks in the solder joints at thermomechanical loads a reliability problem.

Out The document WO 2004/077584 A2 are large-area metal coatings known, which applied to an insulating layer of a substrate and at the same time the connection to contact surfaces make the top of semiconductor chips. This technology requires as a circuit carrier a suitably prepared large-area substrate, as it is for BGA components is known as a wiring substrate. Such conditions a large plane Substrate, however, in component housings such as the P-TDSON housing or P-VQFN housing (Plastic Very thin profile Quad Flat Non-leaded package) not given.

Also the publication US 5,637,922 offers solutions with metal layers applied over large areas and works with a conventional circuit carrier on a "lead frame" basis with laterally protruding flat conductors. Furthermore, from the publication "Planar Me Liang et al., 53rd Electronic Compound and Technology Conference 2003, pp. 1090-1094, discloses aligning silicon power semiconductor devices with ceramic substrates such that large area metal coatings on the coplanar ceramic substrate and semiconductor die surface are provided However, this solution also has the disadvantage that it is not very flexible and can not easily be transferred to power semiconductor modules with plastic housings and with surface-mountable contacts, as offered by the P-TDSON or P-VQFN housings or have.

task The invention is to overcome the disadvantages of the prior art and contacting possibilities within power semiconductor modules in plastic packages too This is a step closer to miniaturization, especially for P-TDSON or P-VQFN packages can hold and to the constant Miniaturization are customizable.

These The object is achieved with the subject matter of the independent claims. advantageous Further developments of the invention will become apparent from the dependent claims.

According to the invention is a Power semiconductor module with surface-mountable flat external contacts, which provide on the bottom of the power semiconductor module provide external contact surfaces. The power semiconductor module has at least one power semiconductor chip on, wherein the upper side of the power semiconductor chip source contact surfaces and Gate contact areas and the back of the semiconductor chip has a drain contact surface. The flat external contacts have tops, which are arranged in an inner housing plane. The Drain contact area the back of the semiconductor chip is on the top of a drain outer contact fixed. An insulation layer, preferably an insulation film covers the top and edge sides of the semiconductor chip, as well the housing level with the release of the source and Gate contact areas on top of the semiconductor chip. Furthermore, the insulation layer covers leaving contact pads free, the tops of the source and gate external contact. This bridges the Approximate insulation layer planar a space between the external contacts in the area of inner housing level.

One Another aspect of the invention relates to a power semiconductor module with surface mountable flat external contacts, which are provided on the underside of the semiconductor module. This Power semiconductor module has at least one power semiconductor chip wherein the top of the power semiconductor chip has source pads and gate pads and the backside of the semiconductor chip has a drain contact surface. In addition, show the flat external contacts Upper sides, which are arranged in an inner housing level and External contact surfaces on the bottom of the plastic housing exhibit.

there is the drain contact area the semiconductor chip on the top of a Drainaußenkontaktes fixed. An insulating film covers the top and the edge sides of the semiconductor chip and the housing level under release the source and gate contact surfaces the top of the semiconductor chip and under partial release the tops of the source and Gate external contacts. On this insulating foil is a metallic source connection layer arranged as a high-current strip line, located on the insulating film from the source contact surfaces to the tops of the source exterior contacts extends. Furthermore, at least one gate connection layer is provided on the insulation film arranged as a signal strip line extending from the gate pads on the semiconductor chip to the top of Gateausßenkontaktes bridging the Interspace between the external contacts extends.

These Power semiconductor modules have the advantage that the source contact surfaces the top of the semiconductor chip interconnected to form a large-area interconnection layer are, wherein both the step size or the so-called "pitch" of the source contact surfaces as also the areal Extension of the individual source contact surface are arbitrarily reduced can, without a reliable Connection to the flat Stripping metallization on the insulation layer. The Same goes for the gate contact surfaces, which are merged into a smaller coating area and from there similar like the source contact surfaces on top of the semiconductor chip via a corresponding gate connection layer with the top of a gate external contact are directly connected. Except the insulation layer are no further substrates or intermediate layers required to electrically contact the source pads or gate pads with the corresponding tops of the external contacts in the area of Housing bottom connect to. It is also possible, on expansive, itself outward extending outer flat conductor to renounce and for the contacting with the available bottom of the power semiconductor module Completely get along.

Another advantage is that now the miniaturization of such power semiconductor modules can proceed without new clamps have to be developed or that corresponding outer flat conductor or wiring substrates, as they are still used in the prior art, are to be adapted to the connecting layers or to the shape of the semiconductor chip.

In a further embodiment According to the invention, the insulating layer has a laminated structured surface Isolation film on. With such an insulating film, on the one hand the coplanar housing level not covered by the semiconductor chip with its drain contact and also to the edges of the semiconductor chip and clings to the top of the semiconductor chip, is the advantage connected, that a high flexibility in the construction of a power semiconductor module possible is and such power semiconductor module by cost Laminating differently structured layers or foils on the tops of the external contacts and inexpensively manufactured on the tops of the semiconductor chips can be.

As Generally known, insulating films are not rigid but follow the thermal stresses by compensatory expansion or contraction and provide the advantage that the interconnecting layer disposed thereon as well as the source contact surfaces as well as for the gate contact surfaces can follow this expansion behavior without embrittlement or Microcracking, as known from bonding wires occur. A Such film has the further advantage of being adapted to the circumstances on the coplanar housing level adapts and with its drain contact surface on the coplanar housing level arranged semiconductor chip can wrap around without tension. For this purpose, the entire system is applied when applying the insulation film heats the softening temperature of the film. Another advantage is that the connecting film forms a bridge, which the space between the external contacts bridged approximately planar in the area of the inner coplanar housing plane and a platform for provides the application of the tie layers.

In a further preferred embodiment of the invention, the source and gate interconnect layers have one multilayer metal layer on. This multilayer metal layer can once a lower metal layer for adhesion and improvement contacting the source contact surfaces to be contacted and Enable gate contact surfaces and another metal layer having the required Thickness for a low-resistance connection of the source or gate contact surfaces with the ensures appropriate source or gate external contacts.

In a further embodiment The invention features the source or gate interconnect layer upper metal layer of copper or a copper alloy. These embodiment The invention has the advantage that copper is a guarantor for a low-impedance electrical connection is and that this copper in large thickness over a galvanic or chemical deposition on top of the insulation layer or the insulation film can be deposited. Because this copper layer is not alone on the top of the semiconductor chip, but can also extend to the coplanar inner housing level not already preparing this low - resistance coating on the corresponding semiconductor wafer are applied, but it is this deposition process for to provide the completion and assembly of the power semiconductor module.

Furthermore indicates the power semiconductor module to the flat surface mountable external contacts also a copper layer or a copper alloy. These Copper layer or copper alloy was made of a metal strip in appropriate structures for the outside outer contact surfaces, the Drain outer contact surface and / or the Gateaußenkontaktfläche structured. For this purpose, preferably an etching technique used. On the undersides of the external contacts can also solderable Coatings be applied. These have solderable coatings the advantage of being surface mount the external contacts the power semiconductor module in the simplest way with appropriate parent Circuit boards is connectable.

In In another aspect of the invention, the power semiconductor module on the power semiconductor chip one or more stacked semiconductor chips so on the top of a power semiconductor chip are fixed, that they are part of the top of the power semiconductor chip take advantage of. As stacked semiconductor devices are preferably Logic components in use, the smaller in their areal extent are as the power semiconductor chips. For the wiring of this stacked Semiconductor chips on the power semiconductor chips can also the above-disclosed technique with insulating layer and metallic Connecting layers are used.

In the case of the stacked semiconductor device, it is even possible to provide internal connection layers between contact areas of the stacked semiconductor chip and contact areas of the power semiconductor chips. This can be done with the same process step as the application of the bonding layers on the other components of the power semiconductor module. Thus, the corresponding connection layers are produced simultaneously with the connection layers between source contact pads and source external contacts, and between gate pads and gate external contacts.

at Use of an insulating film can keep the source and Gate contact areas ensured on top of the semiconductor chip thereby be that before applying the insulating film this accordingly having punched areas with through holes. Such a punching technique is in the production of large area contacts on top of the semiconductor chip and / or the top of the external contacts advantageous. Have to but only small through holes through the insulation film are created, so it is beneficial to first the Apply insulation film and then laser ablation the Keep the source contact areas clear or the gate contact surfaces to reach the top of the semiconductor chip.

One Method for producing a power semiconductor module with surface mountable flat External contacts, which are arranged on the underside of the plastic housing, has the subsequent process steps.

First, will an arrangement of flat external contacts for the surface-mountable semiconductor module produced in a Flachlei terrahmen, the tops of the external contacts be aligned and a coplanar inner housing level form. Furthermore a semiconductor chip is produced, wherein the top side of the semiconductor chip Source contact areas and gate pads and the backside of the semiconductor chip has a drain contact surface. Subsequently, will This semiconductor chip with its drain contact surface on its back on an upper side of a drain outer contact of the lead frame fixed.

After that a structured insulation layer is applied to this structure, these being on the margins and the top of the semiconductor chip and the coplanar housing level leaving the source and gate pads free and partially free the tops of the external contacts is applied. After all a structured metal layer is applied as a planar one Connecting layer between source contact surfaces and surfaces of Source external contacts and between gate pads on top of the semiconductor chip and the surfaces of the Gate external contacts. After applying this compound layer can now be the finished components in a plastic housing compound be embedded, with the external contacts on the bottom of the plastic housing with their external contact surfaces the plastic housing compound protrude.

This Method has the advantage that with increasing miniaturization also the insulation layer and the metallic compound layer can be scaled down without problems. Besides, this procedure has the advantage that the entire structure of the semiconductor module on a Flat conductor frame can be made, the only external contacts has and this provides on the bottom of the semiconductor module.

• 1. eines geringen elektrischen Widerstandes und einer hohen effektiven Wärmeabfuhr von der Chipoberseite aufgrund des großen Verbindungsquerschnitts im Vergleich zu herkömmlichen Bonddrähten;
• 2. eines schnellen und verlustarmen Schaltens durch verminderte Streuinduktivitäten der relativ flachen Verbindungsschicht;
• 3. der gleichzeitigen Herstellung aller Verbindungen und wird mit der zunehmenden Anzahl von Verbindungen, die in einem Gehäuse zu erzeugen sind, ständig vorteilhafter;
• 4. einer deutlich höheren Integrationsdichte durch die Reduzierung der minimal erforderlichen Kontaktflächengrößen für die Sourcekontaktflächen und die Gatekontaktflächen;
• 5. einer hohen Flexibilität des Strukturierungsprozesses bei konstruktiven Änderungen der Kontaktflächengeometrien;
• 6. einer Auskleidung der Kontaktflächen mit einer diffusionshemmenden und/oder haftverbesserenden Schicht unterhalb der Verbindungsschicht, womit zuverlässigkeitsrelevante Schwachstellen an den Metallkontaktstellen vermieden werden;
• 7. eines Stapelaufbaus mit abwechselnder Folge von Isolations- und Verbindungsschichten, der durch die Mehrlagigkeit der Verdrahtungsschicht vielfältige Möglichkeiten der Leitungsentflechtung bietet,
• 8. einer geringeren Bauhöhe der Verbindung, die schließlich einen flachen Gehäuseaufbau ermöglicht.

Finally, the method with the provided planar connection technology has the advantages:

• 1. a low electrical resistance and a high effective heat dissipation from the chip top due to the large cross-sectional area compared to conventional bonding wires;
• 2. a fast and low-loss switching by reduced stray inductance of the relatively flat connection layer;
• 3. the simultaneous production of all connections and becomes more and more advantageous with the increasing number of connections to be produced in a housing;
• 4. a significantly higher integration density by reducing the minimum required contact area sizes for the source contact areas and the gate contact areas;
• 5. a high flexibility of the structuring process with constructive changes of the contact surface geometries;
• 6. a lining of the contact surfaces with a diffusion-inhibiting and / or adhesion-improving layer below the connecting layer, whereby reliability-relevant weak points at the metal contact points are avoided;
• 7. a stacking structure with alternating sequence of insulation and interconnection layers, which offers manifold possibilities of line unbundling due to the multilayeredness of the wiring layer,
• 8. a lower height of the connection, which finally allows a flat housing structure.

Although planar connection techniques exist as mentioned above in various embodiments, but the application is so far limited to insulating substrates. In the present invention, the use of a planar interconnect technique in a lead frame based plastic package is realized in which the first deposited insulating layer has a bridge supporting the tie layer over the trenches between the drain outer contact on which the chip is mounted and the bridge forms further housing outer contacts. In the method described above, an insulation layer and a metallic connection layer are thus advantageously deposited in succession on the "lead frame" equipped with one or more semiconductor chips brought and also structured in a way that leads to large, flat connections between the contact surfaces of the semiconductor chip and the tops of the external contacts.

In a preferred embodiment of the method is for fixing the semiconductor chip with this his drain contact area on an upper side of a drain contact of the lead frame soldered. Preparing for the soldering For example, either the top of the drain outer contact may be a solder layer and / or the back be provided with a solder layer of the semiconductor chip.

In a further preferred embodiment The invention is an electrically conductive instead of the solder layer Adhesive used. This electrically conductive adhesive can also by a double-sided adhesive, but electrically conductive film will be realized. This has the advantage of being an extreme heating up for joining of the semiconductor chip to the drain outer contact are avoided can, especially the temperatures for a curing the adhesive layer or the adhesive film lower by several 10 ° C. are as the required temperatures for a soldering.

As described above, is preferably in this process an insulating film used to the trenches between the individual external contact surfaces of coplanar inner housing plane to bridge until in the final one Process step all assembled components in a plastic housing composition be embedded. Is an insulating film as insulation layer used, so this can be prepared before the application so be punched that corresponding through holes in the places be where access to the tops of the external contacts and access to the source pads and / or the gate pads the top of the semiconductor chip is required.

at an afterthought Structuring of the insulation film can be achieved by laser ablation corresponding source contacts or gate contacts and the corresponding Areas of the tops of the external contacts be exposed. The application of the bonding layer may be in layers take place, wherein a lower first layer by means of sputtering is deposited and then This sputtered layer is based on a second basis To deposit thicker compound layer by means of electrolytic process. The first layer may be an adhesion-promoting and / or a diffusion-inhibiting electrically conductive layer can be applied to adhesion problems from the outset and / or embrittlement problems by diffusion and formation of intermetallic phases. The Invention involves the use of the above method of manufacture of semiconductor modules, in particular in so-called P-TDSON packages and / or in P-VQFN packages or modifications of these types of enclosures.

The The invention will now be described with reference to the accompanying figures.

1 shows a schematic plan view of a power semiconductor module of a first embodiment of the invention;

2 shows a schematic cross section through the power semiconductor module according to 1 along the section line AA;

3 shows a schematic plan view of a power semiconductor module of a second embodiment of the invention.

4 shows a schematic plan view of a power semiconductor module of a third embodiment of the invention.

1 shows a schematic plan view of a power semiconductor module 1 a first embodiment of the invention. This power semiconductor module 1 is in a plastic housing 5 arranged with flat external contacts (leadless package). In this plan view, to clarify the components used in the power semiconductor module 1 or the plastic housing 5 embedded, the plastic housing compound 5 omitted and only with a dashed line 28 the outer contour of the plastic housing 5 shown.

As the top component in this plastic housing compound 5 is a large-scale connection layer 21 to be seen, which is flat over most of a top 7 a power semiconductor chip 6 extends, with the top 7 a contact pad 23 for a plurality of source electrodes of the power semiconductor chip 6 on which this source connection surface 23 is arranged and the same time over the edge 15 of the semiconductor chip 6 juts out and up to the areas of top 10 from source external contacts 19 extends.

This connection layer 21 is on a large insulation film 25 with the edge sides 29 . 30 . 31 and 32 arranged, with this insulation film 25 not just the connection layer 21 carries, but also a connecting layer 22 having a gate contact surface 24 on the top 7 of the semiconductor chip 6 with the top 10 a gate external contact 20 combines. The conductive interconnect layers can be either through a Mask can be applied structured or applied over a large area and then patterned by means of a photolithographic process and subsequent etching process.

The insulation film 25 serves as an insulation layer 14 and also covers the trenches 34 between the external contacts 13 . 19 and 20 from. Under the insulation film 25 is on the outside contact 3 on the left side of the 1 the semiconductor chip 9 with its edge sides 15 . 16 . 17 and 18 arranged.

The not visible in this illustration back of the semiconductor chip 6 has a drain contact surface which covers the entire back side of the semiconductor chip 6 occupies. With this drain contact surface is the semiconductor chip 6 on the top 10 a Drainaußenkontaktes 13 arranged in its planar extent in this embodiment of the invention is greater than the areal extent of the semiconductor chip 6 so that the semiconductor chip 6 taking into account the possible assembly tolerances safely on the large drain external contact 13 can be fixed. The tops 10 the external contacts 3 are coplanar arranged in a housing plane and protrude with their undersides not shown as external contact surfaces on the not visible here underside of the plastic housing 5 out.

2 shows a schematic cross section through the power semiconductor module 1 according to 1 along the cutting plane AA. Components with the same functions as in 1 are marked with the same reference numerals and not explained separately. Like this cross section of the 2 shows is the power semiconductor module 1 built on a leadframe from which the external contact surfaces 3 to be shown, their undersides 12 on the bottom 4 of the semiconductor module 4 of the plastic housing 5 protrude or at least free of a plastic housing composition 5 are.

In this cross-sectional plane are due to the sectional plane AA of 1 the cross section of the large drain outer contact 13 and a source external contact 19 with their external contact surfaces 27 to see whose tops 10 coplanar in an inner housing plane 11 whose position is the dashed line 33 is shown are arranged. On the top 10 the Drainaußenkontaktes 13 is with his back 8th that have a drain contact surface 9 has, the semiconductor chip 6 fixed. On the top 7 of the semiconductor chip 6 is in the border areas 15 and 17 a dimensionally stable insulating film at room temperature 25 laminated.

The insulation film 25 made of a thermoplastic material is pressed during the lamination on the substrate and heated so that they are on the edge sides 15 and 17 of the semiconductor chip 6 clings, and after cooling at room temperature, a stable bridge 36 over the ditch 34 between the external contacts 19 and 13 forms. On this isolation foil 25 can then have a continuous source connection layer 21 are deposited, which the source contact surfaces on the top 7 of the semiconductor chip 6 large area with the tops 10 the source external contacts 19 connects electrically.

Making this connection layer 21 that from the top 7 of the semiconductor chip 6 up to the top 10 the source external contacts 19 can be achieved by depositing two layers, namely a first metal layer as an adhesion-promoting and / or diffusion-inhibiting layer, and a further layer as a low-resistance electrical connection layer 21 be applied. To do this, first one on both the top 7 of the semiconductor chip 6 as well as on the top 35 the film applied well adhering metal. Subsequently, this metal coating is used to deposit a low-resistance layer of sufficient thickness of copper or a copper alloy on this metal layer, which is also called seed layer. The deposition can be continued until a low-resistance electrical connection between the contact surfaces on the top 7 of the semiconductor chip and the tops 10 the external contacts 3 is reached.

In the final embedding of these components of the power semiconductor module 1 in a plastic housing compound 5 also become the trenches 34 between the external contacts 3 with plastic housing compound 5 filled up, resulting in the insulation film 25 formed bridge 36 for corresponding metallic compound layers 21 is supported. In contrast to a bonding wire technology, when embedding the components of the power semiconductor module 1 no drift of bonding wires and thus of unwanted short circuits occur. Furthermore, it allows for the surface contour of the semiconductor chip 6 and to the inner housing level 11 adapted laminated insulating foil 25 the application of a large-area and thick wiring structure within the plastic housing composition.

3 shows a schematic plan view of a power semiconductor module 2 a second embodiment of the invention. Components with the same functions as in 1 are marked with the same reference numerals and not explained separately.

In this embodiment of the invention are within the plastic housing 5 whose outer contour is a dashed line 28 marked in is two power semiconductor chips 6.1 and 6.2 with appropriate tops 10 from external contacts 3 connected, wherein the power semiconductor chip 6.1 on its top 7.1 a logic semiconductor chip 6.3 having. On the tops 7.1 . 7.2 and 7.3 the semiconductor chips 6.1 . 6.2 and 6.3 as well as partially on the topsides 10 the external contacts 3 becomes an insulation film 25 with their edge sides 29 . 30 . 31 and 32 arranged, which the edge sides 15.1 to 18.1 . 15.2 to 18.2 and 15.3 to 18.3 the semiconductor chips 6.1 . 6.2 and 6.3 covers.

On this isolation layer 14 in the form of an insulating film 25 are not just tie layers 21.1 and 21.2 angeord net, which the source contact surfaces of the semiconductor chips 6.1 and 6.2 with corresponding external source contacts 19.1 and 19.2 connect, but also other connecting layers 26 , the contact areas of the stacked logic semiconductor chip 6.3 with contact surfaces of the power semiconductor chip 6.1 or the power semiconductor chip 6.2 connect.

4 shows a schematic plan view of a power semiconductor module 40 a third embodiment of the invention. Components with the same functions as in the preceding figures are identified by the same reference numerals and are not explained separately.

The 4 shows active components of a voltage regulator wherein the plastic housing composition is omitted for clarity and only the contour of the plastic housing 5 with a dashed line 28 will be shown. In this embodiment of the invention are within the plastic housing 5 two power semiconductor chips or power ICs 41 and 42 with appropriate tops 10 connected by external contacts, wherein the power semiconductor chip 41 on its top 7.1 a stacked logic semiconductor chip 43 wearing. On the tops 7.1 . 7.2 and 7.3 of semiconductor chips 41 . 42 and 43 , as well as partially on the tops 10 the external contacts 3 is an insulation film 25 with their edge sides 29 . 30 . 31 and 32 arranged, which the edge sides of the semiconductor chips 40 . 41 and 42 covers. At the same time, this insulation foil bridges over 25 Spaces between the external contacts 3 ,

Furthermore, the insulation film has 25 Openings for contact surfaces on the semiconductor chips 40 . 41 and 43 on, as well as openings to contact pads on the tops 10 the external contacts 3 , so on the insulation film 25 a laminate with structured strip lines 44 to 49 such as 75 and 76 can be arranged partially the semiconductor chips 40 . 41 and 43 with each other and partly with the tops 10 the external contacts 3 through the insulation film 25 connect through.

The external contacts 62 . 63 . 64 and 65 are assigned to the logic semiconductor chip and via their arranged on the top contact pads 55 . 57 . 59 and 61 as well as the strip lines 46 . 47 . 48 and 59 with contact surfaces 54 . 56 . 58 and 60 connected to the logic IC. About these external contacts 62 . 63 . 64 and 65 Thus, the logic IC can be controlled. The logic IC itself is above its contact surface 50 over the stripline 44 as well as via the gate contact surface 51 of the first power semiconductor chip 41 to the gate of the first power semiconductor chip 41 electrically connected.

The second power semiconductor chip 42 , which is also only partly from the insulation film 25 is covered by the stacked logic semiconductor chip 43 over the contact surface 52 and the stripline 45 as well as the gate contact area 53 of the second power semiconductor chip 42 driven.

In addition to this signal strip lines 44 . 45 . 46 . 47 . 48 is the one on the first power semiconductor chip 41 stacked logic semiconductor chip 43 with corresponding external contacts 62 . 63 . 64 and 65 as well as with gate contact surfaces 51 and 53 the two power semiconductor chips 41 and 42 electrically connected.

In addition, the power semiconductor module has high current strip lines 75 and 76 on which on the one hand the source contact surface 73 with the drain contact surface 74 on the top 10 the Drainaußenkontaktes 70 of the second power semiconductor chip 42 connects and another high current strip line 76 which the source contact surface 71 of the second power semiconductor chip 42 with a contact pad 72 on the top 10 the source external contacts 66 . 67 , and 68 combines. Both the high current strip lines 75 and 76 as well as the signal strip lines 44 to 49 can bridge the gaps between the external contacts, as they pass through the large-area insulation film that extends both over the tops of the semiconductor ICs 41 . 42 and 43 as well as over the tops of the external contacts 62 to 70 be supported by bridging the gaps between the external contacts.

1

The power semiconductor module

(1. embodiment)

2

The power semiconductor module

(2nd embodiment)

3

outside Contact

4

bottom of the semiconductor module or

of Plastic housing

5

Plastic housing or

Plastic housing composition

6; 6.1; 6.2; 6.3

Semiconductor chip

7; 7.1; 7.2; 7.3

top of the semiconductor chip

8th

back of the semiconductor chip

9

Drain contact area

10

top the external contacts

11

inner coplanar housing level

12

bottom the external contacts

13

Drain external contact

14

insulation layer

15; 15.1; 15.2; 15.3

edge side of the semiconductor chip

16; 16.1; 16.2; 16.3

edge side of the semiconductor chip

17; 17.1; 17.2; 17.3

edge side of the semiconductor chip

18; 18.1; 18.2; 18.3

edge side of the semiconductor chip

19; 19.1; 19.2

Source external contact

20

Gate external contact

21; 21.1; 21.2

Source link layer

22

Gate connecting layer

23

Source contact surface

24

Gate contact area

25

insulation blanket

26

link layer on stacked

Semiconductor chip

27

External contact area

28

dashed line

29

edge the insulation film

30

edge the insulation film

31

edge the insulation film

32

edge the insulation film

33

dashed line

34

dig between external contacts

35

top the foil

36

planar bridge from insulation film

37

edge side of the housing

40

The power semiconductor module (3rd embodiment)

41

Power semiconductor chip or power IC

42

Power semiconductor chip or power IC

43

Logic semiconductor chip or logic IC

44

stripline for controlling the gate contact surface

of first power semiconductor chips

45

stripline for controlling the gate contact surface

of second power semiconductor chips

46

stripline

47

stripline

48

stripline

49

stripline

50

Contact surface of the stripline 44

51

Contact surface of the stripline 44

52

Contact surface of the stripline 45

53

Contact surface of the stripline 45

54

Contact surface of the stripline 46

55

Contact surface of the stripline 46

56

Contact surface of the stripline 47

57

Contact surface of the stripline 47

58

Contact surface of the stripline 48

59

Contact surface of the stripline 48

60

Contact surface of the stripline 49

61

Contact surface of the stripline 49

62

outside Contact of the logic semiconductor chip

63

outside Contact of the logic semiconductor chip

64

outside Contact of the logic semiconductor chip

65

outside Contact of the logic semiconductor chip

66

Source external contact

67

Source external contact

68

Source external contact

69

Drain external contact of the first semiconductor chip

70

Drain external contact of the second semiconductor chip

71

Source contact surface of the second Semiconductor chips

72

Contact surface on external source contact

73

Source contact surface on first semiconductor chip

74

Drain contact surface on Top of Drainaußenkontaktes

of second semiconductor chips

75

High-current stripline

76

High-current stripline

Claims (22)

Power semiconductor module with surface-mountable flat external contacts ( 3 ) on the bottom ( 4 ) of the power semiconductor module ( 1 ) Provide external contact surfaces, and with at least one power semiconductor chip ( 6 ), the top ( 7 ) of the power semiconductor chip ( 6 ) Source pads and gate pads and the back side ( 8th ) of the semiconductor chip ( 6 ) a drain contact surface ( 9 ), wherein the flat external contacts ( 3 ) Topsides ( 10 ), which in an inner housing level ( 11 ), wherein the drain contact surface ( 9 ) of the back side of the semiconductor chip ( 6 ) on the top ( 10 ) of a drain outer contact ( 13 ), and wherein an insulation layer ( 14 ) the top ( 7 ) and margins ( 15 to 18 ) of the semiconductor chip ( 6 ) as well as the housing level ( 11 ) leaving the source and gate contact surfaces on the top side ( 7 ) of the semiconductor chip ( 6 ) and leaving contact pads on the topsides ( 10 ) the source ( 19 ) and gate external contacts ( 20 ), and wherein the insulating layer ( 14 ) a gap between the external contacts in the region of the inner housing level ( 11 ) bridged approximately planar. Semiconductor module according to claim 1, characterized in that the power semiconductor module with surface-mountable flat external contacts ( 3 ) on the bottom ( 4 ) of the power semiconductor module ( 1 ) made of a plastic housing ( 5 protrude), and with at least one power semiconductor chip ( 6 ), the top ( 7 ) of the power semiconductor chip ( 6 ) Source pads and gate pads and the back side ( 8th ) of the semiconductor chip ( 6 ) a drain contact surface ( 9 ), wherein the flat external contacts ( 3 ) Topsides ( 10 ), which in an inner housing level ( 11 ) are arranged and with their undersides ( 12 ) from the plastic housing ( 5 protrude), wherein the drain contact surface ( 9 ) of the semiconductor chip ( 6 ) on the top ( 10 ) of a drain outer contact ( 13 ), and wherein an insulation film ( 25 ) the top ( 7 ) and margins ( 15 to 18 ) of the semiconductor chip ( 6 ) as well as the inner housing level ( 11 ) leaving the source and gate contact surfaces on the top side ( 7 ) of the semiconductor chip ( 6 ) and leaving contact pads on the topsides ( 10 ) the source ( 19 ) and gate external contacts ( 20 ), and wherein a planar metallic source connection layer ( 21 ) on the insulation film ( 25 ) from the source contact surfaces to the topsides ( 10 ) of the external source contacts ( 19 ) and a gate connection layer ( 22 ) from the gate pads to the top ( 10 ) of the gate external contact ( 20 ) while bridging the gap between the external contacts ( 3 ). Semiconductor module according to claim 1 and claim 2, characterized in that the source ( 21 ) or gate connection layer ( 22 ) has a multilayer metal layer. Semiconductor module according to Claim 3, characterized the multilayer metal layer is an adhesion-promoting lower metal layer and a low-resistance upper metal layer. Semiconductor module according to one of the preceding claims, characterized in that the source ( 21 ) or gate connection layer ( 22 ) has an upper metal layer of copper or of a copper alloy. Semiconductor module according to one of the preceding claims, characterized in that the flat surface-mountable external contacts ( 3 ) Have copper or a copper alloy. Semiconductor module according to one of the preceding claims, characterized in that the undersides ( 12 ) of external contacts ( 3 ) have a solderable coating. Semiconductor module according to one of the preceding claims, characterized in that on the semiconductor chip ( 6 ) a stacked semiconductor chip ( 6.3 ), wherein the stacked semiconductor chip ( 6.3 ) has an integrated logic circuit. Semiconductor module according to one of claims 2 to 8, characterized in that the insulating film ( 25 ) leaving contact surfaces on the top ( 7.3 ) of the stacked semiconductor chip ( 6.3 ) covers it and a structured planar metallic compound layer ( 26 ) carries the partial contact surfaces of the stacked semiconductor chip ( 6.3 ) with contact surfaces of the semiconductor chip ( 6.1 . 6.2 ) electrically connects. Semiconductor module according to one of the preceding claims, characterized in that the semiconductor module ( 2 ) multiple power semiconductor chips ( 6.1 . 6.2 ) at the coplanar housing level ( 11 ) having. Method for producing a power semiconductor module ( 1 ) with surface-mountable flat external contacts ( 3 ) on the bottom ( 4 ) of the plastic housing ( 5 ), wherein the method comprises the following method steps: - producing an arrangement of flat external contacts ( 3 ) for the surface-mountable semiconductor module ( 1 ) in a leadframe, the topsides ( 10 ) are aligned and a coplanar housing level ( 11 ) form; Manufacturing a semiconductor chip ( 6 ), where the Top side ( 7 ) of the semiconductor chip ( 6 ) Source contact surfaces ( 23 ) and gate pads ( 24 ) and the back ( 8th ) of the semiconductor chip ( 6 ) a drain contact surface ( 9 ) exhibit; Fixing the semiconductor chip ( 6 ) with its drain contact surface ( 9 ) on a top side ( 10 ) of a drain outer contact ( 13 ) of the lead frame; - Applying a structured insulation layer ( 14 ) on the margins ( 15 to 18 ) and the top ( 7 ) of the semiconductor chip ( 6 ) and to the coplanar housing level ( 11 ), leaving the source ( 23 ) and gate pads ( 24 ) and with partial release of the tops ( 10 ) of external contacts ( 3 ); Application of a structured metal layer as a planar connection layer ( 21 . 22 ) between source contact surfaces ( 23 ) and surfaces ( 10 ) of the external source contacts ( 19 ), and between gate pads ( 24 ) and surfaces ( 10 ) of the gate external contacts ( 20 ), - Embedding the previously assembled components in a plastic housing composition ( 5 ), external contacts ( 3 ) on the bottom ( 4 ) of the plastic housing ( 5 ) with their external contact surfaces ( 27 ) from the plastic housing composition ( 5 protrude). A method according to claim 11, characterized in that for fixing the semiconductor chip ( 6 ) with its drain contact surface ( 9 ) on a top side ( 10 ) of a drain outer contact ( 13 ) of the leadframe of the semiconductor chip ( 6 ) is soldered. A method according to claim 11 or claim 12, characterized in that for fixing the semiconductor chip ( 6 ) with its drain contact surface ( 9 ) on a top side ( 10 ) of a drain outer contact ( 13 ) of the leadframe of the semiconductor chip ( 6 ) is glued. Method according to one of claims 11 to 13, characterized in that for applying a structured insulating layer ( 14 ) on the margins ( 15 to 18 ) and the top ( 7 ) of the semiconductor chip ( 6 ) and on the inner housing level ( 11 ) an insulation film ( 25 ) is laminated. Method according to one of claims 11 to 14, characterized in that to keep the source ( 23 ) and gate pads ( 24 ) and to partially free the tops ( 10 ) of external contacts ( 3 ) an insulation film ( 25 ) is punched before application. Method according to one of claims 11 to 14, characterized in that to keep the source ( 23 ) and gate pads ( 24 ) and to partially free the tops ( 10 ) of external contacts ( 3 ) an insulation film ( 25 ) is structured after application by laser ablation. Method according to one of claims 11 to 16, characterized in that the connecting layer ( 21 . 22 ) is applied in layers. Method according to one of claims 11 to 17, characterized in that a first layer of the bonding layer ( 21 . 22 ) is deposited by sputtering. Method according to one of claims 11 to 18, characterized in that a second layer of the bonding layer ( 21 . 22 ) is deposited by means of electrolytic process. The method of claim 18 or claim 19, characterized characterized in that within the first layer an adhesion-promoting and / or a diffusion-inhibiting electrically conductive layer applied becomes. Use of the method according to one of claims 11 to 20 for the production of semiconductor modules in P-TDSON (Plastic Thin Dual Small Outline Non-leaded package) - Enclosures and / or Modifications this type of housing. Use of the method according to one of claims 11 to 20 for the production of semiconductor modules in P-VQFN (Plastic Very thin profile Quad Flat Non-leaded package) - Enclosures and / or Modifications this type of housing.