DE102005055402A1 - Producing wiring structure on wafer substrate for center row arrangement or wafer level packaging comprises sputtering of seed layer to form trench and application of copper layer - Google Patents
Producing wiring structure on wafer substrate for center row arrangement or wafer level packaging comprises sputtering of seed layer to form trench and application of copper layer Download PDFInfo
- Publication number
- DE102005055402A1 DE102005055402A1 DE200510055402 DE102005055402A DE102005055402A1 DE 102005055402 A1 DE102005055402 A1 DE 102005055402A1 DE 200510055402 DE200510055402 DE 200510055402 DE 102005055402 A DE102005055402 A DE 102005055402A DE 102005055402 A1 DE102005055402 A1 DE 102005055402A1
- Authority
- DE
- Germany
- Prior art keywords
- layer
- seed layer
- wafer
- photoresist
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Abstract
Description
Die Erfindung betrifft ein Verfahren zur Herstellung einer Umverdrahtung auf Substraten/einem Wafer zur elektrischen Verbindung von Bondpads einer vorgegebenen Anordnung auf dem Halbleiterchip mit Kontaktpads in einer anderen Anordnung, insbesondere zur Umverdrahtung von Bondpads in einer so genannten Center-Row-Anordnung auf dem Halbleiterchip zu Kontaktpads im Randbereich des Halbleiterchips, oder für Wafer-Level-Packaging, Chipstapelanordnungen oder KGD-Anwendungen durch Auftragen eines Dielektrikums auf das Substrat und Strukturieren desselben mittels Photolithographie zur Erzeugung einer Grabenstruktur.The The invention relates to a method for producing a rewiring on substrates / a wafer for the electrical connection of bond pads a predetermined arrangement on the semiconductor chip with contact pads in another arrangement, in particular for rewiring of bond pads in a so-called center-row arrangement on the semiconductor chip to contact pads in the edge region of the semiconductor chip, or for wafer-level packaging, Chip stacking arrangements or KGD applications by applying a Dielektrikum on the substrate and structuring the same means Photolithography for creating a trench structure.
Eine solche Umverdrahtung auf Halbleiterchips bzw. Wafern, die auch als RDL (Redistribution Layer) bezeichnet wird, besteht in der Regel aus einem Schichtstapel aus einer Kupferschicht mit einer Dicke von ca. 8 μm, einer darüber befindlichen Nickelschicht mit einer Dicke von ca. 2 μm und einer Deckschicht aus Gold mit einer Dicke von ca. 0,5 μm, mit einer Basisbreite von ca. 20 μm. Diese Umverdrahtung kann auch beim WLP (Wafer Level Packaging), bei KGD (Known-good-Die) Anwendungen, oder auch bei Chipstapelanordnungen eingesetzt werden.A such rewiring on semiconductor chips or wafers, which also as RDL (redistribution layer) is usually known from a layer stack of a copper layer with a thickness of about 8 μm, one about it located nickel layer with a thickness of about 2 microns and a cover layer made of gold with a thickness of approx. 0.5 μm, with a basic width of approx. 20 μm. This rewiring can also be used in WLP (Wafer Level Packaging), in KGD (known-good-die) applications, or in chip stacking arrangements be used.
Dieser
Stapel wird durch galvanisches Abscheiden realisiert, indem vorher
auf der Oberfläche des
Halbleiterchips oder eines anderen Substrates ein Photoresist mit
einer Dicke von ca. 13,5 μm
abgeschieden und photolithographisch strukturiert worden ist. Hierzu
ist beispielsweise SU
In
Weiterhin
muss die RDL
Der Erfindung liegt nunmehr die Aufgabe zugrunde, ein Verfahren zur Herstellung einer Umverdrahtung auf Substraten zu schaffen, mit dem eine deutliche Verkürzung der Prozesszeit erreicht werden kann.Of the Invention is now the object of a method for To create a rewiring on substrates with a significant reduction the process time can be achieved.
Erreicht wird dies bei einem Verfahren der eingangs genannten Art durch die Verfahrensschritte:
- – Sputtern einer Seed Layer auf die strukturierte Ober fläche des Substrates,
- – Aufschleudern eines Photoresists und photolithographi sches Strukturieren desselben, derart, dass ein die Grabenstruktur säumender Rand entsteht,
- – galvanisches Abscheiden einer dünnen Kupferschicht, so dass mindestens der Boden und die Wände der Graben struktur beschichtet sind,
- – Strippen des Photoresists,
- – Ätzen der nach dem Strippen frei liegenden Seed Layer, und
- – Auftragen einer dielektrischen Abdeckung durch Auf schleudern.
- Sputtering a seed layer onto the structured surface of the substrate,
- Spin-coating of a photoresist and photolithographic patterning of the same, such that a border trimming the trench structure is formed,
- - Electrodeposit a thin copper layer, so that at least the bottom and the walls of the trench structure are coated,
- Stripping the photoresist,
- Etching the stripped seed layer, and
- - Apply a dielectric cover by spin on.
Der Photoresist wird bevorzugt mit einer Dicke von ca. 5 μm aufgetragen.Of the Photoresist is preferably applied with a thickness of about 5 microns.
Die in der Grabenstruktur galvanisch abgeschiedene Kupferschicht wird mit einer Dicke zwischen 3–5 μm aufgetragen.The in the trench structure is electrodeposited copper layer applied with a thickness between 3-5 microns.
In einer weiteren Ausgestaltung der Erfindung ist vorgesehen, dass die dielektrische Abdeckung zusätzlich photolithographisch zur Ausbildung von Bond-Pads strukturiert wird, so dass eine weitere Kontaktierung mit Drahtbrücken möglich wird.In A further embodiment of the invention provides that the dielectric cover in addition photolithographically structured to form bond pads, so that a further contact with wire bridges is possible.
Die Erfindung soll nachfolgend an einem Ausführungsbeispiel näher erläutert werden. In den zugehörigen Zeichnungen zeigen:The Invention will be explained in more detail below using an exemplary embodiment. In the associated Drawings show:
Zur
Herstellung einer erfindungsgemäßen dünnwandigen
RDL
Da
für das
galvanische Abscheiden von Kupfer eine Seed Layer
Danach
wird ebenfalls über
die gesamte Oberfläche
ein Photoresist
Der Vorteil ist, dass durch die dünne Photoresistschicht eine kürzere Prozesszeit, insbesondere eine kürzere Entwicklungszeit erreicht wird.Of the Advantage is that through the thin Photoresist layer a shorter one Process time, especially a shorter one Development time is reached.
Damit
ist die Seed Layer
Der
Photoresist
Zum
Schutz der RDL
Es versteht sich, dass die in dieser Beschreibung enthaltenen Maßangaben nur als Beispiele zu verstehen sind und dass im Einzelfall auch andere Dimensionierungen vorgenommen werden können, ohne den Gegenstand der Erfindung zu verlassen. Weiterhin kann die erfindungsgemäße RDL in allen Fällen eingesetzt werden, in denen eine Umverdrahtung auf einem Chip, einem Wafer, einem beliebigen Substrat, z.B. einem Interposer benötigt wird.It It is understood that the measurements contained in this description only as examples are to be understood and that in the individual case also other dimensions can be made without the subject matter of To leave invention. Furthermore, the inventive RDL in all cases be used in which a rewiring on a chip, a Wafer, any substrate, e.g. an interposer is needed.
Der
Rand
- 11
- Photoresistphotoresist
- 22
- Grabenstrukturgrave structure
- 33
- Kupfercopper
- 44
- Nickelnickel
- 55
- Goldgold
- 66
- RDLRDL
- 77
- Substrat/PE PolyimidSubstrate / PE polyimide
- 88th
- Dielektrikumdielectric
- 99
- Seed LayerSeed layer
- 1010
- Photoresistphotoresist
- 1111
- Randedge
- 1212
- Kupferschichtcopper layer
- 1313
- Abdeckungcover
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200510055402 DE102005055402A1 (en) | 2005-11-17 | 2005-11-17 | Producing wiring structure on wafer substrate for center row arrangement or wafer level packaging comprises sputtering of seed layer to form trench and application of copper layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200510055402 DE102005055402A1 (en) | 2005-11-17 | 2005-11-17 | Producing wiring structure on wafer substrate for center row arrangement or wafer level packaging comprises sputtering of seed layer to form trench and application of copper layer |
Publications (1)
Publication Number | Publication Date |
---|---|
DE102005055402A1 true DE102005055402A1 (en) | 2007-05-31 |
Family
ID=38037575
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE200510055402 Withdrawn DE102005055402A1 (en) | 2005-11-17 | 2005-11-17 | Producing wiring structure on wafer substrate for center row arrangement or wafer level packaging comprises sputtering of seed layer to form trench and application of copper layer |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE102005055402A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102008030725B4 (en) * | 2008-07-01 | 2013-10-17 | Deutsche Cell Gmbh | Process for producing a contact structure by means of a galvanic mask |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6492722B1 (en) * | 1998-06-04 | 2002-12-10 | Advanced Micro Devices, Inc. | Metallized interconnection structure |
WO2005013319A2 (en) * | 2003-07-31 | 2005-02-10 | Freescale Semiconductor, Inc. | Semiconductor device with strain relieving bump design |
-
2005
- 2005-11-17 DE DE200510055402 patent/DE102005055402A1/en not_active Withdrawn
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6492722B1 (en) * | 1998-06-04 | 2002-12-10 | Advanced Micro Devices, Inc. | Metallized interconnection structure |
WO2005013319A2 (en) * | 2003-07-31 | 2005-02-10 | Freescale Semiconductor, Inc. | Semiconductor device with strain relieving bump design |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102008030725B4 (en) * | 2008-07-01 | 2013-10-17 | Deutsche Cell Gmbh | Process for producing a contact structure by means of a galvanic mask |
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OP8 | Request for examination as to paragraph 44 patent law | ||
8127 | New person/name/address of the applicant |
Owner name: QIMONDA AG, 81739 MUENCHEN, DE |
|
8139 | Disposal/non-payment of the annual fee |