DE102005053740A1 - Getaktete NAND-Logik mit paralleler unidirektionaler Schaltungsanordnung - Google Patents

Getaktete NAND-Logik mit paralleler unidirektionaler Schaltungsanordnung Download PDF

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Publication number
DE102005053740A1
DE102005053740A1 DE200510053740 DE102005053740A DE102005053740A1 DE 102005053740 A1 DE102005053740 A1 DE 102005053740A1 DE 200510053740 DE200510053740 DE 200510053740 DE 102005053740 A DE102005053740 A DE 102005053740A DE 102005053740 A1 DE102005053740 A1 DE 102005053740A1
Authority
DE
Germany
Prior art keywords
logic units
inputs
opened
closed
clock pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE200510053740
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English (en)
Inventor
Georg Bedenk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to DE200510053740 priority Critical patent/DE102005053740A1/de
Priority to DE202005020771U priority patent/DE202005020771U1/de
Publication of DE102005053740A1 publication Critical patent/DE102005053740A1/de
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/084—Diode-transistor logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

Die getaktete NAND-Logik erreicht durch eine parallelgeschaltete unidirektionale Schaltungsanordnung einen niedrigeren Gesamtwiderstand und dadurch eine hohe Schaltgeschwindigkeit und durch die Taktung einen niedrigen Energieverbrauch.
DE200510053740 2005-11-10 2005-11-10 Getaktete NAND-Logik mit paralleler unidirektionaler Schaltungsanordnung Ceased DE102005053740A1 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE200510053740 DE102005053740A1 (de) 2005-11-10 2005-11-10 Getaktete NAND-Logik mit paralleler unidirektionaler Schaltungsanordnung
DE202005020771U DE202005020771U1 (de) 2005-11-10 2005-11-10 Getaktete NAND-Logik mit paralleler unidirektionaler Schaltungsanordnung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE200510053740 DE102005053740A1 (de) 2005-11-10 2005-11-10 Getaktete NAND-Logik mit paralleler unidirektionaler Schaltungsanordnung

Publications (1)

Publication Number Publication Date
DE102005053740A1 true DE102005053740A1 (de) 2007-05-16

Family

ID=37982597

Family Applications (1)

Application Number Title Priority Date Filing Date
DE200510053740 Ceased DE102005053740A1 (de) 2005-11-10 2005-11-10 Getaktete NAND-Logik mit paralleler unidirektionaler Schaltungsanordnung

Country Status (1)

Country Link
DE (1) DE102005053740A1 (de)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1309090A (en) * 1969-12-02 1973-03-07 Marconi Co Ltd Logic gating circuits
US4044270A (en) * 1976-06-21 1977-08-23 Rockwell International Corporation Dynamic logic gate
US6433389B1 (en) * 2000-06-09 2002-08-13 Advanced Micro Devices, Inc. Silicon on insulator logic circuit utilizing diode switching elements
US6621305B2 (en) * 2001-08-03 2003-09-16 Hewlett-Packard Development Company, L.P. Partial swing low power CMOS logic circuits
EP1441442A1 (de) * 2003-01-21 2004-07-28 Hewlett-Packard Development Company, L.P. Logisches Gatter mit niedrigem Verbrauch

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1309090A (en) * 1969-12-02 1973-03-07 Marconi Co Ltd Logic gating circuits
US4044270A (en) * 1976-06-21 1977-08-23 Rockwell International Corporation Dynamic logic gate
US6433389B1 (en) * 2000-06-09 2002-08-13 Advanced Micro Devices, Inc. Silicon on insulator logic circuit utilizing diode switching elements
US6621305B2 (en) * 2001-08-03 2003-09-16 Hewlett-Packard Development Company, L.P. Partial swing low power CMOS logic circuits
EP1441442A1 (de) * 2003-01-21 2004-07-28 Hewlett-Packard Development Company, L.P. Logisches Gatter mit niedrigem Verbrauch

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ASIJA,S.P.: Four-phase logic is practical. In: Electronic Design, Dez. 1977, S.160-163 *

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8122 Nonbinding interest in granting licenses declared
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