DE102005037234A1 - Vorrichtung und Verfahren zur Speicherung von Daten und/oder Befehlen in einem Rechnersystem mit wenigstens zwei Ausführungseinheiten und wenigstens einem ersten Speicher oder Speicherbereich für Daten und/oder Befehle - Google Patents
Vorrichtung und Verfahren zur Speicherung von Daten und/oder Befehlen in einem Rechnersystem mit wenigstens zwei Ausführungseinheiten und wenigstens einem ersten Speicher oder Speicherbereich für Daten und/oder Befehle Download PDFInfo
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- DE102005037234A1 DE102005037234A1 DE102005037234A DE102005037234A DE102005037234A1 DE 102005037234 A1 DE102005037234 A1 DE 102005037234A1 DE 102005037234 A DE102005037234 A DE 102005037234A DE 102005037234 A DE102005037234 A DE 102005037234A DE 102005037234 A1 DE102005037234 A1 DE 102005037234A1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
- G06F11/1683—Temporal synchronisation or re-synchronisation of redundant processing components at instruction level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/845—Systems in which the redundancy can be transformed in increased performance
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Quality & Reliability (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102005037234A DE102005037234A1 (de) | 2005-08-08 | 2005-08-08 | Vorrichtung und Verfahren zur Speicherung von Daten und/oder Befehlen in einem Rechnersystem mit wenigstens zwei Ausführungseinheiten und wenigstens einem ersten Speicher oder Speicherbereich für Daten und/oder Befehle |
KR1020087002749A KR20080033338A (ko) | 2005-08-08 | 2006-07-24 | 데이터 및/또는 명령을 위한 적어도 2개의 실행 유닛들과적어도 하나의 제1 메모리 또는 메모리 영역을 갖는 컴퓨터시스템에 데이터 및/또는 명령을 저장하기 위한 장치 및방법 |
PCT/EP2006/064588 WO2007017367A1 (fr) | 2005-08-08 | 2006-07-24 | Dispositif et procede pour enregistrer des donnees et/ou des ordres dans un systeme informatique comprenant au moins deux unites d'execution et au moins une premiere memoire ou zone memoire destinee a des donnees et/ou des ordres |
CNA2006800294352A CN101243404A (zh) | 2005-08-08 | 2006-07-24 | 用于在具有至少两个处理单元和用于数据和/或指令的至少一个第一存储器或存储器区域的计算机系统中存储数据和/或指令的设备和方法 |
JP2008525516A JP2009505178A (ja) | 2005-08-08 | 2006-07-24 | 少なくとも2つの命令実行部と少なくともデータ及び/または命令のための第1記憶装置または記憶領域とを備えたコンピュータシステムにおいて、データ及び/または命令を格納する装置及び方法 |
EP06777936A EP1915684A1 (fr) | 2005-08-08 | 2006-07-24 | Dispositif et procede pour enregistrer des donnees et/ou des ordres dans un systeme informatique comprenant au moins deux unites d'execution et au moins une premiere memoire ou zone memoire destinee a des donnees et/ou des ordres |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102005037234A DE102005037234A1 (de) | 2005-08-08 | 2005-08-08 | Vorrichtung und Verfahren zur Speicherung von Daten und/oder Befehlen in einem Rechnersystem mit wenigstens zwei Ausführungseinheiten und wenigstens einem ersten Speicher oder Speicherbereich für Daten und/oder Befehle |
Publications (1)
Publication Number | Publication Date |
---|---|
DE102005037234A1 true DE102005037234A1 (de) | 2007-02-15 |
Family
ID=36926336
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE102005037234A Withdrawn DE102005037234A1 (de) | 2005-08-08 | 2005-08-08 | Vorrichtung und Verfahren zur Speicherung von Daten und/oder Befehlen in einem Rechnersystem mit wenigstens zwei Ausführungseinheiten und wenigstens einem ersten Speicher oder Speicherbereich für Daten und/oder Befehle |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1915684A1 (fr) |
JP (1) | JP2009505178A (fr) |
KR (1) | KR20080033338A (fr) |
CN (1) | CN101243404A (fr) |
DE (1) | DE102005037234A1 (fr) |
WO (1) | WO2007017367A1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102073565B (zh) * | 2010-12-31 | 2014-02-19 | 华为技术有限公司 | 触发操作方法、多核分组调试方法、装置及系统 |
KR101432274B1 (ko) | 2013-12-12 | 2014-08-21 | (주)이건산전 | 백업모듈을 포함하는 철도 차량용 제어기 |
CN112416609A (zh) * | 2021-01-22 | 2021-02-26 | 南京芯驰半导体科技有限公司 | 双核模式的模式配置方法及装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4823256A (en) * | 1984-06-22 | 1989-04-18 | American Telephone And Telegraph Company, At&T Bell Laboratories | Reconfigurable dual processor system |
EP0439952A3 (en) * | 1990-01-31 | 1992-09-09 | Sgs-Thomson Microelectronics, Inc. | Dual-port cache tag memory |
JPH05128080A (ja) * | 1991-10-14 | 1993-05-25 | Mitsubishi Electric Corp | 情報処理装置 |
US5751932A (en) * | 1992-12-17 | 1998-05-12 | Tandem Computers Incorporated | Fail-fast, fail-functional, fault-tolerant multiprocessor system |
CA2178440A1 (fr) * | 1995-06-07 | 1996-12-08 | Robert W. Horst | Systeme multiprocesseur insensible aux defaillances |
US6615366B1 (en) * | 1999-12-21 | 2003-09-02 | Intel Corporation | Microprocessor with dual execution core operable in high reliability mode |
US6772368B2 (en) * | 2000-12-11 | 2004-08-03 | International Business Machines Corporation | Multiprocessor with pair-wise high reliability mode, and method therefore |
DE10136335B4 (de) * | 2001-07-26 | 2007-03-22 | Infineon Technologies Ag | Prozessor mit mehreren Rechenwerken |
US7055060B2 (en) * | 2002-12-19 | 2006-05-30 | Intel Corporation | On-die mechanism for high-reliability processor |
-
2005
- 2005-08-08 DE DE102005037234A patent/DE102005037234A1/de not_active Withdrawn
-
2006
- 2006-07-24 EP EP06777936A patent/EP1915684A1/fr not_active Withdrawn
- 2006-07-24 CN CNA2006800294352A patent/CN101243404A/zh active Pending
- 2006-07-24 KR KR1020087002749A patent/KR20080033338A/ko not_active Application Discontinuation
- 2006-07-24 JP JP2008525516A patent/JP2009505178A/ja active Pending
- 2006-07-24 WO PCT/EP2006/064588 patent/WO2007017367A1/fr active Application Filing
Also Published As
Publication number | Publication date |
---|---|
EP1915684A1 (fr) | 2008-04-30 |
CN101243404A (zh) | 2008-08-13 |
WO2007017367A1 (fr) | 2007-02-15 |
KR20080033338A (ko) | 2008-04-16 |
JP2009505178A (ja) | 2009-02-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |
Effective date: 20110301 |