DE102005034387A1 - Trench DRAM semiconductor memory has additional p-type anti-punch zone in semiconductor under neighboring strips of shallow trench isolation - Google Patents

Abstract

A trench DRAM semiconductor memory comprises a cell field (1) with parallel strips (2) of memory cells mutually insulated by shallow trench isolation (19) with neighboring cells along a strip also mutually isolated. A p-trench zone (11) in a semiconductor body (10) has an n-channel transistor per cell with source/drain connections to a bitline and through a buried strip to an electrode of a trench memory capacitor. A p-type anti-punch zone (23') lies in the trench beneath the bitline. An independent claim is also included for the production of an anti-punch zone for the above.

Description

The The invention relates to a Trench DRAM semiconductor memory with reduced leakage current and a method of fabricating anti-punch zones for reducing leakage in a trench DRAM semiconductor memory.

DRAMs (Dynamic Random Access Memory, Random Access Memory) have a cell array in which DRAM memory cells for storage one determining a data content of the respective memory cell electric charge are arranged. There is also a support area or support area, which in particular components for electronic circuits contains for controlling individual memory cells. The support area points in particular p-channel and n-channel MOSFETs (Metal oxide semiconductor field effect transistors).

The DRAM memory cells each include a storage capacitor for Storage of the electrical charge and a selection transistor, with the one connection of a storage electrode of the storage capacitor with a data line for writing or reading charge on the storage capacitor can be produced. The storage capacitors are either designed as stack or trench capacitors. trench capacitors are from a substrate surface introduced into a semiconductor substrate while stack capacitors above the substrate surface are provided in a wiring area of the DRAM. The selection transistors are as field effect transistors in an active area with one each Source and drain region formed, which through a channel region spaced apart from each other. Active areas of adjacent storage cells for example, via a Shallow trench isolation structure electrically isolated from each other. Above the channel region is one spaced apart by a gate dielectric Gate electrode provided over their potential a conductivity of the channel area can be set by field effect. Consequently let yourself a conductive Connection between source and drain for writing or reading Make charges of the storage capacitor. Will the gate electrode held at a potential, so that no conductive channel area forms, the charge is held on the storage capacitor and flows only by leakage currents over time. To the state of charge on the storage capacitors as long as possible to keep up and thus to achieve a possible huge Retention Time it is necessary to reduce the leakage currents.

It It is known to have an antipunch zone via a bit line contact hole in the implant active region, whereby in particular a sub-threshold current, hereinafter referred to as deep sub Vt Leakage current referred to be reduced between source and drain should. In a buried-strap trench DRAM cell array, in which memory cells through a shallow-trench isolation structure are electrically isolated from each other, however, other species occur of leakage currents on. One of these leakage current contributions is hereinafter referred to as sub-STI leakage current and corresponds a parasitic MOS current, wherein source and drain of this parasitic MOS transistor by a Buried strap region of n conductivity type a first memory cell and an n-type conductivity semiconductor region below a bit line contact one through the shallow trench isolation structure adjacent memory cell is formed. The threshold voltage this parasitic MOS transistor is essentially determined by the thickness of the shallow trench isolation structure as well as by a potential above the shallow-trench isolation structure, which, for example, over about that lying metal lines is defined determines. Beside this Sub-STI leakage occurs in the buried strap trench DRAM semiconductor memory arranged along strips and through a shallow-trench isolation structure one another so-called self-gated sub-Vt Leakage on. This is a leakage current between along a strip adjacent memory cells between a Bit line contact of one memory cell and the buried strap of the other Memory cell occurs, wherein the one and the other memory cell isolated from each other by a trench. In a known manner these two leakage currents by applying a negative potential to the p-well of the n-channel Selection transistor is reduced, but with the disadvantage of increased junction leakage between the buried strap and the p-tub due to the then overlying this transition higher Blocking voltage brings with it. Likewise, there is the implantation mentioned above the antipunch zone over the bit line contact hole due to misalignments the danger that the implanted region is reduced in the active silicon and / or the implantation takes place partially on the trench top oxide, so that the implantation rather than complete directed into the active area, partially directed into the oxide is. As a result, an increase in the self-gating sub-Vt Leakage result.

The invention is based on the object ei To provide a reduced leak current Trench DRAM semiconductor memory and a method for producing anti-punch zones for reducing the leakage current in the trench DRAM semiconductor memory, so that the above-described problems are avoided.

The The object is achieved by a trench DRAM semiconductor memory with reduced leakage current according to the claim 1 as well as by a method for making anti-punch zones for decreasing the leakage current in the trench DRAM semiconductor memory according to claim 4 solved. Preferred embodiments are the subject of the dependent Claims.

According to the invention, a trench DRAM semiconductor memory with reduced leakage current provided with in a cell array arranged substantially along parallel strips Memory cells created by a shallow-trench isolation structure are electrically insulated from each other, wherein the shallow-trench isolation structure both adjacent to a strip adjacent memory cells as well Memory cells of adjacent strips electrically isolated from each other, one formed in a well zone of the p-type conductivity in the semiconductor body n-channel select transistor per memory cell, which is accessed by one of two as source and drain in the well zone formed semiconductor zones of the n-type conductivity over a Bit line contact with a bit line and through the other of the two semiconductor zones over a buried strap area with an electrode of a trench storage capacitor is conductively connected, one in the well zone in an area below the bit line contact embedded anti-punch zone from p-type conductivity and one in the semiconductor body below the part running between adjacent strips the shallow-trench isolation structure formed further anti-punch zone of the p-conductivity type. The further antipunch zone leads in particular to increase a threshold voltage of a parasitic MOS transistor whose Source and drain area through a buried strap area of a strip and an n-type conductivity semiconductor region below the bit line contact an adjacent strip are formed. As a gate dielectric this parasitic MOS transistor The shallow trench isolation structure acts between the adjacent ones Strips. Thus, the further anti-punch zone is used in particular for Reduction of self-gating sub-VT Leakage current.

at an advantageous embodiment is correct a doping element for adjusting the p-type conductivity of the anti-punch zone with the doping element the other anti-punch zone match. Ideally, the two anti-pound zones are in one common Implantation step formed. For example, the p-conductivity type becomes by implanting a trivalent element such as boron or indium established.

at a further preferred embodiment is a dopant concentration in the further antipunch zone greater than in the tub zone. This leaves an increase the threshold voltage of the parasitic MOS transistor between through the shallow trench isolation structure achieve adjacent memory cells.

In a method according to the invention for producing anti-punch zones for reducing the leakage current in a trench DRAM semiconductor memory, a semiconductor substrate is provided with trenches for arrays of memory cells to be formed, at least in a semiconductor body substantially along parallel strips, an open area for a shallow trench isolation structure electrically insulating the memory cells with each other, wherein the shallow trench isolation structure electrically isolates adjacent memory cells as well as memory cells of adjacent strips from one another, a sidewall region exposed within the trenches adjacent to a p-type well region of an active region of the memory cell, wherein above the region of the active region which adjoins the side wall region, in subsequent steps, a bit line contact of an n-channel selection transistor to be formed is provided is seen and implant dopants in the semiconductor body along a tilted surface normal to the semiconductor body direction to form p-type anti-punch zones in the semiconductor body such that the Do animal substances through the exposed sidewall region in the active region in the semiconductor body and also in the Semiconductor body region are introduced below that portion of the shallow trench isolation structure, the memory cells of adjacent strips electrically isolated from each other. The semiconductor body is preferably formed of silicon and is present as a semiconductor wafer. In addition, however, this may also be formed of other semiconductor materials such as germanium or silicon germanium. The dopants implanted through the exposed sidewall region serve, in particular, to reduce the deep-sub-Vt leakage current and thus define an antipunch zone below the bit line contact to be formed in subsequent steps. In order to reduce the further leakage currents, ie the sub-STI leakage current and the self-gating sub-Vt leakage current, the dopants introduced below the shallow-trench isolation structure between adjacent memory cells serve. These lead to an increase in the threshold voltage of the respective parasitic MOS transistor. A misalignment of the thus implanted anti-punch zones with respect to an active area of the memory cells is excluded, since the implantation does not take place affected by misalignment contact holes.

at an advantageous embodiment the implantation takes place at an implantation angle of at least 5 ° relative to the surface normal. This ensures that dopants through the exposed Sidewall area in the active area to form a particular implanted the deep-sub-VT leakage current reducing antipunch zone become. The implantation angle is in this case by several parameters such as the minimum structural dimensions as well as the Implantation energy determined. Thus, the efficiency can be reduced of deep-sub-VT leakage currents on the one hand and sub-STI and self-gating sub-VT leakage currents, on the other hand, by changing the Implantation angle can be set separately.

at In a further advantageous embodiment, the dopants are over several Implantation steps introduced, wherein the implantation steps at least regarding one of the parameters implantation energy, implantation angle, implantation dose and implanted dopant differ from each other. Several Enable implantation steps an optimization of the anti-punch zones below the bit line contacts on the one hand and below the shallow trench isolation structure between adjacent ones Stripes on the other hand. Thus, you can the anti-punch zones targeted for optimal reduction be optimized of each influenceable leakage.

at In a further advantageous embodiment, the active Area of the memory cells covered with an implantation protection mask. Thus, the dopants become along a stripe with memory cells only about introduced the exposed sidewall area in the active area.

at In another advantageous embodiment, the implantation follows after oxidation of the active area. Consequently, the thermal budget can while the oxidation of the active area not to activate the implanted Dopants are used.

at an alternative embodiment the implantation takes place before an oxidation of the active area. In this case, the thermal budget during the oxidation for activation the dopants are used.

The Invention and in particular certain features, aspects and advantages The invention will be described with reference to the following de detailed description in Connection with the attached Drawings clarified. Show it:

1 in Part A, a schematic cross-sectional view of a buried-strap trench DRAM cell array in a simplified representation and in Part B an assignment of leakage current paths to the cell array;

2 a schematic cross-sectional view of a trench DRAM semiconductor memory in the implantation of an anti-punch zone according to a known method;

3 in Part A is a plan view of a cell array of the trench DRRM semiconductor memory and in Part B is a cross-sectional view of the semiconductor memory immediately prior to implantation of anti-punch zones according to an embodiment of the invention;

4 in Part A, a schematic cross-sectional view of a cell field strip and in Part B a plan view of the cell array with oblique implantation of the dopants according to an embodiment of the invention; and

5 a schematic three-dimensional view of a cell array with introduced anti-punch zones according to an embodiment of the invention.

1A is a schematic view on a cell field 1 a buried-strap trench DRAM semiconductor memory. Along the strip 2 of the cell field 1 Memory cells are arranged, with a surface area 3 a memory cell is schematically indicated. The Stripes 2 of the cell field 1 become over isolation areas 4 electrically isolated from each other. To better illustrate the leakage currents explained below are the isolation areas 4 between the strip 2 of the cell field 1 only shown as a recess. The isolation areas 4 are realized as a shallow-trench isolation structure. To explain the leakage currents relevant parts of adjacent memory cells are highlighted. These are bit line contacts 5a . 5b . 5c . 5c adjacent storage cells, deep trenches 6a . 6b . 6c . 6d adjacent memory cells, buried straps of adjacent memory cells 7a . 7b . 7c . 7d , as well as a gate electrode 8th in the surface area of the designated memory cell 3 , Within the designated memory cell 3 flows between the buried strap 7a and the bit line contact 5b a deep sub Vt leakage current indicated by an arrow 9a , Likewise flows between the Bu ried-Strap 7d another memory cell and the bit line contact 5b the designated memory cell 3 a sub-STI leakage current indicated by an arrow 9b , A self-gated sub-Vt leakage current indicated by another arrow 9c flows between the buried strap 7d the further memory cell and a bit line contact 5d a different memory cell. It should be noted that the respective leakage currents marked by an arrow flow both between further of the marked areas and within further memory cells (not shown). For example, a self-gating sub-Vt leakage current also flows between each of the buried straps 7a . 7b and 7c and the associated respective bit line contact 5a . 5b such as 5c , A similar consideration applies to the sub-STI leakage current. 1B serves to illustrate the in 1A only incompletely marked leakage currents. Starting from the designated memory cell 3 in 1a the already mentioned deep sub VT leakage current flows between the bit line contact 7a and the buried strap 5b , A sub-STI leakage current flows from the designated memory cell 3 both to the bit line contact 5c a memory cell in a first adjacent strip as well as to the bit line contact 5d another memory cell in a second adjacent strip. In addition, a self-gating sub-VT leakage current flows from the buried strap 7a the designated memory cell 3 in the adjacent bit line contact 5a a memory cell of the same strip. The just with regard to the designated memory cell 3 described leakage currents are also based on the adjacent memory cells, but for the sake of simplicity, due to the limited number of bit line contacts shown, deep trench and buried straps is not recognizable.

2 shows schematic cross-sectional views of a buried-strap trench DRAM semiconductor memory both along a strip of the cell array (left part of the figure) and perpendicular thereto (right part of the figure). The figure serves to illustrate the formation of an antipunch zone according to a known method. Here are the deep trenches 6 adjacent memory cells only incomplete in the depth of a semiconductor body 10 , in particular only within a p-type well zone 11 shown. Inside the trenches 6 to the p-type well region 11 adjacent is a dielectric 12 which enters the interior of the Trenches 6 to an electrode 13 borders. The electrode 13 sits down in the depths of the trenches 6 and adjoins there to a capacitance dielectric (not shown). The electrode 13 is with a part of the top each with the buried strap 7 connected, as well as with an insulating trench top oxide 14 which isolates adjacent memory cells and additionally within the respective trenches to the surface 15 of the semiconductor body 10 borders. Above the to the trench top oxide 14 in the figure right side adjacent area of the tub zone 11 p conductivity type are bit line contact holes 16 educated. To create an area 18 with antipunch zone and bit line contact pad zone, implantations of dopants labeled as arrow, such as boron for the antipunch zone and arsenic for the bit line contact pad zone, are performed correspondingly. It should be noted that when doping the anti-punch zone and in particular depending on the adjustment of the contact holes provided for the anti-punch zone dopants in the trench top oxide 14 land and thus do not contribute to the leakage current reduction. In the right part of the figure, a schematic cross-sectional view is shown perpendicular to the strips of the cell array. The two neighboring trenches 6 thus correspond to trenches overcoming neighboring strips, with in the intermediate well zone 11 of p conductivity type, a memory cell is formed in a stripe therebetween. A shallow-low trench isolation structure 19 serves the electrical isolation of adjacent strips.

In 3A is a schematic plan view of a cell field 1 with associated strip 2 of the cell field 1 in the generation of anti-punch zones for leakage reduction according to an embodiment of the invention. The cell field 1 is on both sides of a cell field edge area 20 completed. With AB and CD are marked lines of intersection along which the cross-sectional views shown in part of Figure B. In the left partial image in subfigure B, the cross sectional view is related to the section line AB from subfigure A and shows adjacent trenches along a strip 6 The between neighboring trenches 6 lying tub zone 11 of p conductivity type is on the surface 15 the semiconductor body with a protective layer 21 covered like a SiN liner. This protective layer 21 protects the well zone serving to form a selection transistor 11 of the p-conductivity type, to be added with undesired implanted dopants during the subsequent production of the anti-punch zones for reducing the leakage current. It should be noted that the protective layer 21 above the trenches 6 is open and part of the originally filled trenches 6 was removed to expose one to the surface 15 of the semiconductor body adjacent sidewall region 22 within the trenches 6 , This sidewall area 22 is adjacent to that region of the active region above which a bit line contact of an n-channel selection transistor to be formed is provided in subsequent steps.

In the right part of the figure (in 3B ) is a schematic cross-sectional view along the section line CD 3A to illustrate a cross-sectional view perpendicular to the strips 2 of the cell field 1 shown. The trenches shown 6 form neighboring trenches, with one strip in between. In addition to the opening of the protective layer 21 are also parts of the tub zone 11 of the p-conductivity type as well as a filling of the trenches 6 , about the electrode 13 , removed to form a shallow-low trench isolation structure. Thus, immediately prior to implantation of the anti-punch zones for leakage current reduction according to an embodiment of the invention, both over the exposed sidewall region 22 inside the trenches parts of the tub zone 11 p-type conductivity as well as the open area for the shallow trench isolation structure adjacent other parts of the well zone 11 free from the p-conductivity type.

In 4A Figure 4 is a view, taken from a scanning electron microscope (SEM) cross-sectional view, taken along a strip in the cell array during implantation for producing anti-punch zones for leakage current reduction in accordance with an embodiment of the invention. The implantation takes place here by an implantation angle α with respect to a vertical of the surface 15 of the semiconductor body 10 tilted. The implantation is directed so that these dopants to form the anti-punch zones through the exposed sidewall area 22 in the tub zone 11 penetrate in the p-conductivity type. Above a trained here implanted area 23 ' a bit line contact is set in subsequent process steps. The protective layer 21 holds in another area 23 '' Dopants off, over the surface 15 of the semiconductor body in that region of the well zone 11 Penetrate p-type conductivity, which serves the later formation of the selection transistor.

4B shows a schematic plan view of the cell array 1 With stripes 2 which are spaced by a shallow trench isolation structure to be subsequently formed. The implanted areas 23 ' go to the in 4A shown implantation through the exposed sidewall area 22 back. The one between the strips 2 consistently implanted area 23 ''' represents another anti-punch semiconductor zone within those regions of the p-type conductivity semiconductor region that have been opened to form the shallow-trench isolation structure (see also 3b , right part illustration). The implanted area 23 ' Specifically, it serves to reduce deep-sub-Vt leakage current during the implanted region 23 ''' especially suitable for reducing the sub-STI as well as the self-gating sub-Vt leakage current. It should be noted that the implanted areas 23 ' such as 23 ''' can be produced with the help of one or more implantation steps.

In 5 is a schematic 3D view shown to illustrate the according to 4A and B implanted areas 23 ' and 23 ''' , It is a to 1A identical section of the cell field 1 shown. Below the bit line contacts 5a . 5b . 5c . 5d lies the implanted area 23 ' which forms an anti-punch zone for reducing, in particular, the deep-sub-Vt leakage current. To the semiconductor body 10 below the isolation area 4 between adjacent strips 2 of the cell field 1 , ie below the shallow-trench isolation structure to be formed later, is the implanted region 23 ''' , which in particular the reduction of the sub-STI leakage current as well as the self-gating sub-Vt leakage current (see also 1A ) serves.

1

cell array

2

strip of the cell field

3

surface area a designated memory cell

4

isolation region between strips of the cell field

5, 5a, 5b, 5c, 5d

bit line contact, Bit line contacts of adjacent memory cells

6 6a, 6b, 6c, 6d

trench, Trenches of adjacent storage cells

7, 7a, 7b, 7c, 7d

Buried strap, Buried straps of adjacent memory cells

8th

gate electrode

9a 9b, 9c

Deep sub-Vt Leakage current, sub-STI leakage current, self-gating sub-Vt leakage current

10

Semiconductor body

11

well region of the p-conductivity type

12

dielectric

13

electrode

14

Top oxide

15

Surface of the Semiconductor body

16

bit line contact

17

insulation and wiring area

18

area with anti-punch zone and bit line contact connection zone

19

Shallow trench isolation structure

20

Cell array edge area

21

protective layer

22

exposed Sidewall region

23 ', 23' ', 23' ''

implanted Areas for Anti Punch Zones

α

implantation angle

Claims (9)

Trench DRAM semiconductor memory with: - in a cell array ( 1 ) substantially along parallel strips ( 2 ) arranged memory cells, which by a shallow trench isolation structure ( 19 ) are electrically isolated from each other, wherein the shallow trench isolation structure ( 19 ) both along a strip ( 2 ) adjacent memory cells as well as memory cells of adjacent strips ( 2 ) isolated from each other; - one in a bathing zone ( 11 ) of the p-conductivity type in the semiconductor body ( 10 ) formed n-channel select transistor per memory cell, which by one of two as the source and drain in the well zone ( 11 ) n-type conductivity type semiconductor regions via a bit line contact with a bit line and through the other of the two semiconductor regions via a buried strap region (US Pat. 7 ) with an electrode ( 13 ) of a trench storage capacitor is conductively connected; - one in the tub zone ( 11 ) in an area below the bit line contact embedded anti-punch zone ( 23 ' ) of the p-conductivity type, characterized in that in the semiconductor body ( 10 ) below that between adjacent strips ( 2 ) extending portion of the shallow trench isolation structure ( 19 ) another antipunch zone ( 23 ''' ) is formed by the p-type conductivity. DRAM semiconductor memory according to claim 1, characterized in that a doping element for adjusting the p-type conductivity of the antipunch zone ( 23 ' ) with the doping element of the further antipunch zone ( 23 ''' ) matches. DRAM semiconductor according to claim 1 or 2, characterized in that a dopant concentration in the further anti-punch zone ( 23 ''' ) is larger than in the bath zone ( 11 ). Method for producing anti-punch zones ( 23 ' . 23 ''' ) for reducing the leakage current in a trench DRAM semiconductor memory, comprising: - providing a semiconductor substrate having at least: - in a semiconductor body ( 10 ) substantially along parallel strips ( 2 ) arranged trenches ( 6 ) for trainee memory cells; An opened region in the semiconductor body ( 10 ) for a shallow trench isolation structure ( 19 ) for the electrical isolation of the memory cells with each other, wherein the shallow trench isolation structure ( 19 ) along a strip ( 2 ) adjacent memory cells as well as memory cells of adjacent strips ( 2 ) isolated from each other; - one within the trenches ( 6 ) exposed sidewall area ( 22 ), which leads to a bathtub zone ( 11 ) is adjacent to the p-type conductivity of an active area of the memory cell, wherein above that area of the active area adjacent to the sidewall area ( 22 ), in subsequent steps a bit line contact of a trainee n-channel select transistor is provided; and implanting dopants into the semiconductor body ( 10 ) along one of the surface normal of the semiconductor body ( 10 ) tilted direction to form anti-punch zones ( 23 ' . 23 ''' ) of the p-conductivity type in the semiconductor body ( 10 ) such that the dopants through the exposed sidewall region ( 22 ) in the active region in the semiconductor body ( 10 ) and also in the semiconductor body region below the open area for the shallow trench isolation structure ( 19 ), the memory cells of adjacent strips ( 2 ) electrically isolated from each other, are introduced. Method according to claim 4, characterized in that that the implantation at an implantation angle of at least 5 ° relative to the surface normal he follows. Method according to one of claims 4 or 5, characterized that the dopants over several Implantation steps are introduced, wherein the implantation steps at least regarding one or more of the parameters implantation energy, Implantation angle (α), implantation dose and implanted dopant differ from each other. Method according to one of claims 4 to 6, characterized in that the active region of the memory cells with an implantation protective mask ( 21 ) is covered. Method according to one of claims 4 to 7, characterized that the implantation takes place after an oxidation of the active area. Method according to one of claims 3 to 6, characterized that the implantation takes place before an oxidation of the active area.