DE102005027459B4 - A manufacturing method for a semiconductor structure having a plurality of overfilled isolation trenches - Google Patents

Abstract

A manufacturing method for a semiconductor structure having a plurality of overfilled isolation trenches (5a, 5b), comprising the steps of:
Providing a semiconductor substrate (1);
Forming a first intermediate layer (2) on the upper side (O) of the semiconductor substrate (1);
Forming a sacrificial layer (3) or a plurality of sacrificial layers (3) on the first intermediate layer (2);
Etching a plurality of insulation trenches (5a, 5b) extending into the semiconductor substrate (1) by means of a mask provided on the one sacrificial layer (3) or the plurality of sacrificial layers (3);
Removing the mask to expose the sacrificial layer (3) or the plurality of sacrificial layers (3) remaining after the etching;
Forming an insulating second intermediate layer (6; 6 ') on the trench walls;
Filling the plurality of isolation trenches (5a, 5b) with an insulating filling (10) that extends to the top of the one sacrificial layer (3) or the plurality of sacrificial layers (3);
selective sinking of the filling (10) with respect to the one sacrificial layer ...

Description

The The present invention relates to a manufacturing method for a semiconductor structure with a plurality of protruding filled Isolation trenches.

The US Pat. No. 6,784,077 B1 describes a method for producing a shallow trench isolation (STI). On a semiconductor substrate, a silicon nitride layer is deposited. A trench is etched into the semiconductor substrate through the silicon nitride layer, a silicon dioxide layer is grown thermally in the trench, the trench is filled with silicon oxide by a CVD, the silicon nitride layer is removed and the O-xidliner layer is etched away with a BHF solution at an upper edge.

The US 2004-0048443 A1 describes a method for producing a shallow trench isolation in a semiconductor substrate. On the substrate, a silicon nitride layer is deposited, through which a trench is etched into the semiconductor substrate. The trench is filled with silicon oxide by a chemical deposition process. Finally, the silicon nitride layer is removed. The US 20030124813 A1 and the US Pat. No. 6,319,794 B1 describe further methods for producing shallow trench isolation structures with overhanging fillings.

From the US Pat. No. 6,413,836 B1 For example, there is known a method of forming a semiconductor structure having a plurality of overfilled isolation trenches, wherein selectively sinking the semiconductor substrate in the periphery of the filled trenches is performed to provide a predetermined projection of the filled trenches to the periphery.

From the GB 2 404 283 A For example, a vertical field effect transistor with a dual channel structure that is in contact with an STI trench is known. Sidewall spacers made of silicon nitride are formed along the trench walls of the STI trenches.

Even though in principle be applicable to any integrated circuits the present invention and its underlying problem in relating to memory cell semiconductor structures with a plurality of protruding filled STI (shallow trench isolation) trenches in silicon technology explained.

Become STI trenches in semiconductor structures for isolation of active areas needed, for example for isolation of active cell areas in memory cell arrays. It is necessary that the filled with a dielectric STI trenches a preferably have slight variation in the STI step height, which essentially as a result of a chemical-mechanical Polishing process is set forth below. Under step height is the height, around the filling dielectric over the Semiconductor substrate survives.

One particular problem in this context is that STI trenches of future technologies ever larger aspect ratios (ratio depth / width) have, which from a certain aspect ratio with currently applied Procedures are no longer voider fillable.

4A -D show schematic representations of successive process stages of a production method for a semiconductor structure with a plurality of overfilled trenches to illustrate the problem underlying the invention.

In 4A denotes reference numeral 1 a silicon semiconductor substrate, on the top O a hard mask 50 made of silicon nitride is applied. By means of the hard mask 50 be in the silicon semiconductor substrate 1 isolation trenches 3a . 3b . 3c etched in a per se known reactive ion etching process.

In a subsequent process step, which in 4B is then above the semiconductor substrate 1 with the isolation trenches 3a . 3b . 3c an insulation oxide 10 deposited, which is the isolation trenches 3a . 3b . 3c and their periphery completely covered.

As in 4C shown, then takes place a chemical-mechanical polishing process, in which with a little selective Polierschlemme in the silicon nitride of the hard mask 50 is polished, which thereby receives a modified, at least partially sunken top KA with varying thickness. Since the polishing process is susceptible to feature size variations within the chip, pre-process variations, and polishing process variations, the variations are significant. In this context, it should be mentioned that the thickness of the nitride layer can already vary in any case beforehand because of the deposition process used for its production.

This top KA defines the final height of the supernatants of the filling 10 the isolation trenches over the top O of the semiconductor substrate 1 , Thus, the requirements for the homogeneity of the step heights can not be met.

This is going out 4D clearly, in the state after removing the hard mask 50 is shown made of silicon nitride. Removing the hard mask 50 Of silicon nitride is usually carried out in a wet chemical process, which on the top OF of the semiconductor substrate 1 due to its selectivity stops. Clearly recognizable are a number of different step heights or protrusions ST1 to ST6.

As an alternative to said polishing process, a stop-polishing process has recently been used which is hard on the silicon nitride of the hard mask 50 stops. Also in this improved process, the accuracy of the stopping and the homogeneity of the thickness of the silicon nitride layer for the hardmask determine 50 the homogeneity of the STI step heights.

moreover there are problems with parasitic Corner-devices of different threshold voltages, which adhere to form the corners of the steps of different step heights or overhangs of the STI trenches, where in a later Process stage of gate dielectric material and gate material on the Substrate are deposited.

The The problem underlying the present invention is Therefore, therein, an improved manufacturing method for a semiconductor structure with a plurality of protruding to create filled isolation trenches that makes it possible lower fluctuations of the final Step height and diminished corner-device issues.

According to the invention this problem by the production method specified in claim 1 solved.

The Advantages of the invention Manufacturing process are, in particular, that the final step heights and the adjacent corner devices with almost vanishing Set fluctuation range.

The The idea underlying the present invention is that that a selective sinking of the second intermediate layer to the grave walls by a predetermined height below the top of the semiconductor substrate, regardless of back polishing and selectively sinking the insulating filling.

In the dependent claims find advantageous developments and improvements of respective subject of the invention.

According to one preferred development is to form a parasitic corner device Forming a gate dielectric layer and an overlying one Gate connection layer in the gap and on the surrounding Top of the semiconductor substrate performed.

According to one Another preferred development is the semiconductor substrate made of silicon, the first intermediate layer of silicon oxide, the second Intermediate layer of silicon nitride and the insulating filling Silicon oxide.

According to one Another preferred development is to form a third Interlayer at the moat walls un ter the second intermediate layer in the region of the semiconductor substrate and selectively sinking the third intermediate layer to the grave walls at about the predetermined height below the top of the semiconductor substrate with respect to insulating filling, the first intermediate layer and the second intermediate layer for forming the gap between the insulating filling and the semiconductor substrate carried out.

According to one Another preferred development is the third intermediate layer made of silicon oxide.

According to one Another preferred development is the formation of the second Intermediate layer over the entire surface, wherein the parallel to the top extending portion of the second Interlayer another, formed after the etching of the isolation trenches Sacrificial layer forms.

According to one Another preferred development is a first and a second Sacrificial layer on the first intermediate layer before etching the isolation trenches educated.

According to one Another preferred development is the respective selective Sinking or selective removal in a dry or wet chemical etching process performed with appropriate selectivity.

According to one Another preferred development is the formation of the insulating Filling by Depositing the insulating filling and then back polishing the insulating filling in a chemical-mechanical polishing process.

embodiments The invention is illustrated in the drawings and in the following Description closer explained.

1A -G show schematic representations of successive process stages of a manufacturing method for a semiconductor structure with one of a plurality of overfilled isolation trenches as the first embodiment of the present invention;

2A -F show schematic representations of successive process stages of a manufacturing method for a semiconductor structure with one of a plurality of overfilled isolation trenches as a second embodiment of the present invention;

3 shows a schematic representation of a Verfahrensausgangsstadiums a manufacturing method for a semiconductor structure having a plurality of over-filled isolation trenches as a third embodiment of the present invention; and

4A -D show schematic representations of successive process stages of a production method for a semiconductor structure with a plurality of overfilled trenches to illustrate the problem underlying the invention.

In the same reference numerals denote identical or functionally identical Ingredients.

1A -G show schematic representations of successive process stages of a manufacturing method for a semiconductor structure with one of a plurality of overfilled isolation trenches as a first embodiment of the present invention.

In 1A denotes reference numeral 1 a silicon semiconductor substrate. Applied to the top O of the semiconductor substrate 1 are an intermediate layer 2 made of silicon oxide and a sacrificial layer 3 made of polysilicon. By means of a hard mask (not shown) on the sacrificial layer 3 is a plurality of trenches 5a . 5b been structured, extending through the layers 2 . 3 to the semiconductor substrate 1 extend. In the present example, these trenches are 5a . 5b STI trenches (STI = shallow trench isolation). 1A shows the state immediately after the removal of the hard mask for the trench etching.

In a subsequent process step, the in 1B is illustrated become Seitenwandspacer 6 made of silicon nitride as an intermediate layer on the trench walls. This is done in the usual way by deposition and anisotropic etching back of a silicon nitride layer.

In a subsequent process step, the in 1C shown are the trenches 5a . 5b with an insulating filling 10 filled from silicon oxide, which extends to the top of the sacrificial layer 3 extends. This is also done in a conventional manner by deposition and chemical-mechanical polishing back a silicon oxide layer, wherein the sacrificial layer 3 made of polysilicon serves as a polishing stop.

In a subsequent process step, there is a selective sinking of the filling 10 concerning the sacrificial layer 3 and the intermediate layer 6 to a predetermined projection ST of the top O 'of the remaining filling 10 with respect to the top O of the semiconductor substrate 1 to accomplish. The selective Einsenkprozess usually done by means of a wet or dry etching process. Subsequently, the sacrificial layer 3 polysilicon removed in a likewise selective etching process, resulting in the process state according to 1D leads.

Continue with reference to 1E then takes place a selective sinking the Seitenwandspacer 6 at the trench walls by a predetermined height h below the top surface O of the semiconductor substrate 1 , The fluctuation of the etching etch depth h is determined only by the etching process used, preferably a wet etching process. Fluctuations in the supernatant ST of the top O 'with respect to the top O play no role. By selectively sinking the sidewall spacers 6 a gap Z forms between the insulating filling 10 and the semiconductor substrate 1 ,

Continue with reference to 1F then becomes the intermediate layer 2 of silicon oxide, with an etching process that is selective with respect to the semiconductor substrate 1 and the remaining sidewall 6 is. Because of the small thickness of the intermediate layer 2 is no particular selectivity to the filling 10 necessary.

According to 1G Finally, parasitic corner devices become at the top corners of the trenches 5a . 5b formed by a gate dielectric 100 , z. B. a gate oxide and an overlying gate terminal layer 150 in the gap Z and on the surrounding top O of the semiconductor substrate 1 be formed.

In the present example, the trenches 5a . 5b formed as longitudinal trenches which extend into the plane of the drawing. The gate connection layer 150 is therefore also structured in longitudinal strips which extend within the plane of the drawing from left to right and are spaced apart by corresponding spaces perpendicular to the plane of the drawing.

According to the embodiment described above, the corner devices can thus be independent of the fluctuations of the STI-CMP process or the sinking of the filling 10 are adjusted, and self-aligned to the top O of the semiconductor substrate 1 ,

2A -F show schematic representations of successive process stages of a A manufacturing method of a semiconductor structure having a plurality of over-filled isolation trenches as a second embodiment of the present invention.

In addition to the structure of the first embodiment explained above, in the second embodiment according to FIG 2A at the moat walls and at the trench bottom of the trenches 5a . 5b another intermediate layer 2 ' formed of thermal silicon oxide, prior to the deposition of the intermediate layer 6 ' made of silicon nitride.

In the second embodiment, after the trench etch, a silicon nitride layer is formed 6 ' as an intermediate layer over the structure with the trenches 5a . 5b , in the 1A is deposited, with no side wall spacer made of the silicon nitride layer 6 ' are formed, but this is left over the entire surface of the structure. Thus, the horizontal regions form the silicon nitride layer 6 ' further sacrificial layer areas above the sacrificial layer 3 made of polysilicon.

Continue with reference to 2 B then takes place the deposition and polishing back of the insulating filling 10 of silicon oxide, this STI-CMP process being on top of the horizontal regions of the silicon nitride layer 6 ' stops.

Continue with reference to 2c Then, analogously to the first embodiment, the countersinking of the insulating filling within the trenches takes place 5a . 5b in a selective etching process for forming a supernatant ST of the upper surface O 'of the remaining insulating filling 10 opposite to the top O of the semiconductor substrate 1 ,

Subsequently, according to 2D the horizontal area of the intermediate layer 6 ' made of silicon nitride and the sacrificial layer 3 polysilicon in a respective selective etching process. Then done according to 2E selectively sinking the remaining portion of the silicon nitride interlayer 6 ' at the trench walls, by a predetermined height h below the top surface O of the semiconductor substrate 1 for adjusting the extent of the parasitic corner devices analogous to the first embodiment.

Subsequently, according to 2F the intermediate layer 2 of silicon oxide from the top O of the semiconductor substrate and in the trenches 5a . 5b to the same height as the intermediate layer 6 ' sunk into the moat walls.

The subsequent formation of the parasitic corner devices is analogous to 1G as already explained.

3 shows a schematic representation of a Verfahrensausgangsstadiums a manufacturing method for a semiconductor structure having a plurality of protruding filled isolation trenches as a third embodiment of the present invention.

This in 3 Stage of the third embodiment shown corresponds to that in 2a shown stage of the second embodiment, wherein an additional sacrificial layer 6 '' made of silicon nitride on the sacrificial layer 3 polysilicon prior to forming the trenches 5a . 5b has been applied. This further sacrificial layer 6 '' silicon nitride helps stop the STI-CMP process in the case of a thin intermediate layer 6 ' made of silicon nitride.

1

Silicon semiconductor substrate

5a, 5b

dig

50

hard mask

10

Silica-filling

O, O'

top

ST; STI ST6

supernatants

2, 2 '

interlayer made of silicon oxide

3

sacrificial layer made of polysilicon

6

Sidewall interlayer out

silicon nitride

H

height

Z

gap

100

gate dielectric

150

Gate layer

6 '

interlayer made of silicon nitride

6 ''

sacrificial layer made of silicon nitride

Claims (10)

Manufacturing method for a semiconductor structure with a plurality of overfilled isolation trenches ( 5a . 5b ) comprising the steps of: providing a semiconductor substrate ( 1 ); Forming a first intermediate layer ( 2 ) on the top (O) of the semiconductor substrate ( 1 ); Forming a sacrificial layer ( 3 ) or a plurality of sacrificial layers ( 3 ) on the first intermediate layer ( 2 ); Etching a plurality of into the semiconductor substrate ( 1 ) extending into isolation trenches ( 5a . 5b ) by means of a on the one sacrificial layer ( 3 ) or the plurality of sacrificial layers ( 3 ) provided mask; Removing the mask to expose the sacrificial layer remaining after etching ( 3 ) or the plurality of sacrificial layers ( 3 ); Forming an insulating second intermediate layer ( 6 ; 6 ' ) at the moat walls; Filling the plurality of isolation trenches ( 5a . 5b ) with an insulating filling ( 10 ), which are up to Top of a sacrificial layer ( 3 ) or the plurality of sacrificial layers ( 3 ) extends; selective sinking of the filling ( 10 ) with respect to one sacrificial layer ( 3 ) or the plurality of sacrificial layers ( 3 ) by a predetermined projection (ST) of the upper side (O ') of the remaining filling ( 10 ) with respect to the top (O) of the semiconductor substrate ( 1 ) to build; selective removal of a sacrificial layer ( 3 ) or the plurality of sacrificial layers ( 3 ) with respect to the first intermediate layer ( 2 ), the second intermediate layer ( 6 ; 6 ' ) and the filling ( 10 ); and selectively sinking the second intermediate layer ( 6 ; 6 ' ) on the trench walls by a predetermined height (h) below the top (O) of the semiconductor substrate ( 1 ) with regard to the filling ( 10 ) and the first intermediate layer ( 2 ) for forming a gap (Z) between the filling ( 10 ) and the semiconductor substrate ( 1 ). Method according to claim 1, characterized in that the following step is carried out: selective removal of the first intermediate layer ( 2 ) with respect to the semiconductor substrate ( 1 ) and the second intermediate layer ( 6 ; 6 ' ). A method according to claim 1 or 2, characterized in that the following step is performed: forming a parasitic corner device by forming a gate dielectric layer ( 100 ) and an overlying gate connection layer ( 150 ) in the intermediate space (Z) and on the surrounding upper side of the semiconductor substrate ( 1 ). Method according to one of the preceding claims, characterized in that the semiconductor substrate ( 1 ) made of silicon, the first intermediate layer ( 2 ) of silicon oxide, the second intermediate layer ( 6 ; 6 ' ) of silicon nitride and the filling ( 10 ) consist of silicon oxide. Method according to one of the preceding claims, characterized in that the following steps are carried out: forming a third intermediate layer ( 2 ' ) at the trench walls under the second intermediate layer ( 6 ; 6 ' ) in the region of the semiconductor substrate ( 1 ); and sinking the third intermediate layer ( 2 ' ) at the trench walls at approximately the predetermined height (h) below the top (O) of the semiconductor substrate ( 1 ) selectively to the semiconductor substrate ( 1 ) and the second intermediate layer ( 6 ; 6 ' ) for forming the gap (Z) between the filling ( 10 ) and the semiconductor substrate ( 1 ) while simultaneously removing the first intermediate layer ( 2 ) Method according to claim 5, characterized in that the third intermediate layer ( 2 ' ) consists of silicon oxide. Method according to one of the preceding claims, characterized in that the forming of the second intermediate layer ( 6 ; 6 ' ) over the entire surface and the parallel to the top (O) extending region of the second intermediate layer ( 6 ; 6 ' ) another, after etching the isolation trenches ( 5a . 5b ) forms a sacrificial layer. Method according to one of the preceding claims, characterized in that a first and a second sacrificial layer ( 3 . 6 '' ) on the first intermediate layer ( 2 ) before etching the isolation trenches ( 5a . 5b ) are formed. Method according to one of the preceding claims, characterized characterized in that the respective selective sinking or selective Remove in a dry or wet chemical etching process with appropriate selectivity carried out becomes. Method according to one of the preceding claims, characterized in that forming the filling ( 10 ) by depositing the filling ( 10 ) and then back polishing the filling ( 10 ) takes place in a chemical-mechanical polishing process.