DE102005004354A1 - Semiconductor device, e.g. insulated gate bipolar transistor, has floating area including penetration depth in drift areas, where depth corresponds to another two penetration depths of base areas and trenches - Google Patents

Abstract

Semiconductor device has a semiconductor body between front and rear side contacts with front and rear side surfaces. Control electrodes are embedded against base areas (3) in trenches, such that current flow between emitter areas (9) and drift areas is controllable by the electrodes. A floating area (5) has a penetration depth in the drift areas, where the depth corresponds to another two penetration depths of the base areas and the trenches.

Description

The The present invention is in the technical field of semiconductor devices and more particularly relates to a field effect controllable semiconductor device with improved overvoltage protection.

High-voltage switch in power electronics, such as IGBTs (Insulated Gate Bipolar Transistors) and the like, become common designed so that their reverse voltage well above the typical is the application specified by the operating voltage. Is that lying Operating voltage, for example, in the range of 600-850 V, so will one for that to disposal switch module (eg IGBT), for example, designed so that it has a rated reverse voltage of 1200V. As it turned out has, is such a big one Safety clearance necessary to turn off the high-voltage switch occurring high surges to catch up to destruction to avoid the IGBT. Cause of the high overvoltages are high current change rates dI / dt and the always present (also parasitic) inductances ("stray inductances"). Particularly high overvoltages especially occur when switching off a multiple of the rated current is, as in the so-called overcurrent or short circuit case.

In In this respect, especially the modern, very fast (off) switching high-voltage switch proved problematic, which at high leakage inductances to very high surges tend. examples for Such modern, fast switching IGBTs are described in T. Laska et al. "The Field Stop IGBT (FS IGBT) - A New Power Device Concept with a Great Improvement Potential ", Proceedings of the 12th ISPSD, pp. 355-358, 2000; M. Otsuki et al. "Investigation of the short circuit Capability of 1200V Trench Gate Field-Stop IGBTs, Proceedings of the 14th ISPSD, pages 281-284, 2002; S. Dewar et al. "Soft Punch Through (SPT) - Setting new Standards in 1200V IGBT ", Proc. PCIM Europe, 2000; K. Nakamura et al. Having Advanced Wide Cell Pitch CSTBTs Light Punch-Through (LPT) Structures ", Proceedings of the 14th ISPSD, pages 277-280, 2002.

The Problem of turning off due to fast current change speeds and stray inductances occurring high surges has so far mainly been solved by the user side her big Efforts have been made, either by special drive circuits or by means of reduced build-up stray inductances, the overvoltages that occur to reduce, so the high-voltage switch in a satisfactory To use way. However, this is at high extra cost in the development and / or Manufacturing connected. About that In addition, through this approach, the freedoms in the chip design limited.

As one way to limit overvoltages in IGBTs, the dynamic "self-clamping" property of an IGBT has recently been discussed based on the changes in net charge density of the drift region due to avanlanche current, washed-out neutral region charge carriers and collector-side hole injection ( see, eg. BM Takei et al., "Analysis on the Self-Clamp Phenomena of IGBTs" in Proc. 11 ^th ISPSD, Poster session, Paper 7.1, 1999 and M. Otsuki "1200V FS IGBT module with enhanced dynamic clamping capability," Proceedings of the 2004 ISPSD, pages 339-342, 2004).

If Consequently, it is possible to design a high-voltage switch so that despite existing high stray inductances and high rates of current change is able to do a while the shutdown occurring high overvoltage by self-clamping dynamically limit ("Dynamic Clamping ") and these Load (which up to a multiple of the rated current at about the Nominal voltage can be) over many 100 ns to a few μs could endure that way the user much more creative freedom, in particular with regard to the inverter design, are available (minimized driving effort and / or minimized effort with regard to leakage inductances). Furthermore would this very beneficial for the component manufacturer, since the chips switching even faster and thus designed with lower losses could become, without the risk of excessive overvoltages when switching off under extreme conditions (overcurrent or short circuit) to increase.

Around To achieve this, the design of an IGBT chip must be special Be conceived way. These include the backside emitter efficiency and suitably dimensioning the field stop layer (see For example, M. Otsuki et al. "1200 V FS-IGBT module with enhanced clamping capability "; Proceedings of the 2004 ISPSD, pages 339-342, 2004).

In addition, it is essential that the IGBT cells be dimensioned so that the collector-emitter breakdown voltage is lower than the edge breakdown voltage so as not to stress the chip edge unnecessarily strong and unilaterally during the phase of dynamic clamping. Rather, it should be achieved that the load is distributed homogeneously to many cells. One way in which this can be achieved is in the German patent DE 100 19 813 C2 described. In this case, the weak n-type doping in the drift region between the cells or below the cells is deliberately raised, which, however, involves considerable additional effort and is problematic in terms of process technology, in particular in terms of accuracy and reproducibility.

In contrast, lies an object of the present invention therein, by means of field effect controllable semiconductor device, in particular IGBT, specify that an improved overvoltage protection has, without taking the disadvantages presented at the outset in purchasing to have to. In particular, such a semiconductor device should be designed in such a way that that the collector-emitter voltage is lower than the edge breakdown voltage, without the procedural disadvantages of an increased dopant concentration in the drift region between the cells or below the To have to accept cells.

These Task is according to the proposal of the invention by means of a Field effect controllable semiconductor device solved according to the independent claim. advantageous Embodiments of the invention are specified by the subclaims.

Therefore is according to the invention a means of field effect controllable semiconductor device shown in conventional One front contact, one back contact and one between front and backside contact arranged semiconductor body with a front surface and a back Surface, which of the front surface in a vertical construction, includes.

In the semiconductor body is in the front surface a trench structure formed with a plurality of trenches, that is, the Ditches extend extending from the front surface into the semiconductor body, being the trenches typically in a direction perpendicular to the front surface of the semiconductor body are formed. A penetration depth of the trenches is determined in this Case in a vertical to the front surface of the semiconductor body Direction (a direction perpendicular to the front surface that leads to the rear surface shows) and is given by the depth of the trenches. The trenches can be in the plan view (on the front surface of the semiconductor body) strip-shaped be, d. H. the trenches run parallel to each other in cross section. On the other hand, the trenches Single cells also circulate and, for example, respective square ones or hexagonal structures.

In the trench structure of the semiconductor device according to the invention is one opposite their environment electrically insulated control electrode structure for Embedded for purposes of controlling the field effect of the semiconductor device, d. H. Control electrodes are accommodated in the trenches. An electric Isolation of the control electrode structure from its environment can doing so by an ordinary Insulation layer, such as an oxide layer. In general Therefore, at least parts of the control electrodes in the trenches in one Confrontation positioned to the base regions, allowing for the electrically conductive Connection of the emitter areas with the drift area by field effect a conductive channel can be formed in the base regions.

Of the Semiconductor body of the semiconductor device according to the invention further comprises a (lightly doped) drift region of the first conductivity type (n), at least one base region of the second conductivity type (p), the stronger is doped as the drift region, at least one emitter region of first conductivity type (s), the stronger is doped as the drift region, and at least one unconnected (floating) Floating region of the second conductivity type (p), the more heavily doped is as the drift area. Here is the front side contact with the Emitter areas and usually also with the base areas electrically conductively connected.

Between neighboring trenches The trench structure are intracellular areas and intercellular areas in alternating sequence (translatorically periodic) formed, d. H. one intracellular area is formed between adjacent trenches and one inter-cell area is formed between adjacent trenches. An intracellular region comprises at least one (typically two) of the emitter regions of the first conductivity type (s), at least one (typically one) of the base regions of the second conductivity type (p) and at least parts of the drift region, while an intercell region at least one (typically one) of the unconnected Floating areas of the second conductivity type (p) and at least parts of the drift area. The naming "Intrazellgebiet" or "Interzellengebiet" becomes thereby clear: by the adjacent trenches and that area between these, in which the emitter and base areas are conventional defines a (transistor) cell of the semiconductor device, so that through the intercell area the area between the cells is defined.

A penetration depth of the emitter and base regions into the semiconductor body or the drift region is determined, in a manner analogous to the above definition of the penetration depth of the trenches, generally in one of the front surface of the semiconductor body to the rear surface of the Halbleiterkör pers directed direction, which is typically perpendicular to the front surface of the semiconductor body.

As a general rule intended as a penetration depth in the context of the present invention not an individual dimension of trenches, emitter or base areas in one of the front surface of the semiconductor body to rear surface of the semiconductor body directed direction, but one in the semiconductor body, in particular in the drift area, reached depth of the lower edge of these structures.

The inventive semiconductor device is now characterized by the fact that the floating areas a penetration depth into the semiconductor body (or into the drift area) have, at least, the penetration depth of the base areas, however at the most the penetration depth of the trenches equivalent. In other words, the depth of penetration of the floating areas lies between the penetration depths of the base regions and the trenches, i. H. the bottom of the floating areas in the drift area is at least so deep or lies lower than the lower edge of the base areas in the drift area while the lower edge of the trenches in the drift area is at least as deep or lower than the lower edge of the floating areas in the drift area.

In the semiconductor device according to the invention can through the special design of the penetration depths of the trenches, floating and base areas one achieved excellent dynamic clamping ability become. It is about a specifically designed trench depth in relation to the penetration depth of the floating areas and the penetration depth of the base regions, the "inhomogeneity" of the trench outer edge, which is a field swell in Semiconductor body (or in the drift region) causes, used selectively, the breakdown voltage the (transistor) cells in a moderate manner of z. Typically 1350 V to lower by 100-150V. In this way, the edge remains special relieved in the case of dynamically occurring high voltages and the the energy occurring is distributed at "clamped", not too high voltage (eg 1200-1300 V), in a particularly advantageous manner evenly on all (transistor) cells.

The Dopant concentration can, in contrast to the beginning mentioned prior art, about the entire area between or below the (transistor) cells kept constant. The difference between the depth of the grave is allowed and the depth of penetration of the floating area does not become too large, otherwise the cell breakdown voltage would be lowered too much (im Extremely well below the rated voltage, such as when For example, you can completely do without the training of the floating area would).

at a preferred embodiment of the semiconductor device according to the invention is the difference of the penetration depth of the trenches to the penetration depth of Floating areas therefore a maximum of 3 microns and is preferably in Range of 0.5 to 3 microns.

in the Case of an IGBT is the edge closure of the IGBTs by means of a Feldplatten edge structure or ring edge structure of the second charge type (P) or JTE edge structure preferably designed so that the local Breaking voltage is at a significantly higher level than in the Transistor cells. So is the edge breakdown voltage z. B. 1350 V and the trench cell breakdown voltage for example 1250 V.

The inventive semiconductor device can be made in a simple way, such as the temperature budget the floating area is reduced at a given trench depth, so that the penetration depth of the floating area is reduced, or Alternatively, by the trench depth for a given floating area (resp. given depth of penetration of the floating area) is increased so that the outer grave corner not anymore - so as usual - from the Floating area is surrounded.

On this way manufactured (power) semiconductor devices according to the invention, In particular IGBTs, show a reduced by about 100 V static breakdown voltage (eg 1250 V instead of 1350 V), since the edge structure is no longer but the cell structure determines the breakdown voltage. Furthermore the semiconductor devices according to the invention are distinguished characterized by superior avalanche strength. such Chips can be added Stray inductors up in the μH range in turn off a double rated current and the voltage is limited dynamically even at about 1300 V, while conventional components under these conditions due to an excessive current / voltage load destroyed in the edge area would.

at an advantageous embodiment of the semiconductor device according to the invention show the trenches a penetration depth (trench depth) in the range of approx. 4 μm to approx. 8 μm. In particular, in this case, it is advantageous if the floating areas a Penetration depth in the range of about 3 microns to about 7 microns have.

It is according to the invention preferred if the field effect controllable semiconductor device as a power semiconductor component, in particular high-voltage switch, like a power IGBT, is designed.

In the case of a power IGBT, the The semiconductor body between the drift region and the backside contact further comprises an anode region of the second charge carrier type (p), which is more heavily doped than the drift region. In this case, the backside contact is usually a large area in direct contact with the anode area. Such a power IGBT is also referred to as non-punch-through (NPT) -IGBT. In another variant, which is referred to as punch-through (PT) -IGBT or more often as field stop (FS) -IGBT, the semiconductor body further has a field stop region (also referred to as buffer region) of the first charge carrier type (s) between the drift region and the anode region. which is more heavily doped than the drift region. According to the invention, it is preferred that the doping of the field stop region is reduced to the extent necessary for the static blocking capability, in order thereby to further improve the avalanche resistance of the PT-IGBT. A preferred charge carrier density in this respect is in the range of approx. 1 × 10 ¹¹ cm ^-3 to approx. 1 × 10 ¹² cm ^-3 .

The Invention will now be explained in more detail with reference to an embodiment, wherein Reference to the attached Subscriptions is taken. Same or equivalent elements are provided in the drawings with the same reference numerals.

1A schematically shows a vertical section through a front-side section of the semiconductor body of a conventional semiconductor device;

1B schematically shows a vertical section through a front-side section of the semiconductor body of a semiconductor device according to the invention;

2 shows in a schematic way a vertical section through a (PT) FS-IGBT according to the invention.

First, reference to the two 1A and 1B which schematically shows vertical sections along the trenches of the trench structure through front-side sections of the semiconductor body of a conventional ( 1A ) and a semiconductor device according to the invention ( 1B ) are shown.

Accordingly, in a semiconductor device is a semiconductor body 1 provided in which a weakly n-doped drift region 2 and p-doped regions 3 . 5 are formed, whose doping is higher than in the drift region 2 , Further, the semiconductor body 1 provided with a trench structure, the trenches parallel to each other, in a y-direction deepening 4 having. In the trenches 4 are not shown control electrodes 8th for controlling electrically conductive channels in the p-doped base regions 3 provided, the control electrodes, in particular with respect to the base areas 3 are electrically isolated by an insulating layer (not shown). Between the trenches 4 There are intracellular areas A and intercell areas B, the latter being shown only partially and are to be imagined extending to no longer shown, adjacent trenches in a direction x and -x. The intracellular regions A include the p-doped base regions 3 which are in direct contact with a front side electrode (not shown) and a part of the weakly n-doped drift region 2 while the intracell areas B the p-doped floating areas 5 and a portion of the weakly n-doped drift region 2 include.

There now follows a description of the differences in the 1A and 1B shown sections of a conventional and a semiconductor device according to the invention.

In the in 1A shown section of a conventional semiconductor device embrace the p-doped floating regions 5 by means of Umgreifzonen 6 usually the corners 7 the trenches 4 to thereby avoid a local field overshoot by peak effects, whereby the static breakdown voltage of the semiconductor device can be increased. The cell breakdown voltage in this case is greater than or equal to the edge breakdown voltage.

In the in 1B shown section of a semiconductor device according to the invention are missing in contrast to 1A the Umgreifzonen 6 the floating areas 5 so the corners 7 the trenches 4 into the weakly n-doped drift region 2 plunge. In addition, the penetration depths of the trenches determined in the y-direction are 4 , the sis areas 3 and the floating areas 5 in the drift work 2 designed so that the penetration depth T _{2 of} the floating areas 5 between the penetration depth T _{1 of} the base regions 3 and the penetration depth T _{3 of} the trenches 4 lies. For the penetration depths, therefore, the mathematical relationship T ₁ ≦ T ₂ ≦ T ₃ applies. In other words, the penetration depth T _{3 of} the trenches differ 4 and the penetration depth T _{2 of} the floating areas 5 by a non-negative difference D ₁ , while the penetration depth T _{2 of} the floating areas 5 and the penetration depth T _{1 of} the base regions 3 differ by a non-negative difference D ₂ . In this case, the cell breakdown voltage is smaller than the edge breakdown voltage.

It will now be referred to 2 which schematically shows a vertical section through a (PT) FS-IGBT according to the invention. The IGBT includes a front cone clock 11 , a backside contact 12 and a semiconductor body disposed between front and backside contacts 1 with a front surface and a back surface. The front side is in the semiconductor body 1 a trench structure formed, which mutually parallel trenches 4 having. In plan view, this corresponds to a strip-shaped pattern of the trenches. Alternatively, the trenches could, for example, circulate respective single cells in square or hexagonal form. The semiconductor body 1 includes in the direction of the backside electrode 12 to the front side electrode 11 a p-doped anode region 13 as an emitter for minority carriers, an n-doped field stop region 14 , a weakly n-doped drift region and p-doped regions 3 . 5 namely base areas 3 and floating areas 5 , Intra-cell A and B-cell areas are alternating between the trenches 4 formed, wherein the intracellular regions each have the n-doped emitter regions 9 , the p-doped base regions 3 and parts of the weakly n-doped drift region 2 while the intercell regions comprise the p-doped floating regions 5 and parts of the drift area 2 include. Depending on the structure of the trench, these intercellular and intracellular regions can be designed in the form of a rod or else square, hexagonal or the like.

In the trenches 4 are control electrodes 8th recorded by means of the insulating layer 10 towards their environment, especially towards the base areas 3 are isolated. The front side electrode 11 is in direct contact with the n-doped emitter regions 9 and the p-doped base regions 3 , The backside electrode 12 is in direct contact with the p-doped anode region 13 , In the in 2 (PT) FS-IGBT is the penetration depth of the p-doped floating regions 5 between the penetration depth of the p-doped base regions 3 and the penetration depth of the trenches 4 ,

1

Semiconductor body

2

drift region

3

base region

4

dig

5

floating area

6

Umgreifzone

7

grave corners

8th

control electrode

9

emitter region

10

insulator layer

11

Front side electrode

12

Back electrode

13

anode region

14

Field stop region

Claims (11)

Field-effect-controllable semiconductor device that provides a between a front side contact ( 11 ) and a backside contact ( 12 ) arranged semiconductor body ( 1 ) having a front and a back surface, wherein the semiconductor body ( 1 ) a drift area ( 2 ) of the first conductivity type (s), at least one base region ( 3 ) of the second conductivity type (p), at least one emitter region ( 9 ) of the first conductivity type (s), and at least one non-connected, floating floating region ( 5 ) of the second conductivity type (p), and wherein in the front surface a trench structure having a plurality of trenches (FIG. 4 ) is formed, wherein between adjacent trenches ( 4 ) Intracellular regions (A) and intercellular regions (B) are formed in an alternating sequence, wherein an intracellular region (A) of at least one of the emitter regions (A) 9 ) of the first conductivity type (s), at least one of the base regions ( 3 ) of the second conductivity type (p) and at least parts of the drift region ( 2 ), and wherein an intercell area (B) of at least one of the non-connected, floating floating areas ( 5 ) of the second conductivity type (p) and at least parts of the drift region ( 2 ) and into the trenches ( 4 ) Control electrodes ( 8th ) isolated against the base regions ( 3 ) are embedded, whereby by the control electrodes ( 8th ) Current flows between the emitter areas ( 9 ) and the drift area ( 2 ) are controllable, characterized in that the floating areas ( 5 ) each have a penetration depth (T ₂ ) into the drift region ( 2 ) having at least the penetration depth (T ₁ ) of the base regions ( 3 ) and at most the penetration depth (T ₃ ) of the trenches ( 4 ) corresponds. Semiconductor component according to Claim 1, in which the semiconductor body is arranged between the drift region ( 2 ) and the backside contact ( 12 ) an anode region ( 13 ) of the second charge carrier type (p), which is more heavily doped than the drift region ( 2 ). Semiconductor component according to Claim 2, in which the semiconductor body is arranged between the drift region ( 2 ) and the anode area ( 13 ) a field stop area ( 14 ) of the first charge carrier type (s), which is more heavily doped than the drift region ( 2 ). Semiconductor component according to Claim 3, in which the field stop region ( 14 ) has a charge carrier density in the range of about 1 × 10 ¹¹ cm ^-3 to approx. 1 × 10 ¹² cm ^-3 . Semiconductor component according to one of the preceding claims, wherein one of the penetration depth (T ₃ ) of the trenches ( 4 ) and the penetration depth (T ₂ ) of the floating areas ( 5 ) resulting difference (D ₁ ) is a maximum of 3 microns. Semiconductor component according to Claim 5, in which one of the penetration depths (T ₃ ) of the trenches ( 4 ) and the penetration depth (T ₂ ) of the floating areas ( 5 ) resulting difference (D ₁ ) in the range of 0.5 .mu.m to 3 microns. Semiconductor component according to one of the preceding claims, in which one of the penetration depth (T ₂ ) of the floating regions ( 5 ) and the penetration depth (T ₁ ) of the base regions ( 3 ) resulting difference (D ₂ ) is at least 0.5 microns. Semiconductor component according to Claim 5, in which one of the penetration depths (T ₂ ) of the floating regions ( 5 ) and the penetration depth (T ₁ ) of the base regions ( 3 ) resulting difference (D ₂ ) is in the range of 0.5 microns to 3 microns. Semiconductor component according to one of the preceding claims, in which the trenches ( 4 ) have a penetration depth (T ₃ ) in the range of about 4 microns to about 8 microns. Semiconductor component according to one of the preceding claims, in which the floating regions ( 5 ) have a penetration depth (T ₂ ) in the range of about 3 microns to about 7 microns. Semiconductor component according to one of the preceding Claims, which is designed as a power semiconductor device.