DE102004057238B4 - Semiconductor device with passivation layer - Google Patents

Abstract

Semiconductor device with a semiconductor body (1), above which a passivation layer (6) is provided, wherein between the passivation layer (6) and the semiconductor body (1) a metal layer (4) having an edge is provided, characterized by a crack formation structure, (8, 10, 11, 13) which comprises a cavity (13) located between the edge (8) of the metal layer (4) and an insulation / spacer structure adjacent to the metal layer (4) (12) is formed.

Description

The The present invention relates to a semiconductor device having a semiconductor body, above of which a passivation layer is provided, wherein between the passivation layer and the semiconductor body, a metal layer, the having an edge is provided.

In usually become semiconductor devices with a passivation layer provided to the influences of Environment, such as temperature fluctuations or humidity, on the semiconductor components as possible to keep low. The passivation layer can also be used for mechanical Stabilization of the semiconductor devices serve.

Becomes a semiconductor device with passivation layer strong temperature fluctuations exposed, so can due to different thermal expansion coefficients of passivation layer and adjacent to the passivation layer Regions of the semiconductor device cracks in the passivation layer arise. This is the case in particular when the semiconductor component by a molding compound adjacent to the passivation layer, outward is completed because the thermal expansion coefficient of passivation layer and molding compound differ greatly can. If a crack develops within a critical region of the semiconductor device, For example, in one area, the two conductive areas from each other isolated, so the crack can affect the functioning lead the semiconductor device. In the worst case leads the cracking to a total failure of the semiconductor device.

In detail is from the US 5,539,257 A a semiconductor device is known which has inhomogeneities in the thickness of a passivation layer. The layer thickness of the passivation layer is particularly low in the vicinity of the edges of a metal layer, which is located directly below the passivation layer.

Furthermore, it is from the EP 0 867 934 A1 It is known to provide geometric discontinuities, such as thickness variations, in a crack susceptible layer. Finally, the still describes US 5,358,733 A a reduction of mechanical stresses in large integrated circuits by a "wave-shaped" design of metallizations.

Of the The present invention is based on the object, a semiconductor device its operation in case of cracking in the passivation layer not or only to a limited extent.

to solution In accordance with this object, the present invention provides a semiconductor device of the type mentioned above, which is characterized by a crack formation structure, which includes a cavity located between the edge of the metal layer and an insulation / spacer structure adjacent to the metal layer is. Advantageous embodiments or developments of the invention are in the subclaims specified.

The inventive semiconductor device has So first a semiconductor body on, above which a passivation layer is provided. Between the passivation layer and the semiconductor body is adjacent to the passivation layer and a cavity having cracking structure provided when mechanical stress occurs within the passivation layer the formation of cracks at defined locations in the passivation layer favored.

By The cracking structure can be the formation of cracks to uncritical Be limited areas of the semiconductor device. So it will not the occurrence of cracks itself avoided, but instead Influence on the location of cracking taken.

The Crack formation structure is also partly due to the surface structure the metal layer arranged below the passivation layer, namely by an edge of the metal layer, mitgestaltet.

If below the passivation layer such a metal layer is arranged (for example, a metal layer for contacting of source and drain regions of a transistor) connected to the passivation layer adjacent, so the cracking structure should be designed that the formation of a crack above the metal layer is favored, because cracks in this area only negligible small impairment effect the operation of the semiconductor device.

A Such metal layer advantageously forms the uppermost metal layer ("Power metallization") of the semiconductor device. However, it is just as possible the surface structures, especially peaks and edges of deeper lying metal layers or exploiting other layers to form spatially limited cracks, as long as the mechanical effects of the surface structures of these layers affect the passivation layer.

The crack formation structure comprises a cavity which is formed between the edge of a metal layer arranged below the passivation layer and an insulation / spacer structure adjoining the metal layer. The cavity may be defined, for example, by a recess in the insulation / spacer structure are formed. Preferably, the insulation / spacer structure comprises a silicon nitride layer adjacent to the metal layer (other conceivable materials would be polysilicon, SiO _x N (silicon oxide nitride)) and a silicon oxide layer deposited thereon, the cavity being formed by a recess in the silicon nitride layer.

The The invention is not limited to the above-mentioned cracking structure examples limited, Rather, any cracking structures are conceivable.

The Invention will be described below with reference to the figures exemplary embodiment explained in more detail. It demonstrate:

1 a region of a first conventional semiconductor device in a perspective view, in which due to mechanical stress, a crack has formed in the passivation layer of the semiconductor device,

2 a detail of a section of the in 1 shown semiconductor device,

3 a perspective view of a portion of a second conventional semiconductor device with crack in the passivation layer,

4 a perspective view of a portion of a third conventional semiconductor device with crack in the passivation layer,

5 a plan view of a conventional semiconductor device having cracks in the passivation layer,

6 a simulation of the mechanical stress in a passivation layer in the vicinity of a metal edge lying below the passivation layer,

7 a first process step for producing a preferred embodiment of the semiconductor device according to the invention,

8th a second process step for producing a preferred embodiment of the semiconductor device according to the invention,

9 a third process step for producing a preferred embodiment of the semiconductor device according to the invention,

10 a fourth process step for producing a preferred embodiment of the semiconductor device according to the invention,

11 a fifth process step for producing a preferred embodiment of the semiconductor device according to the invention,

12 a sixth process step for producing a preferred embodiment of the semiconductor device according to the invention, and

13 a micrograph of a section of the in 10 to 12 shown semiconductor device.

In the figures are identical or corresponding areas marked with the same reference numerals.

In 1 a micrograph of a conventional semiconductor device with passivation layer is shown. On a semiconductor body 1 are a first, second and third metal layer 2 . 3 . 4 arranged, at least partially, by insulating layers 5 against each other or with respect to the semiconductor body 1 are electrically isolated. The semicon terbauteil is upward through a passivation layer 6 completed.

In the passivation layer 6 are cracks 7 formed due to mechanical stresses within the passivation layer 6 arise. As 2 can be seen, by the mechanical stresses within the passivation layer 6 both cracks in the passivation layer 6 itself as well as cracks within the insulating layers 5 (Intermetal dielectric) arise, which is the penetration of moisture from the outside into the semiconductor device and short circuits between the metal layers 2 . 3 and 4 can result. The mechanical stresses within the passivation layer 6 can thus lead to severe impairment of the operation of the semiconductor device.

In 3 is shown to be cracks within the passivation layer 6 mainly on edges 8th the below the passivation layer 6 located metal layer 4 form. However, cracks can also occur above even metal surfaces in the passivation layer 6 train as in 4 is shown.

Cracks are not a serious problem if they are above the metal layer 4 run, as in 3 and 4 is shown. However, the situation is critical if, as in 5 shown, the cracking also areas 9 in which are below the passivation layer 6 no metal layer (metal layer 4 ) is formed ("power metallization free" areas). In these areas, the operation of the semiconductor device is particularly sensitive affected by cracking.

In 6 It is shown that the mechanical stress within the passivation layer 6 near edges 8th one below the passivation layer 6 arranged metal layer 4 is especially big.

A preferred embodiment of the semiconductor device according to the invention, its production in 7 to 12 described, exploits this knowledge. In the following description, the manufacturing process of this embodiment will be explained in more detail.

On a semiconductor body 1 a metal layer (power metallization) is deposited, wherein in the upper region of the metal layer 4 edge 8th are trained ( 7 ).

Subsequently, 8th ) on the metal layer 4 a silicon nitride layer 10 deposited, and on the silicon nitride layer 10 becomes a silicon oxide layer 11 applied.

Then the silicon nitride layer 10 and the silicon oxide layer 11 by anisotropic etching (spacer etching) down to the surface of the semiconductor body 1 or the surface of the metal layer 4 etched back so that lateral to the metal layer 4 adjacent isolation / spacer structures 12 arise ( 9 ).

In the next process step ( 10 ) become upper and lower portions of the silicon nitride layer 10 removed, which is done for example by a selective, isotropic etching process. In this way arise between the edges 8th and dividing the silicon oxide layer 11 cavities 13 ; the same applies analogously to lower regions of the metal layer 4 ,

In a further process step ( 11 ) is placed on the in 10 structure obtained a passivation layer 6 deposited, resulting from a first layer 6 ₁ (Oxide) and a second layer 6 ₂ (Silicon nitride).

In a final process step ( 12 ) becomes one above the metal layer 4 arranged region of the passivation layer 6 removed, leaving the metal layer 4 can be contacted. As 12 it can be seen that there are four "intended" 14 the passivation layer 6 present, which is the formation of cracks along these predetermined breaking points 14 favor. Cracks along these predetermined breaking points lead to no significant impairment of the operation of the semiconductor device. Through the predetermined breaking points 14 Therefore cracks are directly above the semiconductor body 1 that is, left and right of the metal layer 4 , largely avoided because of mechanical stresses within the passivation layer 6 completely by cracks along the predetermined breaking points 14 can break down.

In 13 is a micrograph of the in 9 to 12 shown isolation / spacer structure 12 shown. Here was the metal layer 4 structured by a wet-chemical process. "Functional" predetermined breaking points 14 However, they can also be achieved by structuring the metal layer 4 produce with a dry etching, especially if the flanks of the metal layer 4 precipitous. The thickness of the metal layer 4 is not on the in 9 to 12 shown thickness limited.

In The following description is intended to cover further aspects of the invention discussed become.

When using a standard passivation (300 nm oxide and 800 nm SiN) over a power metallization (structured aluminum) occurs after typical temperature tests (step a): 192 hours "Soak" (soaking) at about 80 ° C and 30% -80% Humidity, step b): 3 × 240 ° C (simulation of a brazing temperature) and step c): thermal cycling ("TC"): eg 1000 × from -55 ° C to 150 ° C) to form passivation cracks. Simulations show that the greatest stress is built on the aluminum edge of the power metallization ( 6 ). Cracks can either lead directly to electrical failures (short circuits, leakage through aluminum pressed into the cracks), or later pose a reliability risk due to moisture ingress and subsequent anodic oxidation of TiN layers and corrosion.

It turns out that all Smart Power Technology (SPT) products experience passivation cracks, but only very specific products and designs show electrical failures, including, but not limited to, the size of the chip. It can also be seen that not all cracks in the passivation layer are ultimately responsible for an electrical failure: cracks that run along or above the power metallization or end at an edge of the power metallization are harmless. However, cracks that run in an aluminum-free area can rupture the underlying intermetallic dielectric or cause (pre-) damage / weakening thereof - see eg 1 and 2 , This results in further thermomechanical stress to the above-described failure mechanisms.

So far There is no known process which causes thermal cracking Would prevent cycles.

In accordance with the invention, in a preferred embodiment, predetermined breaking points are deliberately installed at the edge of the power metallization. The occurring during thermal cycling shear stress caused by the different expansion coefficients of silicon chip (semiconductor body) and molding compound, which acts on the passivation layer, can be degraded along the predetermined breaking point by deliberate breaking of the passivation layers. This prevents an uncontrolled "breaking out" of the passivation cracks in the area free of metallization.

The predetermined breaking point is formed for example by a spacer of nitride and oxide along an aluminum edge with subsequent isotropic nitride undercutting (see 9 and 10 ). The "undercut" of the nitride creates a predetermined breaking point on the spacer at the upper and lower edge of the aluminum.

After the structuring of the metal 4 intermediate oxide is followed by the deposition of the spacer layers 10 . 11 , For example, silicon nitride 3 and silica 4 be used. However, other combinations of mutually selectively etchable, conductive or non-conductive materials can be used, for example, oxide and poly. In the example given below, 40 nm SiN (PECVD) and 1400 nm SiOx (PECVD) have been used. As in 9 shown, then an anisotropic etching process for the production of the spacer structure is used. The spacer structure can be made, for example, using a "Lam Rainbow" system, using Ar, CF4, CHF3 and N2 for 170s at a power of 1300 W and 300 mTorr pressure. For generating the predetermined breaking point at the edges of the spacer and the aluminum, for example, an isotropic etching of the silicon nitride ( 10 ). The isotropic undercut can be made with a "CDE80" system using CF4, O2 and N2 for 180s at a power of 700 W and 70 Pa pressure. Subsequently, the deposition of the standard passivation layers ( 11 ). For example, a 300 nm PECVD oxide layer 6 ₁ and a 800 nm PECVD SiN layer 6 ₂ be used. With the opening of the pads ( 12 ) the process block is completed.

In Modification of the described embodiment, the undercut and so that the double layer can be omitted. In this case, the Aluminum spacers consist of only one layer and ensure that the stress is reduced without breaking point only over the aluminum spacer becomes.

1

Semiconductor body

2

first metal layer

3

second metal layer

4

third metal layer

5

insulating layer

6

passivation layer

7

Crack

8th

edge

9

area

10

silicon nitride

11

silicon oxide

12

Insulating / spacer structure

13

cavity

14

Breaking point

Claims (4)

Semiconductor component, having a semiconductor body ( 1 ), above which a passivation layer ( 6 ), wherein between the passivation layer ( 6 ) and the semiconductor body ( 1 ) a metal layer ( 4 ) having an edge, characterized by a crack formation structure, ( 8th . 10 . 11 . 13 ) which has a cavity ( 13 ), which is between the edge ( 8th ) of the metal layer ( 4 ) and one to the metal layer ( 4 ) adjacent isolation / spacer structure ( 12 ) is trained. Semiconductor component according to claim 1, characterized in that the cavity ( 13 ) through a recess in the insulation / spacer structure ( 12 ) is formed. Semiconductor component according to Claim 2, characterized in that the insulation / spacer structure ( 12 ) a silicon nitride layer adjacent to the metal layer ( 10 ) and a silicon oxide layer ( 11 ), wherein the cavity ( 13 ) through a recess in the silicon nitride layer ( 10 ) is formed. Semiconductor component according to one of Claims 1 to 3, characterized in that the metal layer ( 4 ) is the uppermost metal layer of the semiconductor device.