DE102004048745B4 - Method for forming a bit line structure - Google Patents

Abstract

method for forming a bit line structure for an HL memory device in two sentences (A, B) of bit lines alternately as the first bit line (22A) and as a second bit line (22B) in such a way that adjacent bit lines different sentences are assigned and in different, horizontally staggered Layers are arranged, with over the memory cells an insulating material (1) is deposited, in this contact holes (2) for Etched bit line contacts then, in the escape of the contact holes (2) parallel damascene trenches in the etched insulating material be and conductive with this Material (4) to be filled up, around a plurality of parallel bit lines (22), characterized in that damascene trench only for every second Bit line (22A) are provided, then one for the following Production of the first and second bit lines common metal layer is deposited and then the metal layer at least over the damascene trenches Will get removed.

Description

The present invention relates to a method of forming a bit line structure for a HL memory device in two sets of bit lines alternately as a first bit line and a second bit line such that adjacent bit lines are assigned different sets and are arranged in different horizontally offset planes. In this case, an insulating material is deposited over the memory cells, into which contact holes are etched for bit line contacts, then etched in the alignment of the contact holes parallel damascene trenches in the insulating material and filled with conductive material to form a plurality of mutually parallel bit lines. Such a method is known from US 2004/0140569 A1 known.

at various types of memory devices, such as DRAMs, becomes the state of charge of capacitors in the memory cells used to store information. Access to the information over Word lines which the gate electrodes of the cell transistors connect, as well as over Bit lines connecting the source / drain diffusion regions. The signal, which when reading the data from the cell is dependent on the relationship the cell capacity to the capacity the bit line (BL) used to access the cell.

Of the large part the BL capacity is on the coupling capacity attributed between adjacent bit lines. In conventional Designs, the bitlines are at the same level, i. adjacent bitlines are in the same plane. Thus, the capacitive coupling between adjacent be bit lines proportional the height times the length divided by the distance of the bit lines.

Various approaches have been proposed to improve the ratio of cell capacitance to BL capacitance, and thus the readout signal. One possibility is to increase cell capacity. Furthermore, it has been proposed to shorten the bit lines, to increase the distance between the bit lines or to arrange material with a low dielectric constant between the bit lines (eg DE 1 02004 002 659 A1 ). All these approaches are associated with a significantly higher complexity of the process management and / or they are at the expense of the chip size. Another prior art proposal involves reducing the thickness of the bitlines, disadvantageously resulting in a higher BL resistance.

From the DE 44 33 695 A1 For example, various embodiments of a folded bit line structure for reducing coupling noise are known in which first and second bit lines are located in part on different horizontal planes, merged in part and intersecting in part in three dimensions. A manufacture not disclosed therein is conventionally possible in a complicated process with numerous lithography steps.

The US 2004/0140569 A1 also discloses a structure in which first and second wiring lines are formed in different layers, each offset from each other and partly made of different materials. As possibilities for the production of the same, the RIE etching and, alternatively, the damascene technique are mentioned, wherein the first and the second wiring harness are formed successively in two analogous process runs.

It will continue to look for new approaches to improve the relationship from cell capacity to bit line and thus sought to improve the readout signal.

task The invention therefore is the capacitive coupling between two significantly reduce adjacent bitlines without causing a larger space requirement for the Circuit is created.

These Task is according to the invention with a A method for forming a bit line structure solved at the over the memory cells an insulating material is deposited, in this contact holes for bit line contacts etched then, in the flight of the vias, parallel damascene trenches into the insulating material to be etched and these with conductive Material to be replenished, around a plurality of parallel bit lines form, wherein the method is characterized in that the parallel bit lines in two successive different Lithography steps in two sentences of bitlines alternately as first bitline and second Bit line be formed in such a way that adjacent Bit lines of different sentences are assigned and in different, horizontal to each other staggered levels are arranged, with only the first set of Bit lines are formed using the damascene technique and then the second set of bitlines in one above the first Bit lines lying horizontal plane is formed.

After the etching of the contact holes, the method according to the invention may advantageously comprise the following steps: forming a photomask over the entire structure in such a way that only strips for the first bit lines are open therein; Etching damascene trenches using the mask for the first set of bitlines; Depositing conductive material in the trenches and vias and on the entire structure surface such that the layer thickness of the conductive material above the top of the insulator material and the top of the trenches is at least equal to the desired thickness of the bitlines; Forming a photomask in such a way that only strips for the second bit lines remain closed therein; ani sotropes etching back of the unmasked conductive material up to at least the height of the insulator top.

alternative It is also possible according to the invention the etching the contact holes this first with conductive To refill material. The subsequent etching step for etching the damascene trenches can then be designed so that in this also the previously deposited conductive Material for the bit line contacts are removed into the trench. Another possibility This is the etching step for etching the damascene trenches interpreted in such a way that only removes the insulator material in this is at the position of the bit line contacts the previously deposited conductive Material stops, so that this protrudes into the trenches. They stand remained bit line contacts are then in the subsequent filling the Digging with further conductive Material enclosed by this.

The Depth of the damascene trenches etched in the first lithography step should be at least the desired thickness of the bit lines correspond and preferred these exceed.

In In the latter case, it is in etching back the unmasked conductive material possible, this until below the height the insulator top back, so that the distance between the bit lines can be further increased can, without requiring more chip area needed becomes.

at the mask used to form the second bitline set corresponds to the width of the closed strips advantageously the desired width of the bit lines.

Thereby, that in the two consecutive lithography steps only each second of the bit lines is formed, which is Grid spacing in the for needed these steps Masks each twice the size, whereby the process window advantageously considerably is extended.

At a terminal edge of the memory cell array, the second photomask be provided in such a way that the first bit lines remain masked, so that at this connecting edge the tops all bitlines, the first as well as the second set the same level, what with regard to the connection to peripheral circuit for the further litigation Cheap is.

Further Features and advantages of the invention are the following detailed Description and the accompanying drawings, in where like reference numerals designate like components. It demonstrate:

1 a schematically greatly simplified plan view of a matrix of memory elements, in which the word and bit lines and the bit line contacts are shown; and the

2 to 8th a process flow for the production according to the invention of a bit line structure in two successive lithography steps, namely:
2 a sectional view taken along the line 2-2 1 by a layer of insulator material applied over the memory cells into which contact holes for bit line contacts are etched;
3 one of the 2 corresponding sectional view at a later stage in the process flow, after on the insulator material, a mask has been provided for the formation of a first set of bit lines;
4 a sectional view through the insulator layer of the 2 and 3 at a later stage of the process after trenches for a first set of bit lines have been etched into the insulator material;
5 a sectional view through the structure 4 at a later stage in the process after conductive material has been deposited;
6 a sectional view as in 5 but at a later stage of the process after a mask has been provided on the conductive material to form a second set of bitlines;
7 a sectional view of the finished formed bit line structure with two sets of bit lines on staggered horizontal planes; and
8th a sectional view at the same time of the process flow as in 6 but off along line 8-8 1 taken at a terminal edge of the memory cell array.

An embodiment of the method according to the invention for forming the bit line structure will now be described with reference to FIG 1 to 7 be explained in more detail.

1 shows a highly schematic plan view of a memory matrix in which the word lines lying parallel to each other 7 in a horizontal direction tion and parallel to each other and perpendicular to the word lines arranged bit lines 22 along with the positions of the bitline contacts below 20 are shown.

The 2 to 7 make sectional views along a plane perpendicular to the plane of the 1 The skilled worker will be aware that the arrangement of the bit line contacts 1 FIG. 3 illustrates only one exemplary embodiment of a memory element, which is given herein merely for better illustration of the invention. Other arrangements are conceivable in which the bit line contacts need not all be in the same vertical plane, but this does not affect the basic inventive concept.

7 makes a vertical section along the line 2-2 1 It can be seen that the bit lines are formed in two sets A, B, wherein the bit lines of the first set A lie on a lower horizontal plane than the bit lines of the second set B. Side by side bitlines are alternately associated with set A and set B, respectively.

Thus, the gist of the invention is to implement adjacent bitlines 22A . 22B at different levels to increase the spacing between the bitlines and thus reduce the capacitive coupling therebetween without consuming more footprint on the memory chip.

In the 2 to 7 the method according to the invention for producing such a bit line structure is illustrated. This includes a known damascene process in which conductive material for bit lines is filled into a predefined trench in an insulating material and optionally planarized.

However, according to the invention, this known method is used only for a first set A of bit lines on a first lithographic plane. This is after the conventional etching of contact holes 2 for the later bit line contacts 20 in an insulating layer deposited over the memory cells 1 above this a mask 3 applied from photoresist and patterned such that stripes at the positions of a future first set A of bitlines (every other of the future bitlines 22 ). The width of the openings corresponds to the desired width of the bit lines, ie the minimum feature size of the technology in question. The raster width of the bit lines here is twice as large as usual.

In the places where the mask 3 open, are now digging according to the conventional Damascene method 21 in the insulator 1 etched ( 4 ). The trench depth should be slightly larger than the target thickness d of the bit lines 22 be (d + x).

After that ( 5 ) becomes conductive material 4 for the bitlines 22 deposited. This should be the contact holes 2 and the etched trench 21 and, moreover, are deposited in a thickness equal to the desired thickness of the second set of bit lines to be formed 22B equivalent. To form a more level surface, a thicker deposit and a subsequent planarization step could also be considered.

The formation of the second set of bitlines 22B now takes place in a second lithography step on a second lithography level. This will be another photoresist mask 5 on the conductive bit line material 4 deposited and patterned such that stripes at the positions of the future second bitlines 22B (each between the first sentence 22A ) stay closed ( 6 ). The width of the closed strips of the mask 5 corresponds to the nominal width of the bit lines 22 ie the minimum feature size of the technology concerned. The raster width of the bit lines is thus twice as large as usual, as in the first lithography step, whereby the process window is considerably expanded.

Last ( 7 ) will not do that with the mask 5 masked conductive material 4 etched back, at least up to the top 11 of the insulator 1 and preferably until just below this.

The result of this process flow are two sets of bit lines 22A . 22B wherein adjacent bitlines are spaced greater apart than would be the case if they were in the same plane. As a result, the coupling between the bit lines is reduced. The first (lower) set A of bitlines will have a slightly higher capacitive coupling to the bitline contacts 20B the second set of bitlines 22B demonstrate. But this becomes clear by reducing the coupling between the bit lines 22A . 22B outweighed each other.

Note that the shortest diagonal distance between the two sets A, B of bitlines is determined by the degree of overetch in the final process step in conjunction with the trench depth d + x of the etched trenches 20 can be adjusted. Increased overetching increases this distance and thus reduces the capacitive coupling of adjacent bitlines.

7 make a cut through the finished However, at the edge of the memory cell array, for a suitable connection to peripheral circuitry, it is advantageous to provide the pads of all the bitlines on the same plane. This can be realized, for example, in that in connection with 6 described process step the mask 5 at the terminal edge of the memory cell array as in the sectional view 8th is provided is shown, so at this point, the bit lines 22A remain masked so that in the finished structure the tops of all the bitlines at the edge of the memory cell array come to lie on the same plane.

The basis of the 2 to 8th The described process merely represents one possible embodiment of the inventive method for forming a bit line structure with two bit line sets arranged in different planes.

Alternatively, for example, the contact holes 2 also before the first lithography step with conductive material 4 filled to bit line contacts 20A . 20B train. The subsequent process flow then takes place in a similar way as described above. When etching the trench 21 could that before in the contact holes 2A deposited conductive material 4 be removed so that continuous open ditches arise. Another possibility would be to design the etching step such that it is already in the contact holes 2A deposited conductive material 4 not be etched away with. The contacts would thus remain protruding into the trench, of which later in the trench 21 deposited conductive bit line material to be enclosed.

The Invention thus offers a possibility with a little bit more complex process flow the capacitive coupling between adjacent ones To reduce bitlines in a HL memory device without this is at the expense of the chip size.

1

insulating material

11

top of the insulating material

2 (A, B)

Contact holes for bit line contacts of the 1st or 2nd set of bit lines

20 (A, B)

Bit line of the 1st or 2nd set of bit lines

21

etched trenches for the 1st Bitleitungssatz

22 (A, B)

1. or 2nd set of bit lines

3

mask for first lithography step

4

conductive material

5

mask for second lithography step

7

word lines

d

target thickness the bitlines

Claims (9)

A method for forming a bit line structure for a HL memory device in two sets (A, B) of bit lines alternately as a first bit line ( 22A ) and as a second bit line ( 22B ) in such a way that adjacent bit lines are assigned to different sets and are arranged in different, mutually horizontally offset planes, wherein an insulating material ( 1 ) is deposited in this contact holes ( 2 ) are etched for bit line contacts, then in alignment with the contact holes ( 2 ) parallel damascene trenches are etched into the insulating material and these are coated with conductive material ( 4 ) are filled to form a plurality of bit lines ( 22 ), characterized in that damascene trenches only for every second bit line ( 22A ), after which a metal layer common to the subsequent production of the first and second bit lines is deposited and subsequently the metal layer is removed at least over the damascene trenches. Method according to Claim 1, characterized in that, after the etching of the contact holes ( 2 ) comprises the following steps: - forming a photomask ( 3 ) over the entire structure in such a way that in this only strips for the first bit lines ( 22A ) are open; - etching damascene trenches ( 21 ) with the help of the mask ( 3 ) for the first set of bitlines ( 22A ); Deposition of conductive material ( 4 ) in the ditch ( 21 ) and the contact holes ( 2 ) and on the entire structure surface in such a way that the layer thickness of the conductive material ( 4 ) above the top ( 11 ) of the insulator material ( 1 ) and the top of the trenches ( 21 ) corresponds to at least the desired thickness (d) of the bit lines; Forming a photomask ( 5 ) in such a way that in this only strips for the second bit lines ( 22B ) stay closed; Anisotropic etching back of the unmasked conductive material ( 4 ) to at least the height of the insulator top ( 11 ). Method according to Claim 1, characterized in that, after the etching of the contact holes ( 2 ) comprises the following steps: - filling the contact holes ( 2 ) with conductive Ma material ( 4 ) for the formation of bit line contacts ( 20A . 20B ); Forming a photomask ( 3 ) over the entire structure in such a way that in this only strips for the first bit lines ( 22A ) are open; - etching damascene trenches ( 21 ) with the help of the mask ( 3 ) for the first set of bitlines ( 22A ); Deposition of conductive material ( 4 ) in the ditch ( 21 ) and on the entire structure surface in such a way that the layer thickness of the conductive material ( 4 ) above the top ( 11 ) of the insulator material ( 1 ) and the upper edge of the trench ( 21 ) corresponds to at least the desired thickness (d) of the bit lines; Forming a photomask ( 5 ) in such a way that in this only strips for the second bit lines ( 22B ) stay closed; Anisotropic etching back of the unmasked conductive material ( 4 ) to at least the height of the insulator top ( 11 ). A method according to claim 3, characterized in that the etching step for etching the damascene trenches ( 21 ) is designed such that in this also the previously deposited conductive material ( 4 ) for the bit line contacts ( 20A . 20B ) is removed in the trenches. A method according to claim 3, characterized in that the etching step for etching the damascene trenches ( 21 ) is designed such that in this only the insulator material is removed, wherein at the position of the bit line contacts ( 20A ) the previously deposited conductive material ( 4 ) stops, so this into the ditch ( 21 protruding bit line contacts ( 20A ) in the subsequent step of filling the trench ( 21 ) with further conductive material ( 4 ) are enclosed by this. Method according to one of claims 1 to 5, characterized in that the depth of the damascene trenches ( 21 ) at least the desired thickness (d) of the bit lines ( 22A ) corresponds. A method according to any one of claims 1 to 6, characterized in that in the step of etching back the conductive material not forming the second bit lines ( 4 ) this to below the height of the insulator top ( 11 ) is etched back. Method according to one of claims 1 to 7, characterized in that the width of the in the mask ( 5 ) closed strips of the nominal width of Bitlei lines ( 22B ) corresponds. Method according to one of claims 2 to 8, characterized in that the photomask ( 5 ) is formed at a terminal edge of a memory cell array of the semiconductor memory device in such a way that the first bit lines ( 22A ) remain masked, so that at this connection edge the tops of all bit lines, the first as well as the second set ( 22A . 22B ), be formed in the same plane.