DE102004033980A1 - Control of an electrical load such as a light emitting diode has load current measured and compared with reference - Google Patents

Abstract

Connected between the terminals [2,3] are a current sensing resistor [R] and a load stage [10]. The sensed value is compared [7] with a reference [Uref] to generate an error value [UD] that is then used as input to a drive amplifier [8] that controls the load.

Description

The The invention relates to a method and a circuit arrangement for driving a load, e.g. a light emitting diode (LED), with an electric current.

A classical method or circuitry around a load, e.g. a LED, to drive with a predetermined amperage consists in the series connection of a preferably ohmic resistor to Load. This solution only works reliably, when the voltage drop across the load and the voltage of the power source are constant. However, this is not true in most cases to. A higher one Source voltage leads to a higher amperage and a higher one Power loss in the load, which in turn with a reduced Lifetime of the load is connected. In the case of an LED as a load leads one changed amperage about that out to a non-consistent brightness.

From the EP 0 707 255 A1 or the US 5,966,110 are known for driving LED power generators, which are based on a reflection of an internal constant and compensated current. However, these controls are very inaccurate due to the thermal offset. This problem is even greater when used for current mirroring bipolar junction transistors (BJTs), which have a high temperature sensitivity. For example, temperature differences of about 10 Kelvin between the current measuring cell and the power cell lead to a control error of more than 100%. In particular, base currents and parasitic substrate currents also contribute to the inaccuracy.

The US 2002/0140380 A1 describes a pulsed current generator as Control circuit for an LED array. This pulsed current generator is at a medium amperage operated, a limitation of current peaks to a maximum current strength finds not happening. This has a negative effect on the service life of the load out.

All The current control circuits described above require more than two terminals. Are these current control circuits on a Silicon chip realized, so need a comparatively large one Chip area, which in turn is a big one Pack volume requirement and consuming contacting is connected. About that In addition, these variants can be not simply as a two-pole in series with the load to be controlled, because at least one supply voltage connection and in some cases also connections to external components must be provided.

The The object of the invention is therefore a circuit arrangement to introduce for controlling a load with an electric current, which optionally as a dipole in series with the load to be controlled can be switched. About that In addition, a method or a circuit arrangement is presented be, which or which also comparatively strongly different Input voltages or large Voltage fluctuations with high accuracy a constant current supplies.

These The object is achieved by a method having the features of the patent claim 1 or by a circuit arrangement with the features of the claim 6 solved.

advantageous versions and further developments of the invention are specified in the subclaims.

Accordingly, according to the invention a method or a circuit arrangement is provided in which or formed at the corresponding means an error signal which is a measure of the difference a voltage drop across an impedance arranged in series with the load and a reference voltage. An electric current for the load providing power level is driven by the error signal.

The Invention provides a solution ready, which above a certain minimum voltage a constant electrical power supplies. The determination of the load driving Electricity is achieved by placing it in line with the load arranged impedance dropping voltage to a predetermined Value is adjusted. When the circuit arrangement according to the invention, such in the embodiments described below, on a Semiconductor (preferably silicon) chip is arranged so can the impedance may be integrated into the chip or as a separate (e.g. discrete) component outside be arranged of the chip. When using an internal impedance let yourself perform the circuit as a two-terminal without additional connections, if the constant reference voltage between the two terminals of the Zweipol's declining voltage is generated.

Of the Advantage of the invention is that the two-terminal without additional Lines, circuit arrangements or other components in series can be switched to the load. The circuit arrangement according to the invention delivers a constant current, reducing the life of the load elevated and in the case of an LED or a light emitting diode array as a load a constant brightness is generated.

The constant amperage is using egg Fixed circuit which compares the voltage drop at the connected in series to the load, hereinafter referred to as the measuring impedance impedance with a fixed constant reference voltage. As comparator, a comparator or differential amplifier is preferably provided.

The generated by the comparator (differential amplifier) Differential voltage is according to the invention used to control a Trei berstufe, which in turn the downstream aforementioned power level controls. The power stage can as well as differential amplifier, reference voltage source and driver stage, for example, in MOS (acronym for Metal Oxide Semiconductor), DMOS (Acronym for Diffusion Metal Oxide Semiconductor) or BJT (acronym for Bipolar junction transistor) technology. The performance level provides the high current to drive the load. The advantage of a preferably used high loop gain (English: loop gain) is in achieving a high control accuracy even with comparatively high temperature fluctuations and input voltage fluctuations, further tolerances of the individual components of the circuit arrangement and mismatches the individual components of the circuit arrangement.

Of the Advantage of the use according to the invention the power level alone guarantees the provision of the load current a higher one Degree of accuracy compared to above-described solutions according to the state the technique where a power stage is used as a current mirror becomes. The inaccuracy of using the power stage as a current mirror lies in component mismatches as well as in temperature gradients based on the chip. They lead to different warming of the sense transistor relative to the power transistor. At the present solution scattering of the components due to the two voltages are comparative Circuit less significant. The accuracy of the load current is in the present case according to the invention only by the accuracy of the measuring impedance and the set Reference voltage determined. Very high accuracies can be achieved when the impedance (preferably, a pure ohmic resistance used) is adjustable. The term adjustable includes a trim one realized on a common chip (internal) Impedance (in particular an ohmic resistance).

Farther is it for a high setting accuracy of the load current is essential that the entire current flowing through the load over the (preferably ohmic) resistor flows and thus from the circuit is controlled. These include in particular (which in the realization of the circuit arrangement a chip is to be considered) also supply, rest, base and Substrate currents. In the case of one on the BJT technology level of control are inaccurate due to base and / or substrate currents avoided.

Furthermore the adjustment accuracy of the load current can thereby be increased, in that the (preferably ohmic) resistor and the means for generating the reference voltage are designed such that they are identical Have temperature behavior. Approximately let yourself achieve this by making the relevant components predominantly Operating temperature range of interest identical temperature coefficient exhibit.

According to the invention is further provided that the power supply (this includes a power supply Of course with a) single or (as already indicated above) preferably of all individual components not over an external source takes place, but that within the two-pole itself a corresponding voltage supply device (power supply device included) is provided. A simple realization possibility is that the comparator and / or the driver stage and / or the means for generating the reference voltage from the power stage with a supply voltage be supplied.

It is known to be (over a large temperature range) constant currents much easier to generate than constant voltages. The Temperature behavior of an acted upon by a constant current Ohmic resistance dropping voltage can be very accurate predetermine. The invention therefore provides that the tel with for generating the reference voltage (hereinafter simplicity half referred to as a reference voltage source) means for generating a reference current and an ohmic resistance, over the the reference current flows, so that the reference voltage drops at the ohmic resistance. On this way, the temperature behavior of the reference voltage source and the measuring resistance comparatively easily adapted to each other what is set (as stated above) for precise tuning of the load current is essential is.

there it has to be cheap proved the amperage the reference current for loss minimization (preferably at least an order of magnitude smaller as the current of the load current to choose.

Furthermore, the invention provides ver to the reference current to polarize the comparator turn. This has the advantage that then the bias current of the comparator itself can generate the desired reference voltage.

A particularly advantageous embodiment The invention looks over it In addition, an overtemperature protection device and optionally also an overload protection device (in the Anglo-Saxon This literature is referred to as SOA protection, where SOA is one Acronym for safe operation area = safe area).

The Invention will now be described with reference to the drawing. Show it:

• a) ein Blockschaltbild eines Schaltkreises mit beliebiger Last
• b) eine prinzipielle Laststrom-Batteriespannungs-Kennlinie
• c) ein Blockschaltbild eines Schaltkreises mit LED als Last

1 an arrangement of a bipolar circuit arrangement according to the invention in a battery-operated circuit with load

• a) a block diagram of a circuit with any load
• b) a principal load current battery voltage characteristic
• c) a block diagram of a circuit with LED as a load

2 a block diagram of a first embodiment of an inventive designed as a two-terminal circuit arrangement

3 a block diagram of a second embodiment of an inventive designed as a two-terminal circuit arrangement

• a) Referenzspannungsquelle als Kombination einer ersten Teilreferenzspannungsquelle mit positivem Temperaturkoeffizienten und einer zweiten Teilreferenzspannungsquelle mit negativem Temperaturkoeffizienten
• b) Referenzspannungsquelle basierend auf einer einem ohmschen Widerstand einen Konstantstrom aufprägenden Referenzstromquelle, welche wiederum als Kombination einer ersten Teilreferenzstromquelle mit positivem Temperaturkoeffizienten und einer zweiten Teilreferenzstromquelle mit negativem Temperaturkoeffizienten ausgebildet ist
• c) Schaltungstechnische Realisierung der Referenzstromquelle

4 a section of the block diagram according to the 2 from which it can be seen in which way a reference voltage source can be realized in concrete terms by way of example

• a) reference voltage source as a combination of a first partial reference voltage source with a positive temperature coefficient and a second partial reference voltage source with a negative temperature coefficient
• b) Reference voltage source based on a reference current impressing a reference current source, which in turn is formed as a combination of a first partial reference current source with a positive temperature coefficient and a second partial reference current source with a negative temperature coefficient
• c) circuit realization of the reference current source

5 a section of the block diagram according to the 2 from which the circuit realization of a differential amplifier, a driver stage and a power level can be seen

6 an overtemperature protection device for a circuit arrangement according to the invention

7 an overload protection device for a circuit arrangement according to the invention

8th a circuit realization of a circuit according to 2 , which is suitable for very low voltage drops at a measuring resistor.

As detailed above has been, a circuit arrangement according to the invention can there be used, where a Ansteuerbaustein is needed, which Guaranteed a precise current, thermally compensated, one constant current over one provides wide input voltage range and on the only one low voltage drops. The circuit arrangement can be designed as a two-terminal, which directly can be arranged in series to a load.

The 1 shows a typical implementation of a circuit arrangement according to the invention 1 as well as the associated current-voltage characteristic. In particular, the shows 1a a block diagram of a circuit with load. The circuit is powered by a battery 5 powered by a battery voltage U _Batt . The battery 5 a current I is taken, which is the load 4 feeds and which of the series in the load 4 arranged circuit arrangement according to the invention 1 is regulated to a constant value. The circuit arrangement 1 is designed as a bipolar whose terminals in the 1a with the reference number 2 and 3 Marked are.

The 1b shows a principal load current I battery voltage U _Batt characteristic. It can be seen from this characteristic curve that the load current intensity I supplies a substantially constant load current intensity I _sat after exceeding a certain minimum battery voltage U _{Batt, min} .

For completeness, the shows 1 the preferred use of the bipolar formed as a circuit arrangement according to the invention 1 as a driving device of a light emitting diode 6 , According to the is in the 1c instead of in the 1a provided symbol for the load 4 a symbol of a light emitting diode 6 used.

The 2 and 3 show block diagrams of two embodiments of inventive circuit arrangements 1 , Both bipoles (terminals 2 . 3 ) comprise a measuring resistor R _sense , a reference voltage source 9 , a comparator or differential amplifier 7 , a driver stage 8th as well as a performance level 10 , The measuring resistor R _sense as well as the power level 10 are in both embodiments in series with each other and thus in series with the load 4 arranged. However, both embodiments differ only in that in one case the measuring resistor R _sense the power stage 10 in the other case the power level 10 is downstream.

The power level 10 facing terminal terminal of the resistor R _sense is connected to the inverting input - the comparator 7 connected. The other connection of the measuring resistor R _sense is via the voltage source 9 with the non-inverting input + of the comparator 7 connected. The output of the comparator 7 is on the entrance of the driver bank 8th whose output is in turn connected to a control input of the power stage 10 is guided. The above the power level 10 decreasing voltage U ₀ is in both cases as the supply voltage U _{0 of} the comparator 7 and the driver stage 8th used.

The principle of operation in the 2 and 3 illustrated circuit arrangements 1 results as follows:
At the in series to the load 4 arranged measuring resistor R _sense drops an electrical voltage U _sense . This measurement voltage U _sense is compared with that of the reference voltage source 9 generated reference voltage U _ref by means of the comparator 7 compared. At the output of the comparator 7 is a difference of the measuring voltage U _sense and reference voltage U _ref representing differential voltage signal U _D on. This difference voltage U _D is at the driver stage 8th to which this signal U _D in a corresponding to the control of the power level 10 suitable signal converts. Depending on what kind of performance level 10 is used, this control signal may be an electrical voltage or an electric current. In principle, it is also possible to provide, for example, a conversion to an optical or other signal, provided that it is used to control the power stage 10 suitable is.

Due to the arrangement of the components R _sense , 9 . 7 . 8th and 10 according to the embodiments according to the 2 respectively. 3 In each case, a control loop is formed, which endeavors to regulate the reference voltage U _ref and the measuring voltage U _sense to the same value. Since the measuring voltage U _{sense represents} the voltage drop across the measuring resistor R _sense , in this way a constant current I flowing through the measuring resistor R _{sense is} set.

The strength of the current I to be set is predetermined by a suitable choice of the measuring resistor R _sense and / or the reference voltage U _ref . The setting accuracy of the current I is therefore dependent solely on the measuring resistor R _sense and the reference voltage U _ref . In particular, it is irrelevant whether the entire circuit arrangement is implemented in bipolar transistor technology or in MOS, DMOS or other technology.

The temperature behavior of the load current I is merely a function of the temperature coefficient of the reference voltage U _ref and of the measuring resistor R _sense. It is therefore favorable to choose the respective temperature coefficients CTR _sense , CTU _ref largely identical, in order to compensate the temperature behavior of the measuring resistor R _sense and thus one to obtain independent of the temperature T load current I.

Mathematically, the preferred identical choice of the temperature coefficient CTR _{sense of} the measuring resistor R _sense and the temperature coefficient CTU _{ref of} the reference voltage U _ref results as follows:
The comparator 7 compares the reference voltage U _ref with the voltage drop U _sense at the measuring resistor R _sense . The system is in equilibrium if both voltages U _ref , U _{sense are} identical: U ref = U scythe = R scythe · I

The current I = U ref / R scythe is constant independent of the temperature T when the derivative of the current I after the temperature T is zero: dI / dT = 0 with U _{ref / T0} as a reference _voltage at room temperature T ₀ and R _{sense, T0} as a measuring resistor at room temperature T ₀ results:

It follows you ref / DT · (1 / R sense, T0 ) - (1 / R sense, T0 ) 2 - (dR scythe / DT) · U ref, TO = 0, or after simplification (you ref / DT) / U ref, T0 = (dR scythe / DT) / R sense, T0 ,

This equation _is the equation for the temperature coefficient CTU, CTR _sense of the reference voltage U _ref and the sensing resistor R _sense is, so that it can be rewritten in the following manner: CTU ref = CTR scythe

Preferably, the reference voltage source 9 as a combination of a first partial reference voltage source 9a with positive temperature coefficient CTU _{ref, PTAT} and a second partial reference voltage source 9b with negative temperature coefficient CTU _{ref, NTAT} , in order to obtain the necessary value for compensation of the temperature coefficient CTR _{sense of} the measuring resistor R _sense . This preferred embodiment takes symbolically the 4a ,

In addition, a compensation of the temperature behavior of the load can 4 . 6 be reached when the load 4 . 6 in the vicinity of the measuring resistor R _sense or the reference voltage source 9 is arranged so that temperature changes of the load 4 . 6 be included.

In a further embodiment of the invention, the reference voltage source 9 like in the 4b is shown on a resistance R _{a is} a constant current I _ref aufprägenden reference current source 12 which in turn is a combination of a first partial reference current source 12a with positive temperature coefficients CTI _{ref, PTAT} and a second partial reference current source 12b with negative temperature coefficient CTI _{ref, NTAT is} formed. The reference _currents generated with positive or negative temperature coefficients CTI _{ref, PTAT} , CTI _{ref, NTAT} are identified in the drawing _figure by the reference _symbols I _{ref, PTAT} and I _{ref, NTAT} .

Circuit technology can be a reference voltage source 9 based on an ohmic resistance R _{a is} a constant current I _ref aufprägenden reference current source 12 with first partial reference current source 12a with positive temperature coefficients CTI _{ref, PTAT} and second partial reference current source 12b with negative temperature coefficient CTI _{ref, Ntat} as in the 4c is shown realized. The partial reference current source 12a with positive temperature coefficient CTI _{ref, NTAT} is formed by a four npn transistors T1, T2, T3 and T4, a polarization resistor R _start-up and a resistor R _b comprising partial circuit. The partial reference current source 12b with negative temperature coefficient CTI _{ref, NTAT} is formed by an npn transistor T5 and a resistor R _c .

The ohmic resistance R _b must form with the resistors R _c and R _a a independent of the temperature and any product fluctuations ratio. In integrated circuits one speaks of paired resistors. The reference _{partial current} I _{ref, PTAT} with positive temperature coefficient CTI _{ref, PTAT} results in too I ref, PTAT = (U T / R b ) * Ln (N) where U _{T is} the temperature voltage U _T = kT / q and N is the emitter area of the transistor T4 in relation to those of the transistors T1 to T3.

The partial reference current I _{ref, NTAT} with negative temperature coefficient CTI _{ref, NTAT is} calculated to I ref, NTAT = U be / R c . wherein U _be about the emitter voltage at the transistor T3. To achieve high accuracy, the resistors R _a , R _b , R _{c must be} in strict relation to each other. For ICs, the geometry is exactly the same or equal parts; the situation is the same; the temperature is the same, because the resistances are close to each other.

The reference voltage U _ref is thus given U ref = (R a / R b ) · U T Ln (N) + (R a / R c ) U be

The resistance ratios R _a / R _b and R _a / R _c must be chosen so that the above temperature coefficient equation, namely CTU ref = CTR scythe is satisfied.

As a comparator 7 is an arrangement in question, as for example in the 5 is shown. The comparator consists of three npn transistors T10, T11, T12 which provide the polarization, the two transistors T13, T14 as an input differential pair and a compensation capacitor C _comp for stabilizing the control loop. The reference _current I _ref = I _{ref, PTAT} + I _{ref, NTAT} is preferably used not only to generate the reference voltage U _{ref dropped} across the resistor R _a but also to the comparator 7 to polarize. In this way you can save an otherwise additional power source, since the power is used twice.

As a driver stage 8th In the present exemplary embodiment, an npn Darlington circuit is used, which is composed of two npn transistors T15, T16 and the emitter against coupling resistor R _D. The performance level 10 is formed in the present embodiment by a number K of parallel-connected pnp transistors, one of which is denoted by the reference symbol T17.

According to the invention, an over-temperature protection device can be provided. 6 shows an example of such a device 13 based on an npn transistor T20 and an ohmic resistance R _d . The collector of the transistor T20 is at the output of the comparator 7 connected. It is expressly pointed out sen that the temperature shutdown can of course be realized with any known threshold circuit.

In addition, an overload protection device may be provided. An example of such an overload protection device 14 is in the 7 shown. It is based in the present embodiment on two npn transistors T18, T19, which are parallel to the transistor T10 of the comparator 7 according to 5 are connected, an ohmic resistance R _e and a Zener diode 11 , The operation of this circuit 14 results as follows:
If the input voltage rises above a zener voltage U _{z of} the zener diode 11 fixed value, the current flowing through the resistor R _a reference current I _ref decreases. The reference voltage U _ref decreases and thus also the load current I.

An essential parameter is the minimum voltage drop across the two-pole (see U _{Batt, min} in 1b ). In the embodiment in 5 the critical voltage _{path is} formed by the through the base-emitter paths of the transistors T15 and T16 and the CE residual voltage U _{CESat of} the transistor T14. The drop voltage of the two-pole is so U drop = U RSense + U ce (T14) + U be (T16) + U RD ,

The minimum required voltage drop U _{drop, min} at the two-pole (between the two terminals 2 and 3 ) is U drop, min = 2 U be + U CEsat . which in the worst case means a voltage drop U _{drop, min} (worst case) of about 2V.

The 8th shows a further circuit realization of a circuit arrangement 1 after 2 , which is particularly suitable for very low voltage _drops U _drop . The operating principle of this circuit is identical to that of the circuit arrangement described above 1 after the 4 and 5 , for generating the currents I, I _ref .

The critical path contains here only a base-emitter threshold voltage and a saturation voltage, z. _{For example} : U _{be (T33)} + U _{CESat (T32)} , ie approx. 1V _drop voltage U _{drop, min (worst case)} in the worst case.

1

circuitry

2

first clamp

3

second clamp

4

load

5

battery

6

led

7

Comparator / differential amplifier

8th

driver stage

9

Reference voltage source

9a

Reference voltage source with a positive temperature

coefficients

9b

Reference voltage source with negative temperature

coefficients

10

power stage

11

Zener diode

12

Reference current source

13

Overtemperature protection scheme

14

Overvoltage switching device

T1

first transistor

T2

second transistor

T3

third transistor

T4

fourth transistor

T5

fifth transistor

T6

sixth transistor

T7

seventh transistor

T8

eight transistor

T9

ninth transistor

T10

tenth transistor

T11

eleventh transistor

T12

twelfth transistor

T13

thirteenth transistor

T14

fourteenth transistor

T15

fifteenth transistor

T16

sixteenth transistor

T17

seventeenth transistor

T18

eighteenth transistor

T19

nineteenth transistor

T20

twentieth transistor

T21

twenty first transistor

T22

twenty second transistor

T23

twenty third transistor

T24

twenty-fourth transistor

T25

twenty-fifth transistor

T26

twenty sixth transistor

T27

twenty seventh transistor

T28

twenty-eighth transistor

T29

twenty-ninth transistor

T30

thirtieth transistor

T31

thirty first transistor

T32

thirty-second transistor

T33

thirty third transistor

T34

thirty fourth transistor

CTR _sense

Temperature coefficient R _sense

CTU _ref

Temperature coefficient U _ref

CTI _ref

Temperature coefficient I _ref

R _D

Darlingtonwiderstand

C _comp

Compensation capacitor / condenser

I

load current

I _sat

Saturation load amperage

I _ref

reference current

I _{ref, PTAT}

Reference current portion with a positive temperature coefficient

coefficients

I _{ref, NTAT}

Reference current portion with negative

temperature coefficient

R _sense

ohmic measuring resistor

U _Batt

battery voltage

U _{Batt, min}

Minimum battery voltage

U ₀

supply voltage

U _ref

reference voltage

U _{ref, PTAT}

Reference voltage component with a positive temperature

coefficients

_{Uref, NTAT}

Reference voltage component with negative temperature

coefficients

U _D

differential voltage

U _sense

measuring voltage

U _be

positive Emitter of voltage

U _ce

Collector-emitter of voltage

U _drop

Voltage drop across the two-pole between the terminals 2

and 3

U _{drop, min}

minimum Drop voltage that contributes to the function of

circuit needed becomes

+

Not inverting input

-

inverting entrance

R _start-up

polarization resistance

R _a

first resistance

R _b

second resistance

R _c

third resistance

R _d

fourth resistance

R _e

fifth resistance

R _f

sixth resistance

R _g

seventh resistance

Claims (19)

Method for controlling a load ( 4 . 6 ) with an electric current (I), characterized in that an error signal is formed, which is a measure of the difference of a voltage drop (U _sense ) on one in series with the load ( 4 . 6 ) arranged impedance (R _sense ) and a reference voltage (U _ref ) and that a the electric current (I) providing power level ( 10 ) is driven by the error signal. A method according to claim 1, characterized in that the error signal from a differential voltage (U _D ) from the voltage drop (U _sense ) at the in series to load ( 4 . 6 ) arranged impedance (R _sense ) and the reference voltage (U _ref ) is formed. Method according to claim 2, characterized in that the power level ( 10 ) via a driver stage ( 8th ), which is controlled by the differential voltage (U _D ). Method according to one of the preceding claims, characterized in that an ohmic resistance (R _sense ) is used as the impedance. A method according to claim 4, characterized in that the entire current flowing through the load (I) via the resistor (R _sense ) is guided. Circuit arrangement ( 1 ) for controlling a load ( 4 . 6 ) with an electric current (I), characterized in that one in series with the load ( 4 . 6 ) arranged impedance (R _sense ) is provided, at which an electrical voltage (U _sense ) drops, that means ( 9 . 9a . 9b ; 12 , R _a ) are provided for generating a reference voltage (U _ref ), that means ( 7 . 8th ) are provided which form an error signal which is a measure of the difference of the voltage drop (U _sense ) in series with the load ( 4 . 6 ) arranged impedance (R _sense ) and the reference voltage (U _ref ) and that one of the error signal controlled power stage ( 10 ) is provided which the electrical current (I) for the load ( 4 . 6 ). Circuit arrangement ( 1 ) according to claim 6, characterized in that a comparator ( 7 ) is provided, which as a fault signal, a differential voltage (U _D ) from the voltage drop (U _sense ) in series to the load ( 4 . 6 ) arranged impedance (R _sense ) and the reference voltage (U _ref ) forms. Circuit arrangement ( 1 ) according to claim 7, characterized in that one of the differential voltage (U _D ) driven driver stage ( 8th ), which determines the power level ( 10 ). Circuit arrangement ( 1 ) according to one of claims 7 or 8, characterized in that the comparator ( 7 ) and / or the driver stage ( 8th ) and / or the funds ( 9 . 9a . 9b ; 12 , R _a ) for generating the reference voltage (U _ref ) from the power stage ( 10 ) are supplied with a supply voltage (U ₀ ). Circuit arrangement ( 1 ) according to one of claims 6 to 9, characterized in that the impedance is an ohmic resistor (R _sense ). Circuit arrangement ( 1 ) according to claim 10, characterized in that the value of ohm rule resistance (R _sense ) is adjustable. Circuit arrangement ( 1 ) according to claim 10 or 11, characterized in that the whole by the load ( 4 . 6 ) flowing current (I) via the ohmic resistance (R _sense ) flows. Circuit arrangement ( 1 ) according to one of claims 10 to 12, characterized in that the ohmic resistor (R _sense ) and the means ( 9 . 9a . 9b ; 12 , R _a ) for generating the reference voltage (U _ref ) have an identical temperature coefficient (CTR _sense , CTU _ref ). Circuit arrangement ( 1 ) according to one of claims 10 to 13, characterized in that the means ( 9 . 9a . 9b ; 12 , R _a ) for generating the reference voltage (U _ref ) means ( 12 , R _a ) for generating a reference current (I _ref ) and an ohmic resistance (R _a ) include, over which the reference current (I _ref ) flows, so that at the ohmic resistance (R _a ), the reference voltage (U _ref ) drops. Circuit arrangement ( 1 ) according to claim 14, characterized in that the current strength of the reference current (I _ref ) is at least an order of magnitude smaller than the current intensity of the load current (I). Circuit arrangement ( 1 ) according to claim 14 or 15, characterized in that the reference current (I _ref ) the polarizing current of the comparator ( 7 ). Circuit arrangement ( 1 ) according to one of claims 6 to 16, characterized in that an over-temperature protection device ( 13 ) is provided. Circuit arrangement ( 1 ) according to one of claims 6 to 17, characterized in that an overload protection device ( 14 ) is provided. Circuit arrangement ( 1 ) according to one of claims 6 to 18, characterized in that the load is a light emitting diode array ( 6 ), in particular a light-emitting diode ( 6 ).