DE102004026596A1 - Active semiconductor arrangement with at least one module plane and having a raised geometry with a conductive layer to make contact with an upper plane - Google Patents
Active semiconductor arrangement with at least one module plane and having a raised geometry with a conductive layer to make contact with an upper plane Download PDFInfo
- Publication number
- DE102004026596A1 DE102004026596A1 DE200410026596 DE102004026596A DE102004026596A1 DE 102004026596 A1 DE102004026596 A1 DE 102004026596A1 DE 200410026596 DE200410026596 DE 200410026596 DE 102004026596 A DE102004026596 A DE 102004026596A DE 102004026596 A1 DE102004026596 A1 DE 102004026596A1
- Authority
- DE
- Germany
- Prior art keywords
- power semiconductor
- semiconductor device
- geometry
- plane
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09045—Locally raised area or protrusion of insulating substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/0969—Apertured conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10272—Busbars, i.e. thick metal bars mounted on the PCB as high-current conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Die Erfindung betrifft eine Leistungshalbleiteranordnung mit mindestens einer Modulebene, bestehend aus einem Träger und auf dem Träger angeordneten Leistungshalbleitern, und mindestens einer weiteren, mit Abstand oberhalb der Modulebene angeordneten Ebene, insbesondere einer Busbarebene, wobei mindestens eine elektrische Verbindung zwischen der Modulebene und der oberen Ebene vorgesehen ist.The The invention relates to a power semiconductor device having at least a module level, consisting of a carrier and arranged on the carrier Power semiconductors, and at least one other, by far above the module level arranged plane, in particular a Busbarebene, wherein at least one electrical connection between the module level and the upper level is provided.
Bei der elektrischen Verbindung kann es sich beispielsweise um einen Hochstromkontakt oder einen Signalkontakt handeln. An die elektrischen Verbindungen werden je nach Anwendungsfall die unterschiedlichsten Anforderungen gestellt. Insbesondere ist bei Hochstromkontakten auf einen möglichst geringen elektrischen Widerstand zu achten, um die Eigenerwärmung der elektrischen Verbindung zu minimieren. Die mechanische Stabilität und Haltbarkeit sowie die elektrische Leitfähigkeit haben Einfluss auf die Güte einer elektrischen Verbindung. Je nach Einsatzgebiet muss die elektrische Verbindung Vibrationen, Temperaturänderungen oder sonstigen Umwelteinflüssen standhalten.at The electrical connection may be, for example, a High current contact or a signal contact act. To the electrical Connections will vary depending on the application Requirements made. In particular, in high-current contacts on one as possible low electrical resistance to pay attention to the self-heating of the minimize electrical connection. The mechanical stability and durability as well the electrical conductivity have an influence on the quality an electrical connection. Depending on the application, the electrical Connection vibration, temperature changes or other environmental conditions withstand.
Zur Herstellung einer elektrischen Verbindung zwischen beispielsweise einem Printed Circuit Board (PCB) und einem Leistungshalbleitermodul ist es bekannt, Zusatzelemente wie Metallstifte, Bügel, Bonddrähte, etc. einzusetzen. Mit Hilfe dieser Zusatzelemente wird der Abstand zwischen dem PCB und dem Leistungshalbleitermodul überwunden und ein elektrischer Kontakt hergestellt. Die Zusatzelemente werden einerseits am PCB und andererseits an dem Leistungshalbleitermodul befestigt. Bekannte Techniken hierzu sind Löten, Schweißen, Verkleben, Verschrauben oder Einspritzen, etc. Bei den bekannten Technologien ist nachteilig, dass die Zusatzelemente häufig den äußeren Belastungen, wie Vibrationen oder Temperaturschwankungen nicht standhalten. In Extremfällen kann es zu Kontaktabrissen kommen. Weiterhin nachteilig ist, dass die Be festigung der Zusatzelemente an den unterschiedlichen Ebenen technisch aufwändig und zeitintensiv ist.to Making an electrical connection between, for example a printed circuit board (PCB) and a power semiconductor module it is known, additional elements such as metal pins, hangers, bonding wires, etc. use. With the help of these additional elements, the distance between overcome the PCB and the power semiconductor module and an electrical Contact made. The additional elements are on the one hand on the PCB and on the other hand attached to the power semiconductor module. Known Techniques for this are soldering, Welding, Gluing, screwing or injecting, etc. In the known technologies is disadvantageous that the additional elements often the external loads, such as vibrations or Temperature fluctuations can not withstand. In extreme cases can it comes to contact breaks. Another disadvantage is that the Be fastening the additional elements at the different levels technically costly and time consuming.
Der Erfindung liegt die Aufgabe zugrunde, eine Leistungshalbleiteranordnung vorzuschlagen, die einerseits widerstandsfähiger und andererseits einfacher herstellbar ist.Of the Invention is based on the object, a power semiconductor device to propose, on the one hand more resilient and on the other hand simpler can be produced.
Diese Aufgabe wird dadurch gelöst, dass die elektrische Verbindung aus einer, in den Träger eingeformten und gegenüber einer Trägeroberfläche erhöhten, Geometrie, zur zumindest teilweisen Überwindung des Abstandes zwischen Modulebene und oberer Ebene, besteht, wobei die erhöhte Geometrie zumindest teilweise mit einer elektrisch leitenden Schicht zur Herstellung eines elektrischen Kontakts mit der oberen Ebene, versehen ist. Bei der erfindungsgemäßen Leistungshalbleiteranordnung ist von entscheidendem Vorteil, dass auf die bisher üblichen Zusatzelemente zur Herstellung einer elektrischen Verbindung wie beispielsweise Metallstifte, Bügel, Bonddrähte, etc. verzichtet werden kann. Auf einer Modulebene können selbstverständlich eine Vielzahl von erhöhten Geometrien vorgesehen sein. Dabei ist es möglich, die erhöhten Geometrien in unterschiedlichen Höhen zu realisieren, um mehrere, übereinander angeordnete, Ebenen verbinden zu können.These Task is solved by that the electrical connection of one, molded into the carrier and opposite a carrier surface increased, geometry, for at least partial overcoming the distance between the module level and the upper level, where the increased Geometry at least partially with an electrically conductive layer for making an electrical contact with the upper level, is provided. In the power semiconductor device according to the invention is of crucial advantage that on the usual Additional elements for making an electrical connection such for example, metal pins, hangers, Bonding wires, etc. can be dispensed with. On a module level, of course, a variety from elevated Geometries be provided. It is possible, the increased geometries at different heights to realize, to several, one above the other arranged to be able to connect planes.
Gemäß einer vorteilhaften Ausgestaltung der Erfindung ist vorgesehen, dass der Träger aus einem elektrisch leitenden Material, beispielsweise Aluminium, besteht. Um einen Kurzschluss zu vermeiden, ist zwischen der elektrisch leitenden Schicht und der erhöhten Geometrie eine Isolationsschicht vorgesehen. Die Isolationsschicht kann beispielsweise direkt aus dem Trägermaterial durch einen Oxidationsprozess hergestellt werden. Auf die Isolationsschicht kann dann eine elektrisch leitende Schicht zur Herstellung der eigentlichen elektrischen Verbindung aufgebracht werden. Eine weitere Möglichkeit zur Herstellung der Isolationsschicht besteht darin, dass auf die erhöhte Geometrie unmittelbar eine Isolationsschicht aufgetragen wird. Es ist auch denkbar, auf das Trägermaterial eine Metallschicht aufzubringen, die dann mittels eines Oxidationsprozesses in eine Isolationsschicht umgewandelt wird. Unabhängig von der Art der Herstellung der Isolationsschicht wird nach deren Fertigstellung eine Metallschicht zur eigentlichen Kontaktierung der oberen Ebene auf die Isolationsschicht aufgebracht.According to one advantageous embodiment of the invention it is provided that the carrier made of an electrically conductive material, for example aluminum, consists. To avoid a short circuit is between the electric conductive layer and the raised Geometry provided an insulation layer. The insulation layer can, for example, directly from the substrate by an oxidation process getting produced. On the insulation layer can then be an electrical applied conductive layer for producing the actual electrical connection become. One more way for the preparation of the insulating layer is that on the increased Geometry directly an insulation layer is applied. It is also conceivable on the carrier material to apply a metal layer, which then by means of an oxidation process is converted into an insulating layer. Independent of Type of production of the insulation layer is after their completion a metal layer for the actual contacting of the upper level applied to the insulation layer.
In Weiterbildung der Erfindung ist mit Vorteil vorgesehen, dass der Träger aus einem elektrisch nicht leitenden Material besteht. In diesem Fall ist es nicht notwendig, auf die erhöhte Geometrie eine zusätzliche Isolationsschicht aufzubringen. Die elektrisch leitende Schicht kann unmittelbar auf die erhöhte Geometrie aufgebracht werden.In Development of the invention is provided with advantage that the carrier consists of an electrically non-conductive material. In this Case, it is not necessary to add an extra to the increased geometry Apply insulation layer. The electrically conductive layer can be increased directly to the Geometry to be applied.
Um die Haltbarkeit der elektrischen Verbindung zu erhöhen, ist mit Vorteil vorgesehen, dass die elektrisch leitende Schicht aus mehreren Metallisierungsschichten aufgebaut ist. Dies erhöht beispielsweise den Schutz gegen Korrosion. Es ist besonders zweckmäßig, wenn in der oberen Ebene eine Bohrung oder Vertiefung zur Herstellung einer formschlüssigen Verbindung mit der erhöhten Geometrie vorgesehen ist. Dabei ist es denkbar, die erhöhte Geometrie mit leitender Schicht in der Öffnung oder Vertiefung zu verlöten. Weiterhin ist es denkbar, dass die Geometrie mit Metallschicht in die Öffnung oder Vertiefung gepresst wird. In diesem Fall kann auf einen aufwändigen Lötprozess verzichtet werden. Alleine durch das Vorsehen einer entsprechend dimensionierten Öffnung in der oberen Ebene kann ohne weitere Hilfsmittel eine zweidimensionale Verbindung zwischen oberer Ebene und unterer Ebene geschaffen werden.In order to increase the durability of the electrical connection, it is advantageously provided that the electrically conductive layer is made up of a plurality of metallization layers. This increases, for example, the protection against corrosion. It is particularly useful if in the upper level, a bore or recess for producing a positive connection with the increased geometry is provided. It is conceivable to solder the raised geometry with conductive layer in the opening or depression. Furthermore, it is conceivable that the geometry with metal layer in the opening or Ver depression is pressed. In this case, a complex soldering process can be dispensed with. Alone by the provision of a correspondingly dimensioned opening in the upper level can be created without further aids a two-dimensional connection between the upper level and lower level.
In Ausgestaltung der Erfindung ist mit Vorteil vorgesehen, dass je nach Anwendungsfall die erhöhte Geometrie als Stift oder als Pyramide oder als Noppe oder als Kegel oder als Zylinder ausgebildet ist. Selbstverständlich ist es denkbar, unterschiedliche Geometrien in einem Arbeitsschritt zu realisieren.In Embodiment of the invention is provided with advantage that ever after application, the increased Geometry as a pencil or as a pyramid or as a knob or as a cone or is designed as a cylinder. Of course, it is conceivable, different Realize geometries in one work step.
Anhand einer Zeichnung, in der mehrere Ausführungsbeispiele dargestellt sind, wird die Erfindung näher erläutert.Based a drawing, shown in the several embodiments are, the invention is closer explained.
Es zeigen:It demonstrate:
In
Bestandteil
der Modulebene
In
Bei
dem in
In
- 11
- LeistungshalbleiteranordnungA power semiconductor device
- 22
- Modulebenemodule level
- 33
- BusbarebeneBusbarebene
- 44
- elektrische Verbindungelectrical connection
- 55
- elektrisch leitender Trägerelectrical conductive carrier
- 66
- Trägeroberflächesupport surface
- 77
- erhöhte Geometrieincreased geometry
- 88th
- elektrisch leitende Schichtelectrical conductive layer
- 99
- Isolationsschichtinsulation layer
- 1010
- Leiterladder
- 1111
- Öffnungopening
- 1212
- Vertiefungdeepening
- 1313
- Isolationsschichtinsulation layer
- 1414
- Metallisierungsschichtmetallization
- 1515
- elektrisch nicht leitender Trägerelectrical non-conductive carrier
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200410026596 DE102004026596A1 (en) | 2004-06-01 | 2004-06-01 | Active semiconductor arrangement with at least one module plane and having a raised geometry with a conductive layer to make contact with an upper plane |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200410026596 DE102004026596A1 (en) | 2004-06-01 | 2004-06-01 | Active semiconductor arrangement with at least one module plane and having a raised geometry with a conductive layer to make contact with an upper plane |
Publications (1)
Publication Number | Publication Date |
---|---|
DE102004026596A1 true DE102004026596A1 (en) | 2006-03-02 |
Family
ID=35745371
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE200410026596 Withdrawn DE102004026596A1 (en) | 2004-06-01 | 2004-06-01 | Active semiconductor arrangement with at least one module plane and having a raised geometry with a conductive layer to make contact with an upper plane |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE102004026596A1 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0782765B1 (en) * | 1994-09-23 | 2000-06-28 | Siemens N.V. | Polymer stud grid array package |
DE10059178C2 (en) * | 2000-11-29 | 2002-11-07 | Siemens Production & Logistics | Method for producing semiconductor modules and module produced using the method |
DE10121970B4 (en) * | 2001-05-05 | 2004-05-27 | Semikron Elektronik Gmbh | Power semiconductor module in pressure contact |
-
2004
- 2004-06-01 DE DE200410026596 patent/DE102004026596A1/en not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0782765B1 (en) * | 1994-09-23 | 2000-06-28 | Siemens N.V. | Polymer stud grid array package |
DE10059178C2 (en) * | 2000-11-29 | 2002-11-07 | Siemens Production & Logistics | Method for producing semiconductor modules and module produced using the method |
DE10121970B4 (en) * | 2001-05-05 | 2004-05-27 | Semikron Elektronik Gmbh | Power semiconductor module in pressure contact |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8181 | Inventor (new situation) |
Inventor name: PASSE, THOMAS, 33142 B?REN, DE Inventor name: CHRISTOF, KLOS, 59581 WARSTEIN, DE |
|
8127 | New person/name/address of the applicant |
Owner name: INFINEON TECHNOLOGIES AG, 81669 MUENCHEN, DE |
|
8139 | Disposal/non-payment of the annual fee |