DE102004026108A1 - Integrated semiconductor circuit arrangement containing field effect transistor, is constructed with resistance contacting source, drain and gate - Google Patents

Abstract

A field effect transistor device (T) is constructed with a source (S), drain (D), intermediate channel (K) and insulated gate (G). A resistance (R) is constructed. This is in contact with the source, drain and/or gate. The resistor is made of 80%-100% of amorphous carbon as a layer or layered structure. Its thickness is preferably 10 nm to 100 nm and it is formed entirely or in part, using cathode beam atomization, chemical gas phase deposition or vaporization. An independent claim is included for the corresponding method of manufacture.

Description

The The present invention relates to a semiconductor integrated circuit device and a process for their preparation.

at Many semiconductor integrated circuit devices require in combination with each other field effect transistor devices and Provide resistance devices to certain functionalities of the to realize integrated semiconductor circuit arrangement. In the simplest Case, there is such a semiconductor integrated circuit device So from a field effect transistor, which with a resistive element, So an ohmic resistance, electrically linked, the latter with the transistor over its source region, drain region and / or gate region is connected.

at certain semiconductor circuit arrangements is in view of the Range of values of the ohmic resistance of the intended resistance element a particularly high dynamic, d. H. a particularly broad value range, necessary. This can be done with conventional Semiconductor materials or metallic materials difficult to realize be, especially if particularly simple processes and Structures should be used.

Of the Invention is based on the object, a semiconductor integrated circuit arrangement the aforementioned To provide a type and a corresponding manufacturing process, in which in a particularly simple and reliable way and Make the resistor device with a wide resistance range can be trained.

Is solved the task according to the invention in a Semiconductor integrated circuit arrangement by the features of independent Patent claim 1. Furthermore, the object is in a method for Producing a semiconductor integrated circuit arrangement according to the invention the features of claim 16 solved. Advantageous developments the semiconductor integrated circuit device according to the present invention Invention and method of manufacturing a semiconductor integrated circuit device according to the present Invention are each the subject of the dependent subclaims.

at the semiconductor integrated circuit device is at least one Field effect transistor device formed with a source region, a drain region, a channel region provided therebetween and one to this electrically isolated gate area. Furthermore a resistance device is formed, which is formed in contact with the source region, the drain region and / or the gate region. According to the invention, the resistance device formed with or from amorphous carbon.

It is thus a fundamental idea of the integrated invention Semiconductor circuit arrangement that the resistance device with a proportion of amorphous carbon is formed. Through this measure it is achieved that the resistance device has a value for the ohmic Resistance can be in one in comparison to the state of the Technology wide range for the ohmic resistance is.

basis Thus, the present invention is the presence of amorphous carbon in the training and structural design of the envisaged Resistance device. The resistance device must but not completely out amorphous carbon, although in special applications can be beneficial. Rather, it is also conceivable that the invention provided Resistance device only to a proportion of amorphous carbon is trained.

According to one preferred embodiment of Integrated according to the invention Semiconductor circuit arrangement, it is provided that the resistance device with an amorphous carbon content in the range of approximately 80% is trained to about 100%.

Structurally The present invention provides a particularly simple design Resistance device made of or with amorphous carbon then, if this is formed as a layer or as a layer structure. It can this is a single shift or a sequential one Plurality of single layers. The individual layers can be planar or the respective surface topography substantially compliant follow. Also can the different layers in a layer structure with a Plurality of single layers of different compositions and / or have different layer thicknesses and geometries. It is preferred that the layer or layer structure with a layer thickness in the range of 1 nm to about 10 microns is trained. In particular, an area is preferred which ranges from about 10 nm to about 100 nm.

The semiconductor integrated circuit arrangement according to the invention can be implemented in various ways and Ways may be formed completely or partially structured.

at a preferred embodiment the integrated invention Semiconductor circuit arrangement, it is provided that the resistance device partly or completely by means of cathode jet atomization is trained.

In addition and Alternatively, it may be provided that the resistance device partly or completely is formed by chemical vapor deposition.

Furthermore It may be additional or alternatively be provided that the resistance device partly or completely is formed by evaporation.

Especially profitable the resistance device with or from amorphous carbon then apply, if according to a preferred embodiment the present invention, the field effect transistor device formed the basis of at least one organic semiconductor material is.

there For example, the channel region of the field-effect transistor device can be with or be formed of an organic semiconductor material.

there In particular, it may be provided that the channel region of the Field effect transistor device formed with or from a material is from the group formed by pentacene, polythiophene and oligothiophenes.

at an alternative embodiment The invention provides that the field effect transistor device is formed as an inorganic field effect transistor device, in particular as a thin-film field effect transistor device.

there it is advantageous if the field effect transistor device on the basis of amorphous silicon is formed.

The Semiconductor integrated circuit arrangement can be used, for example, as Inverter arrangement may be formed, wherein the resistance means between the drain region of the field effect transistor device and a VDD connection region or power supply area is formed.

alternative It is conceivable that the semiconductor integrated circuit arrangement is designed as a NOR gate.

Further it is alternatively provided that the semiconductor integrated circuit arrangement is designed as a NAND gate.

The describe embodiments the semiconductor integrated circuit arrangement as an inverter arrangement, as a NOR gate or as a NAND gate can also be combined be part of a parent or singly or in combination be integrated semiconductor circuit arrangement.

One Another aspect of the present invention is the provision a method of manufacturing the semiconductor integrated circuit device.

at the method according to the invention for manufacturing a semiconductor integrated circuit device a field effect transistor device is formed with a Source region, a drain region, an interposed Channel region and one of these electrically insulated gate area. Further, a resistance device is formed, in Contact with the source region, the drain region and / or the gate region.

It is according to the invention provided that the resistance device with or from amorphous carbon is trained.

at a preferred embodiment the production process according to the invention it is provided that the resistance device with a share formed on amorphous carbon in the range of about 80% to about 100% becomes.

Further can advantageously the resistance device as a layer or layer structure may be formed.

there In particular, it is provided that the layer or layer structure the resistance device with a layer thickness in the range of 1 nm to about 10 μm is trained. Preferably, the layer thickness in the range formed from about 10 nm to about 100 nm.

The Resistance device may be partly or completely by a method the cathode jet atomization be formed.

alternative it is conceivable that the resistance device partly or completely by means of chemical Gas phase deposition is formed.

Of Furthermore, it is conceivable that for the formation of a part or the entire resistance device uses a method of evaporation becomes.

at another advantageous development of the manufacturing method according to the invention it is provided that the field effect transistor device on formed the basis of at least one organic semiconductor material becomes.

there it is conceivable that the channel region of the field effect transistor device is formed with or from an organic semiconductor material.

Especially it is conceivable that the channel region of the field effect transistor device is formed with or from a material from the group, the is formed by pentacene, polythiophenes and oligothiophenes.

at an alternative embodiment the method according to the invention it is provided that the field effect transistor device as inorganic field effect transistor device is formed, in particular as a thin film field effect transistor device.

there it is advantageous if the field effect transistor device on the basis of amorphous silicon is formed.

at another embodiment the production process according to the invention it is provided that the semiconductor circuit arrangement as an inverter arrangement is formed, wherein the resistance means between the Drain region of the field effect transistor device and a VDD connection area or a connection region of the supply voltage is formed becomes.

at another embodiment the production process according to the invention it is provided that the semiconductor circuit arrangement as a NOR gate is trained.

Conceivable it is also that, according to one another embodiment the production process according to the invention the semiconductor circuit arrangement is formed as a NAND gate.

These and other aspects of the present invention will be further explained by the following remarks:
More particularly, the invention relates to amorphous carbon layer resistors for integrated circuits based on organic field effect transistors.

FETs based on organic semiconductor layers are, inter alia for the Realization of simple analog and digital integrated circuits of interest. A significant advantage of organic transistors is the fact that the relatively low, in the production of the Transistors required temperatures (usually below about 200ºC) the production of such integrated circuits on inexpensive, allow flexible polymeric substrates.

One An essential element of integrated circuits are electrical resistances. In Digital circuits will always use resistors as load elements used when the technology is not the realization of complementary transistors allowed. This is usually the case with organic transistors, for example the case. Although organic semiconductors allow the production of p-channel field effect transistors with relatively good electrical properties, however, the realization of organic n-channel field effect transistors hampered by the rapid oxidation of most organic semiconductors. In such cases Digital circuits are using transistors only of a charge type (in the case of organic transistors using p-channel transistors) and by using resistors as Realized load elements.

In analog integrated circuits are resistors for setting the operating point, for reference voltages and especially for the compensation of nonlinear effects of the active ones Components (caused for example by feedback) imperative.

For the realization of resistances In integrated circuits there are in principle several possibilities. In digital circuits, for example, a diode-connected Field effect transistor or a field effect transistor operating in the linear region be used as a load element. However, this has to be integrated Circuit has the distinct disadvantage that the capacity of this load transistor must be at least partially reloaded at each switching operation. Furthermore have such resistances a relatively unfavorable characteristic curve compared to simple linear resistors on. For these reasons leads the realization of the load element by a simple linear (ie a "real") resistance both to a lower dynamic power consumption as well as to a higher Speed of the circuit, since such a resistor is no capacity.

For realizing "true" linear resistances in integrated circuits, it is possible, for example, to deposit a thin metal layer on the substrate and to structure it in such a way that an electrically conductive arrangement with a defined length (L), width (W) and thickness (t) From these geometric dimensions and the specific electrical resistance (ρ) of the metal, the electrical resistance of the arrangement thus defined (R = ρ · L / W / t) is obtained However, this method is only suitable for the realization of resistors up to about 10 ⁴ Ω (at most about 10 ⁵ Ω), which has a relatively low specific electrical resistance of metals (between about 1.6 μΩ cm for silver and about 40 μΩ cm for titanium). Since the electrical resistance of organic transistors is usually between about 10 ⁶ Ω and 10 ¹⁰ Ω, for the production of integrated circuits based on organic transistors resistors by about 10 ⁷ Ω to 10 ⁸ Ω required.

• – Die Erzeugung dünner Schichten des Materials auf dem Substrat muss bei Substrattemperaturen unterhalb etwa 200ºC möglich sein, um die Verwendung preiswerter, flexibler polymerer Substrate zu ermöglichen.
• – Das Material darf bei Einwirken von Luftsauerstoff, Luftfeuchtigkeit und organischen Lösungsmitteln (wie sie bei der Herstellung integrierter Schaltungen auf der Grundlage organischer Transistoren zum Einsatz kommen) seine elektrischen Eigenschaften nicht verändern.
• – Es muss möglich sein, das Material gezielt und reproduzierbar zu strukturieren, so dass sich verschieden große Widerstände mit möglichst geringen Toleranzen realisieren lassen. Die Strukturierung des Materials muss bei Substrattemperaturen unterhalb etwa 200ºC möglich sein.
• – Das Material sollte möglichst preiswert sein.

Ideal for the realization of resistors for organic integrated circuits is thus a material with a specific electrical resistance by about 10 ² Ωcm to about 10 ⁴ Ωcm. In addition, the material should meet the following requirements:

• The formation of thin layers of the material on the substrate must be possible at substrate temperatures below about 200 ° C to allow the use of inexpensive, flexible polymeric substrates.
• - The material must not change its electrical properties when exposed to atmospheric oxygen, atmospheric moisture and organic solvents (such as those used in the manufacture of integrated circuits based on organic transistors).
• It must be possible to structure the material in a targeted and reproducible manner so that resistors of different sizes can be realized with the lowest possible tolerances. The structuring of the material must be possible at substrate temperatures below about 200 ° C.
• - The material should be as cheap as possible.

In The literature is the realization of a load resistance for an integrated Circuit with organic transistors based on an electric conductive Polymers (H. Sirringhaus et al., "High-resolution inkjet printing of all-polymer transistor circuits "Science, vol. 290, p. 2123, 2000). Specifically, the use of the conductive polymer Poly (3,4-ethylenedioxythiophene) doped with polystyrene sulfonic acid described. This material, like all other conductive polymers (for example Polyaniline), several disadvantages.

The Synthesis of conductive Polymers are relatively expensive, and the materials are therefore relatively expensive and inexpensive Applications inappropriate. Furthermore is the targeted and reproducible attitude of the specific electrical resistance is very difficult with conductive polymers, since even the smallest deviations in the synthesis and doping to big changes the electrical properties of the material. Another disadvantage conductive Polymers is the instability of these Opposite materials Atmospheric oxygen and humidity; conductive polymers tend to to oxidize quickly in air, which is usually a dramatic one increase the specific electrical resistance leads. Finally, this results in the use conductive Polymers the problem of exact structuring for the purpose of generation of resistive structures with accurate and reproducible geometric Dimensions. In the literature, for example, the structuring of poly (3,4-ethylenedioxythiophene) by means of ink-jet printing (H. Sirringhaus et al., "High-resolution inkjet printing of all-polymer transistor circuits "Science, vol.290, p.22123, 2000). Although this method avoids the need for photolithographic processes, but brings a relatively large Uncertainty in the achieved width and thickness of the layer with it.

These The invention describes, inter alia, a method for deposition and patterning layers of amorphous carbon for fabrication of resistance structures for integrated circuits based on organic transistors. For the Deposition thinner Layers of amorphous carbon are a number of technical Methods, such as sputtering; physical vapor deposition ", PVD) and Chemical Vapor Deposition (CVD). In particular, that Kathodenstrahlzerstäuben and plasma assisted CVD method (for example, high-frequency CVD or RF-CVD) allowed the deposition of high quality amorphous carbon layers without the need for substrate heating. (Also the purely chemical CVD allows the production of high amorphous carbon layers Quality, However, in this method, a heating of the substrate necessary.)

The reproducible adjustment of the thickness of the carbon layers is in all of these methods with great accuracy by choice the process conditions and the process duration possible. The specific electric Resistance of amorphous carbon can be targeted over a wide range Choice of process conditions can be specified. Amorphous carbon layers are characterized by high chemical stability. In particular, the Layers stable opposite organic solvents and thus allow their structuring by means of photolithography and etching in the oxygen plasma. (The targeted structuring of the amorphous carbon layers is for the realization of resistances for integrated Circuits mandatory.)

One of the core of the invention is, inter alia, the use of amorphous carbon layers for the production of resistor structures for integrated circuits based on organic transistors, the Ab Separation and structuring of the amorphous carbon layers can be done with the methods described above. Amorphous carbon layers have a number of advantages over other materials that may be used to realize resistances in integrated circuits. Compared with resistors made of thin metal layers, amorphous carbon layers have the advantage, for example, that the resistance of the layer can be set over a much larger range, and that the realization of resistances greater than 10 ⁶ Ω or 10 ⁷ Ω is possible without difficulty. In comparison to resistors based on conductive polymers, amorphous carbon layers have a significantly higher environmental and process stability.

layers made of amorphous carbon For example, be generated by means of cathode ray sputtering. For this are in a previously evacuated vacuum reactor from a carbon target by Ignite of an argon-nitrogen plasma carbon particles knocked out, in the form of a uniformly growing Condense layer on a suitable substrate (for example, glass or polymer film).

The specific electrical resistance of the layer can be adjusted by the ratio of argon and nitrogen in the process gas, as in 5 is shown. The layer thickness is determined by the intensity of the plasma, ie z. B. on the process pressure, by the electrical power and the electrical voltage and over the duration of the deposition or the duration of the process specified.

5 shows an experimentally determined dependence of the electrical resistivity of thin amorphous carbon layers with a layer thickness of 20 nm of the composition of the process gas in the cathode jet atomizing (250 W electrical power, 60 seconds process duration).

The electrical resistance of such a layer is constant over almost the entire voltage range, which manifests itself in a linear dependence of the measured current on the applied voltage, as in the 6 and 7 is shown.

The 6 and 7 show experimentally determined dependencies of the current intensity through thin amorphous carbon layers with a layer thickness of 20 nm from the applied voltage.

6 : 50 sccm argon, 50 sccm nitrogen, 250 w electrical power, 60 seconds.

7 : 50 sccm argon, 100 sccm nitrogen, 250 W electrical power, 60 seconds.

The Structuring thinner Amorphous carbon layers, for example by means of photolithography and etching in the oxygen plasma.

1 shows the schematic cross section and 2 the equivalent circuit of an inverter as a simple digital integrated circuit consisting of an organic field effect transistor T and a resistor R of amorphous carbon. In this arrangement 1, the transistor T operates as a switch and the resistor R as a resistive load element.

8th shows the experimentally determined passage characteristic of an inverter consisting of an organic field effect transistor using pentacene as a semiconductor and a resistor. The transfer characteristic shows the correct switching behavior of the inverter, including sufficiently large small signal amplification. The small signal gain is the maximum increase in the passage characteristic.

When a possible one embodiment for the inventive method for manufacturing a semiconductor integrated circuit device Let the production of an inverter from an organic field effect transistor T and an amorphous carbon resistor R:

1st metal level:

Deposition of a thin (20 nm) layer of aluminum or titanium by means of cathode jet atomization (evacuation of the vacuum chamber to 10 ^-6 mbar, addition of the process gas argon (50 sccm), ignition of the plasma at 100 W power, process duration 1 min); Structuring of the layer by photolithography and wet chemical or plasma etching. This metal level defines the gate of the transistor and the contacts of the resistor.

2nd resistance layer:

Deposition of a thin (20 nm) amorphous carbon layer by means of cathode sputtering (evacuation of the vacuum chamber to 10 ^-6 mbar, addition of the process gases argon (50 sccm) and nitrogen (100 sccm), ignition of the plasma at 250 W power, process duration 1 min); Structuring of the carbon layer by photolithography and etching in oxygen plasma.

3. Dielectric:

Deposition of a layer of polyvinylphenol by spin-coating from an organic Lö solvents; Driving off the solvent and crosslinking the layer in a vacuum oven; Opening vias in the polyvinylphenol layer (to make connections to the contacts of the resistor and the gate of the transistor) by photolithography and oxygen plasma etching. The polyvinylphenol layer serves to isolate the organic semiconductor layer from the gate electrode (gate dielectric of the transistor) and to protect the amorphous carbon layer from the further process steps, in particular from the oxygen plasma.

4. Second metal level:

deposition a thin one (30 nm) layer of gold by thermal evaporation; structuring the layer by photolithography and wet chemical etching in an iodine-potassium iodide solution.

5. Organic Semiconductor Layer:

deposition a thin one (30 nm) layer of pentacene by thermal evaporation; structuring the layer by photolithography (using a water-soluble Photoresist) and etching in the oxygen plasma.

following The present invention will be described with reference to schematic drawings explained in more detail based on preferred embodiments.

1 is a schematic and sectional side view of a preferred embodiment of the semiconductor integrated circuit device.

2 is a schematic representation of another embodiment of the integrated semiconductor circuit arrangement according to the invention.

3 is a schematic representation of another embodiment of the integrated semiconductor circuit arrangement according to the invention.

4 is a schematic representation of another embodiment of the integrated semiconductor circuit arrangement according to the invention.

5 is a graphic representation of the dependence of the electrical resistivity of thin amorphous carbon layers (layer thickness 20 nm) on the composition of the process gas (250 W electrical power, 60 s process duration).

6 . 7 are graphs of the dependence of the electric current through thin amorphous carbon layers (layer thickness 20 nm) of the applied voltage in each case at 50 sccm argon, 250 W electric power, 60 s process duration and 50 sccm nitrogen or 100 sccm nitrogen.

8th is a graphical representation of a passage characteristic of an inverter.

following become structurally and functionally similar, comparable or equivalent Elements and structures denoted by the same reference numerals. Not in any case of their occurrence will be a detailed description repeated.

1 is a schematic and sectional side view of a first embodiment of the semiconductor integrated circuit device according to the invention 1 , This semiconductor circuit arrangement 1 is based on an underlying semiconductor material area 20 or semiconductor substrate 20 with a planar surface area 20a , On the surface area 20a a gate electrode region or gate region G is formed, which is embedded in a gate insulation region GOX. This embedding in the gate insulation region GOX results in electrical insulation of the gate region G with respect to the drain region D provided above, the corresponding source region S and the channel region K provided therebetween. The channel region K itself consists in the embodiment of FIG 1 from an organic semiconductor material. By influencing the gate region G with an electrical potential, the material of the channel region K can be modulated in its electrical resistance by influencing the gate insulation region GOX, so that when an electrical potential difference between the source region S and the drain region D is applied according to the operation of a field effect transistor can form an electrical current flow over the channel region K. By means of corresponding contacts, the resistor element R made of amorphous carbon is connected to the drain region D.

2 shows in the form of an equivalent circuit diagram in a schematic manner the in 1 illustrated embodiment form of the semiconductor integrated circuit arrangement according to the invention 1 , It can clearly be seen that the resistance element or the resistance device R is contacted directly with the drain region D of the transistor device T. The source region S of the transistor device T is at the ground potential. The gate region G of the transistor device T is connected to an input terminal, while between the resistor device R and the drain region D of the transistor T, the output terminal is provided, so that as a whole from the 2 the embodiment of the semiconductor integrated circuit device 1 in Form of an inverter arrangement emerges. The 3 and 4 show in a corresponding manner embodiments of the semiconductor integrated circuit arrangement in the form of a so-called NOR gate or a so-called NAND gate.

1

integrated Semiconductor circuit arrangement according to

of the present invention

20

Semiconductor material region, Semiconductor substrate,

substratum

20a

surface area

D

Drain region, drain

G

Gate area gate

GOX

Gate insulating region

K

channel area

R

Resistance device, resistance

S

source region or source

T

Field effect transistor means,

Field-effect transistor, transistor

Claims (30)

Integrated semiconductor circuit arrangement, - in which a field effect transistor device (T) is formed with a Source region (S), a drain region (D), a channel region provided therebetween (K) and one to this electrically isolated gate region (G) and - in which a resistance device (R) is formed, which in contact is formed with the source region (S), the drain region (D) and / or the gate region (G) and - in which the resistance device (R) is formed with or made of amorphous carbon. Integrated semiconductor circuit arrangement according to claim 1, characterized in that the resistance means (R) with a proportion of amorphous carbon in the range of about 80% to about 100% trained. Integrated semiconductor circuit arrangement according to one of the preceding claims, characterized in that the resistance means (R) as Layer or layer structure is formed. Integrated semiconductor circuit arrangement claim 3, characterized in that the layer or layer structure the resistance device (R) with a layer thickness in the range from 1 nm to about 10 μm is formed, preferably in the range of about 10 nm to about 100 nm. Integrated semiconductor circuit arrangement according to one of the preceding claims, characterized in that the resistance means (R) for Part or completely by means of cathode jet atomization is trained. Integrated semiconductor circuit arrangement according to one of the preceding claims, characterized in that the resistance means (R) for Part or completely is formed by chemical vapor deposition. Integrated semiconductor circuit arrangement according to one of the preceding claims, characterized in that the resistance means (R) for Part or completely is formed by evaporation. Integrated semiconductor circuit arrangement according to one of the preceding claims, characterized in that the field effect transistor device (T) based on at least one organic semiconductor material is trained. Integrated semiconductor circuit arrangement according to claim 8, characterized in that the channel region (K) of the field effect transistor device (T) is formed with or from an organic semiconductor material. Integrated semiconductor circuit arrangement according to one of the preceding claims 8 or 9, characterized in that the channel region (K) of Field effect transistor device (T) with or made of a material is formed from the group formed by pentacene, Polythiophenes and oligothiophenes. Integrated semiconductor circuit arrangement according to one of the preceding claims 1 to 7, characterized in that the field effect transistor device (T) formed as an inorganic field effect transistor device (T) is, in particular as a thin-film field effect transistor device. Integrated semiconductor circuit arrangement according to one of the preceding claims 1 to 7 or 11, characterized in that the field effect transistor device (T) is formed on the basis of amorphous silicon. Integrated semiconductor circuit arrangement according to one of the preceding claims, which is designed as an inverter arrangement, wherein the resistance device (R) between the drain region (D) of the field effect transistor device (T) and a VDD terminal region is formed. Integrated semiconductor circuit arrangement according to one of the preceding claims 1 to 12, which is formed as a NOR gate. Integrated semiconductor circuit arrangement according to one of the preceding claims 1 to 12, which is designed as a NAND gate. Method for producing a semiconductor integrated circuit arrangement, - in which a field effect transistor device (T) is formed with a Source region (S), a drain region (D), an intermediate provided Channel region (K) and one of these electrically insulated gate region (G) and - at which a resistance device (R) is formed, which is formed in contact with the source region (S), the drain region (D) and / or the gate region (G) and - in which the resistance device (R) is formed with or from amorphous carbon. Method according to claim 16, characterized in that that the resistance device (R) with a proportion of amorphous Carbon is formed in the range of about 80% to about 100%. Method according to claim 16 or 17, characterized that the resistance device (R) as a layer or layer structure is trained. Method according to claim 18, characterized that the layer or layer structure of the resistance device (R) with a layer thickness in the range of 1 nm to about 10 microns is formed, preferably in the range of about 10 nm to about 100 nm. Method according to one of the preceding claims 16 to 19, characterized in that the resistance device (R) partly or completely by means of cathode jet atomization is trained. Method according to one of the preceding claims 16 to 20, characterized in that the resistance device (R) partly or completely is formed by chemical vapor deposition. Method according to one of the preceding claims 16 to 21, characterized in that the resistance device (R) partly or completely is formed by evaporation. Method according to one of the preceding claims 16 to 22, characterized in that the field effect transistor device (T) based on at least one organic semiconductor material is trained. Method according to claim 23, characterized the channel region (K) of the field-effect transistor device (T) is formed with or from an organic semiconductor material. Method according to one of the preceding claims 23 or 24, characterized in that the channel region (K) of the field effect transistor device T) is formed with or from a material from the group, which is formed by pentacene, polythiophenes and oligothiophenes. Method according to one of the preceding claims 16 to 22, characterized in that the field effect transistor device (T) is formed as an inorganic field effect transistor device (T), in particular as a thin-film field effect transistor device. Method according to one of the preceding claims 16 to 22 or 26, characterized in that the field effect transistor device (T) is formed on the basis of amorphous silicon. Method according to one of the preceding claims 16 to 27, which is formed as an inverter arrangement, wherein the resistance device (R) between the drain region (D) of the field effect transistor device (T) and a VDD terminal area is formed. Method according to one of the preceding claims 16 to 28, in which the semiconductor circuit arrangement as a NOR gate is trained. Method according to one of the preceding claims 16 to 29, in which the semiconductor circuit arrangement as a NAND gate is trained.