DE102004026002B4 - Semiconductor device with solid electrolyte memory cells and manufacturing method - Google Patents

Abstract

Semiconductor device with
- A semiconductor substrate (1) and
- One, parallel to a main surface (9) of the semiconductor substrate (1) arranged, provided with electrical connection contacts (3), first. Insulator layer (2), as well
Solid-state electrolyte memory cells which can be switched between a high-resistance OFF state and a low-resistance ON state, each memory cell comprising a reactive electrode (5), an inert electrode (6), and a solid electrolyte arranged between the two electrodes, which is suitable to electrically isolate the two electrodes (5, 6) from each other, whereby the OFF state of the memory cell is defined, wherein metal ions can be generated on the reactive electrode (5) by applying an electric voltage, forming in the solid electrolyte the formation of a cause both electrodes electrically connecting, low-resistance current paths, whereby the ON state of the solid state electrolyte storage cell is defined, wherein
Each memory cell has a structure which is parallel to the main surface of the semiconductor substrate and has non-overlapping electrodes (5, 6) offset in a direction parallel to the main surface, the memory cells being ...

Description

The The present invention is in the field of non-volatile Memory and in particular relates to a semiconductor device with Solid electrolyte memory cells and manufacturing method therefor.

nowadays be considered non-volatile Memory often Flash memory used. Flash memory is one on charge storage on a floating gate based memory, which is typically one of columns and Has rows of composite matrix structure. The cells are in dependence from their architecture (eg NOR or NAND) in parallel or in series connected. Each memory cell has a control gate and a floating gate on which by a thin Tunnel oxide layer are separated. Becomes an electrical Field to source, drain and applied to the control gate, electrons can between the active region of the semiconductor substrate and the floating gate tunnel, causing the threshold voltage of the memory cell between two states can be switched. Although the flash memory technology in In recent years, a rapid scaling in the sub-100 nm range experienced the disadvantages of long write / erase times, which are typically in the range of milliseconds, the high Write voltages typically in the range of 10 to 13V and the consequently large programming energy required, which hinders the desire for further miniaturization, not solved yet become. Further, the manufacturing method of the flash memory cells relatively expensive and thus comparatively complex.

One new, promising approach to non-volatile manufacturing Memory cells based on the use of solid state electrolytes as active (switching) material for nonvolatile memory cells. in this connection In particular, chalcogenides are suitable for their suitability as active material has been studied. See for example M. N. Kozicki, M. Yun, L. Hilt, A. Singh, Electrochemical Society Proceedings, Vol. 99-13, 298, 1999; M.N. Kozicki, M.Yun, S.J. Yang, J. P. Aberouette, J.P. Bird, Superlattices and Microstructures, Volume 27, No. 5/6, 485-488, 2000; M.N. Kozicki, et al., "Nanoscale Phase separation in Ag-Ge-Se glasses ", Micro Electron. Closely. 63, 155/2002; M.N. Kozicki, M. Mitkova, J. Zhu, M. Park, C. Gopalan, "Can Solid State Electrochemistry Eliminate the Memory Scaling Quandry ", Proceedings VLSI, 2002; R. Neale, "Micron to look again at non-volatile amorphous memory ", Electronic Engineering Design, 2002.

there In particular, it has been found that Chalcogenide, i. H. alloys, which chalcogens (elements of the VI main group of the periodic table of the elements), in a solid state electrolyte storage cell, as described, for example, by Kozicki et al. has been described have good switching properties.

Solid-state electrolyte memory cells are based on an electrochemical redox process in which metal ions of one electrode can reversibly in and out of the solid electrolyte material, thus forming or dissolving a low-resistance path. More specifically, a solid electrolyte is embedded between two electrodes, one electrode being formed as an inert electrode and the other electrode as a so-called reactive electrode, wherein the reactive electrode together with the solid electrolyte forms a redox system in which above a defined threshold voltage (V _th ) a redox reaction takes place. Depending on the polarity of the voltage applied to the two electrodes, which, however, must be greater than the threshold voltage, the redox reaction can proceed in one or the other reaction direction, metal ions being produced or destroyed. Specifically, when an anodic potential above the threshold voltage is applied to the reactive electrode, metal ions are generated and released into the solid state electrolyte. These metal ions are then reduced in the solid electrolyte and form metallic precipitates. If metal ions are continuously released into the solid-state electrolyte, the number and size of the metallic precipitates increase until, finally, a metallic current path bridging the two electrodes is formed. In this state, the electrical resistance of the solid state electrolyte is substantially reduced, as compared to the state without a metallic current path, by several orders of magnitude, whereby the ON state of the memory cell is defined. If an oppositely poled voltage is applied to the two electrodes, this leads to the oxidation of the metallic precipitates of the current path, with the result that the latter no longer electrically connects the two electrodes to one another, whereby the OFF state of the memory cell is defined.

The abovementioned publications suggest depositing the solid state electrolyte into a via hole etched vertically in a conventional inter-dielectric (hole between two metallization levels of a semiconductor device). Subsequently, the material of the reactive electrode is deposited and patterned, which can be done for example by a suitable etching process or by chemical-mechanical polishing (CMP). This is followed by a process that drives the material of the reactive electrode in the solid electrolyte to a background doping of the solid electrolyte by UV irradiation to produce with the metal of the reactive electrode. In order to ensure a sufficiently thin layer thickness of the reactive electrode material for a sufficient UV irradiation of the solid electrolyte, however, the reactive electrode must be deposited at least in two stages. However, this two-step process management is complex and therefore costly. In addition, scalability is low in this type of process control.

New description page 4a (suggestion)

The PCT application WO 03/079463 A2 describes a lateral PMC (Programmable Metallization Cell) with the features of the preamble of claim 1.

In contrast there is the object of the present invention therein, a semiconductor device, as well to provide a method for its production, with which the possibility a one-step deposition of the solid electrolyte with a two-stage process management associated disadvantages can be avoided.

These The object is according to the proposal of the invention by a semiconductor device with the characteristics of the independent claims solved. advantageous Embodiments of the invention are indicated by the features of the subclaims.

According to the invention is a Semiconductor device shown, which with a semiconductor substrate and at least one, parallel to a main surface of the semiconductor substrate arranged, provided with electrical connection contacts, first Insulator layer, as well as solid state electrolyte storage cells, between a high-impedance OFF state and a low-resistance one ON state can be switched is provided. Each solid-state electrolyte storage cell, hereinafter simply referred to as "memory cell" two electrodes, namely a reactive electrode, generally a metal electrode, and an inert electrode and one between the two electrodes arranged solid state electrolyte. The solid state electrolyte is suitable for electrically insulating the two electrodes from each other, whereby the OFF state of the solid electrolyte memory cell is defined. The reactive electrode and the solid electrolyte together form a redox system in which above a defined Redox potential, a redox reaction takes place, which depends on the polarity a voltage applied to the two electrodes in the one or the other direction expires, wherein at the reactive electrode at a suitably polarized voltage Metal ions can be generated in the solid state electrolyte be reduced and a metal concentration in the solid electrolyte increase. If the metal concentration in the solid electrolyte is sufficiently high, this leads for the formation of a low-resistance current path bridging the two electrodes, whereby the ON state of the solid electrolyte memory cell is defined. The semiconductor device according to the invention is essentially characterized by the fact that the memory cells, d. H. each individual memory cell for itself, one to the main surface of the Semiconductor substrate has substantially parallel structure. aid of the structure according to the invention is a one-step deposition of the material of the reactive electrode possible, because a clear view to the solid electrolyte the memory cells and this therefore easily with UV light can be exposed. In addition, the structure of the invention provides the advantage of high scalability and easier process control, since the memory cell essentially by the diffusion of the material the reactive electrode is self-aligned forms. Furthermore, several memory cells advantageously with a common reactive electrode be formed.

at an advantageous first embodiment of the semiconductor device according to the invention are the memory cells substantially in one on the first insulator layer arranged second insulator layer, which in particular a solid electrolyte layer can be educated. The first embodiment is advantageous configured such that a terminal contact of the first insulating layer with the reactive electrode or the inert electrode of a memory cell electrically is conductively connected. A procedural advantage in terms of on the Ätzselektivität may show that the other electrode from the reactive Electrode and the inert electrode of this memory cell in having the first insulator layer projecting portion.

One Method for producing the first embodiment of the semiconductor device according to the invention includes the following steps: providing a semiconductor substrate with at least one, parallel to a main surface of the Semiconductor substrate arranged with electrical connection contacts provided, first insulator layer; Depositing a solid electrolyte layer on the first insulator layer; etching of holes at least in the solid electrolyte layer; To fill the holes with the material of an electrode of the reactive electrode and the inert electrodes of the memory cells; Etching holes at least into the solid electrolyte layer; To fill the holes with the material of the other electrode from the reactive electrode and the inert electrodes of the memory cells and doping the solid state electrolyte.

If the layer deposited on the first insulator layer is not a layer of a solid electrolyte, but only one of the memory cells isolie As an alternative to the above method, the first embodiment of the semiconductor component according to the invention can be produced according to the following method, comprising the steps: providing a semiconductor substrate with at least one first insulator layer arranged parallel to a main surface of the semiconductor substrate and provided with electrical connection contacts; Depositing a second insulator layer on the first insulator layer; Etching holes at least into the second insulator layer; Filling the holes with the material of an electrode of the reactive electrode and the inert electrodes of the memory cells; Etching holes at least into the second insulator layer; Filling the holes with the material of the other electrode of the reactive electrode and the inert electrodes of the memory cells; Etching holes at least into the second insulator layer; Filling the holes with the material of the solid state electrolyte of the memory cells and doping the solid state electrolyte.

at an advantageous second embodiment of the semiconductor device according to the invention are the memory cells substantially in the first insulator layer and a second insulator layer disposed on the first insulator layer, in particular a solid electrolyte layer, educated. The second embodiment of the semiconductor component according to the invention is advantageously designed so that one in the first insulating layer trained, electrical connection contact an electrode the reactive electrode and the inert electrode of a memory cell forms and the other electrode from the reactive electrode and the inert electrode of the memory cell in the on the first insulator layer arranged second insulator layer is formed. A process engineering Advantage, especially with respect to the Ätzselektivität can This results from the fact that the one electrode from the reactive Electrode and inert electrode of the memory cell, which in the first insulator layer is arranged, one in the on the first Insulator layer disposed second insulator layer projecting portion and / or the other electrode from the reactive electrode and inert electrode of the memory cell, which in the second insulator layer is arranged, a projecting into the first insulator layer portion having.

The second embodiment of the semiconductor device according to the invention can be made by a process which includes the following steps comprising: providing a semiconductor substrate with at least one, parallel to a main surface of the semiconductor substrate arranged, provided with electrical connection contacts, first insulator layer, wherein the electrical connection contacts an electrode from the reactive electrode and the inert electrode of a memory cell form; Depositing a solid electrolyte layer on the first insulator layer; etching of holes at least in the solid electrolyte layer; To fill the holes with the material of the other electrode from the reactive electrode and the inert electrode of the memory cells and doping the solid electrolyte.

alternative for this, for the case that no solid electrolyte layer deposited on the first insulator layer, the second embodiment of the semiconductor device according to the invention be prepared by a process which includes the following steps comprising: providing a semiconductor substrate with at least one, parallel to a main surface of the semiconductor substrate arranged, provided with electrical connection contacts, first Insulator layer, wherein the electrical connection contacts an electrode from the reactive electrode and the inert electrode of a memory cell form; Depositing a second insulator layer on the first Insulator layer; etching of holes at least in the second insulator layer; Fill the holes with the material of the others Electrode of the reactive electrode and the inert electrode the memory cells; etching of holes at least in the second insulator layer; Fill the holes with the material of the solid electrolyte the memory cells and doping of the solid state electrolyte.

at an advantageous third embodiment of the semiconductor device according to the invention are the memory cells substantially in the first insulator layer, a second insulator layer disposed on the first insulator layer, which is in particular a solid electrolyte layer can, and arranged on the second insulator layer third Insulator layer formed. The third embodiment of the semiconductor device according to the invention is advantageously designed so that a trained in the first insulating layer, electrical connection contact an electrode from the reactive electrode and the inert electrode of one memory cell and the other electrode from the reactive electrode and the inert electrode of the memory cell is formed in the third insulator layer. A process engineering Advantage, especially with regard to the Ätzselektivität, may be In this case, it can be concluded that the one electrode is made of the reactive one Electrode and inert electrode of the memory cell, which in the first insulator layer is arranged, one in the second insulator layer, in particular Solid electrolyte layer, Having projecting portion, and / or the other electrode of the reactive electrode and inert electrode of the memory cell, which is disposed in the third insulator layer, one in the second Insulator layer projecting portion has.

The third embodiment of the semiconductor device according to the invention can be made by a process which includes the following steps comprising: providing a semiconductor substrate with at least one, parallel to a main surface of the semiconductor substrate arranged, provided with electrical connection contacts, first insulator layer, wherein the electrical connection contacts an electrode from the reactive electrode and the inert electrode of a memory cell form; Depositing a solid electrolyte layer on the first insulator layer; Depositing a third insulator layer on the solid electrolyte layer; Etching of holes at least in the third insulator layer; Fill the holes with the material of the others Electrode of the reactive electrode and the inert electrode the memory cells and doping of the solid electrolyte.

alternative For this, the third embodiment the semiconductor device according to the invention, for the Case, that no solid electrolyte layer deposited on the first insulator layer by a method which comprises the following steps: providing a semiconductor substrate having at least one, parallel to one main surface of the semiconductor substrate arranged, provided with electrical connection contacts first insulator layer, wherein the electrical connection contacts an electrode of the reactive electrode and the inert electrode form a memory cell; Depositing a second insulator layer on the first insulator layer; etching of holes at least in the second insulator layer; Fill the holes with the material of the solid electrolyte the memory cells; Depositing a third insulator layer the second insulator layer; Etching of holes at least in the third insulator layer; Fill the holes with the material of the others Electrode of the reactive electrode and the inert electrode the memory cells and doping of the solid electrolyte.

According to the invention and in accordance with the general understanding in the technical field an "electric conductive state "one Electron current, which is different than the "ion-conducting state" of the solid electrolyte without low impedance current path must be considered. For this reason can the solid electrolyte, Although it is ion-conducting, the two electrodes from each other electrically isolate to define the OFF state of the switching element. Will an anodic potential higher than the redox potential, applied to the reactive electrode, the metal becomes the reactive one Electrode oxidized and the metal ions generated are in the solid state electrolyte issued. This redox potential thus defines the threshold voltage to start the redox reaction, but which of a variety other properties, such as the chosen material system depends. A Reactive electrode according to the invention is capable of metal ions to generate (or destroy) if a suitable polarized voltage is applied to the two electrodes, which is higher than the threshold voltage. In contrast, an "inert Electrode "as an electrode which is unable to produce metal ions when the above-mentioned threshold voltage applied to the two electrodes is, d. H. the material of the inert electrode is chosen so that its redox potential in conjunction with the solid-state electrolyte certainly higher is than that of the metal of the reactive electrode. The material the inert electrode is further selected to be in contact with the solid state electrolyte not chemically reacted and no significant solubility or mobility in the Solid electrolyte having.

The solid-state electrolyte is an ion-conductive material which has a good ionic conductivity for the metal ions of the reactive electrode or can be brought into such a state by heating. Such a solid electrolyte is advantageously a glass, in particular a semiconductive material. Particularly preferably, the solid electrolyte comprises at least one alloy containing at least one chalcogen, ie an element of VI. Main group of the Periodic Table of the Elements, such as O, S, Se, Te contains. For example, a glassy chalcogenide alloy may be Ge-S, Ge-Se, Ni-S, Cr-S or Co-S. According to the invention, the solid electrolyte may also be a porous metal oxide, such as WO _x , Al ₂ O ₃ , VO _x or TiO _x . The above enumerations for the solid electrolyte are merely exemplary and are not intended to limit the invention thereto.

at The material of the reactive electrode may be a metal which, for example, from Cu, Ag, Au, Ni, Cr, V, Ti or Zn chosen is. The inert electrode may be made of a material which for example, selected from W, Ti, Ta, TiN, doped Si and Pt.

According to the invention, the inert electrode is considered to be "inert" if its redox potential is greater than the potential used to switch the memory cell, whereby it may be advantageous for the material of the inert electrode to have a redox potential which does not exist for a threshold voltage of 5 volts maximum According to the invention, it is preferred that the threshold voltage for activating the redox system, ie for starting the redox reaction for generating metal ions on the anodic electrode, is a maximum of 5 volts, since otherwise the risk of electrical breakdown of the layers exists , if the threshold voltage is a maximum of 2 volts. In accordance with the invention, it is most preferred that the threshold voltage be less than 1 volt, which may typically be in the range of 200 to 500 millivolts. According to the invention, it is preferred that the two electrodes are at a distance from each other which is in the range of 10 nm to 250 nm. It is more preferred if the distance between the two electrodes is in the range of 20 nm to 100 nm and, for example, 50 nm.

In the memory cells of the semiconductor device according to the invention are advantageously realizes fast switching speeds, which at least the current switching speeds of conventional Reach DRAM / SRAM switch cells. According to the invention is a switching speed of 1 μs prefers. Stronger preferred is a switching speed of less than 100 ns, and even stronger preferred is a switching speed of less than 10 ns.

By the generation of a background doping in the solid electrolyte can be described in Advantageously, the switching properties for creating a Low impedance current paths to bridge both Electrodes are optimized. The doped solid electrolyte material has a percolative switching effect, so starting from a critical Metallkonzenration a low-impedance current path is formed. That way you can the switching characteristics of the memory cells are reduced. nevertheless but must be for it Care should be taken that the insulating property of the solid electrolyte is not affected by the background doping, so an overdosing is avoided.

The Layer thicknesses of the first insulating layer and / or the memory cell level and / or, if present, the second insulating layer, preferably have a layer thickness in the range of 50 nm to 200 nm.

at a particularly advantageous embodiment of the semiconductor device according to the invention forms a reactive electrode is a common reactive electrode of two adjacent memory cells.

The Invention will now be closer explains with reference to the attached Drawings is taken.

1 schematically shows an exemplary embodiment of a semiconductor device;

2 shows in a schematic way a further exemplary embodiment of a semiconductor device;

3 schematically shows an exemplary embodiment of the first Ausfüh tion form of the semiconductor device according to the invention;

4 shows in a schematic way a further exemplary embodiment of the first embodiment of the semiconductor device according to the invention;

5 schematically shows an exemplary embodiment of the second embodiment of the semiconductor device according to the invention;

6 shows in a schematic way a further exemplary embodiment of the second embodiment of the semiconductor device according to the invention;

7 shows in a schematic way a further exemplary embodiment of the second embodiment of the semiconductor device according to the invention;

8th shows in a schematic way a further exemplary embodiment of the second embodiment of the semiconductor device according to the invention;

9 shows in a schematic way a further exemplary embodiment of the second embodiment of the semiconductor device according to the invention;

10 shows in a schematic way a further exemplary embodiment of the second embodiment of the semiconductor device according to the invention;

11 shows in a schematic way a further exemplary embodiment of the second embodiment of the semiconductor device according to the invention;

12 shows in a schematic way a further exemplary embodiment of the second embodiment of the semiconductor device according to the invention;

13 schematically shows an exemplary embodiment of the third embodiment of the semiconductor device according to the invention;

14 shows in a schematic way a further exemplary embodiment of the third embodiment of the semiconductor device according to the invention;

15 shows in a schematic way a further exemplary embodiment of the third embodiment of the semiconductor device according to the invention;

16 shows in a schematic way a further exemplary embodiment of the third embodiment of the semiconductor device according to the invention;

17 shows in a schematic way a further exemplary embodiment of the third embodiment of the semiconductor device according to the invention;

18 shows in a schematic way a further exemplary embodiment of the third embodiment of the semiconductor device according to the invention;

19A - 19D illustrate in a schematic way the steps for producing an exemplary embodiment of the second embodiment of the semiconductor device according to the invention according to 12 ,

First, reference to the 1 - 4 which schematically shows exemplary embodiments of the first embodiment of the semiconductor device according to the invention. 1 shows a semiconductor substrate 1 with a first insulator layer arranged parallel to a main surface of the semiconductor substrate 2 from, for example, SiO ₂ , which has electrical connection contacts ("plugs") 3 is provided for contacting the different metallization levels of the semiconductor device. Parallel to the first insulator layer 2 is a second insulator layer 4 of solid electrolyte material, for example, a vitreous, porous chalcophenolite alloy. Within the solid electrolyte layer 4 are a reactive electrode 5 , as well as an inert electrode 6 educated. The electrical connection contact 3 the insulator layer contacts the reactive electrode 5 , Between the two electrodes 5 . 6 is solid electrolyte. The dotted border (in all figures) is the switching element consisting of the two electrodes 5 . 6 and the interposed solid electrolyte, the memory cell characterized.

The others 2 . 3 and 4 show further embodiments of the first embodiment of the semiconductor device according to the invention, wherein only the structural differences are described to avoid unnecessary repetition.

In the in 2 The embodiment shown is the electrical connection contact 3 with the inert electrode 6 electrically connected. In the in 3 The embodiment shown is the electrical connection contact 3 with the inert electrode 6 electrically connected and also has the reactive electrode 5 this electrode into the first insulator layer 2 protruding section 7 on. In the in 4 The embodiment shown is the electrical connection contact 3 with the reactive electrode 5 electrically connected and also has the inert electrode 5 this memory cell into the first insulator layer 2 protruding section 8th on.

The in the 1 to 4 shown embodiments of the first embodiment of the semiconductor device according to the invention can be prepared by acting on the insulator layer 2 with the connection contacts 3 the second insulator layer 4 is deposited from the solid electrolyte material, in which then using a first etching mask, a hole for forming one of the two electrodes is etched, which is then filled with the corresponding electrode material. Subsequently, another hole is etched using a second etching mask to form the other electrode, which is then filled with electrode material. One of the two holes should be above the connection contact 3 to form the electrical contact between the electrode and the terminal contact. When etching the holes, it is according to the in 3 or in 4 shown embodiments possible that a hole into the insulator layer 2 extends, which significantly facilitates the process control with respect to the Ätzselektivität.

There is now a description of the in the 5 - 12 shown exemplary embodiments of the second embodiment of the semiconductor device according to the invention. Next is reference to 5 taken. 5 shows a semiconductor substrate 1 with a parallel to a main surface 9 of the semiconductor substrate arranged insulator layer 2 from, for example, SiO ₂ , which is provided with electrical connection contacts for contacting the various metallization levels of the semiconductor component. The connection contact is as a reactive electrode 5 educated. Parallel to the first insulator layer 2 is a solid electrolyte layer 4 For example, from a glassy, porous Chalgonenid metal alloy, deposited. Within the solid electrolyte layer 4 is an inert electrode 6 educated. Between the two electrodes 5 . 6 is solid electrolyte. The dotted border is the switching element, consisting of the two electrodes 5 . 6 and the interposed solid electrolyte, the memory cell characterized.

The others 6 to 12 show further embodiments of the second embodiment of the semiconductor device according to the invention, wherein only the structural differences are described to avoid unnecessary repetition. In the in 6 The embodiment shown is the electrical connection contact of the first insulator layer 2 as a reactive electrode 5 educated. In addition, the reactive electrode has 5 one into the solid electrolyte layer 4 protruding section 10 on. In the 7 shown embodiment of the second embodiment differs from that in 6 shown embodiment in that the inert electrode 6 with one in the first insulator layer 2 protruding projection 11 is provided. In the 8th shown embodiment of the second embodiment differs from that in 5 shown embodiment in that the inert electrode 6 with one in the first insulator layer 2 protruding projection 11 is provided. In the 9 The embodiment shown is the electrical connection contact of the insulator layer 2 as an inert electrode 6 formed while the reactive electrode 5 in the solid state electrolyte layer 4 is trained. In the 10 shown embodiment of the second embodiment differs from that in 9 shown embodiment in that the inert electrode 6 with one in the solid state electrolyte layer 4 protruding projection 12 is provided. In the 11 shown embodiment of the second embodiment differs from that in 10 shown embodiment in that the reactive electrode 5 , which in the solid electrolyte layer 4 is formed, with a in the first Isloatorschicht 2 protruding projection 13 is provided. In the 12 shown embodiment of the second embodiment differs from that in 9 shown embodiment in that the reactive electrode 5 , which in the solid electrolyte layer 4 is formed, with a in the first insulator layer 2 protruding projection 13 is provided.

The in the 5 to 12 shown embodiments of the second embodiment of the semiconductor device according to the invention can be prepared by a semiconductor substrate with a first insulator layer in which one of the two electrodes of the switching element of the memory cell is designed as a terminal contact, is provided, and then on the insulator layer 2 a solid electrolyte layer 4 is deposited. Using an etching mask, a hole is then etched to form the other of the two electrodes, which is then filled with the corresponding electrode material. The two electrodes of the memory cell can each extend into the adjacent layer, which considerably facilitates the process control with regard to the etch selectivity.

There is now a description of the in the 13 - 18 shown exemplary embodiments of the third embodiment of the semiconductor device according to the invention. First of all, refer to 13 taken. 13 shows a semiconductor substrate 1 with a first insulator layer arranged parallel to a main surface of the semiconductor substrate 2 from, for example, SiO ₂ , which is provided with electrical connection contacts for contacting the various metallization levels of the semiconductor component. The connection contact is as an inert electrode 6 educated. Parallel to the insulator layer 2 is a second insulator layer in the form of a solid electrolyte layer 4 For example, from a glassy, porous Chalgonenid metal alloy, deposited. On the solid electrolyte layer 4 is a third insulator layer 14 separated from, for example, SiO ₂ . In the third insulator layer 14 is a reactive electrode 5 formed, which one in the solid electrolyte layer 4 projecting section 15 having. Between the two electrodes 5 . 6 is solid electrolyte of the solid electrolyte layer 4 , The dotted border is the switching element, consisting of the two electrodes 5 . 6 and the interposed solid electrolyte, the memory cell characterized.

The 14 to 18 show further embodiments of the third embodiment of the semiconductor device according to the invention, wherein only the structural differences are described to avoid unnecessary repetition. In the 14 shown embodiment differs from the in 13 shown embodiment in that the inert electrode 6 one into the solid electrolyte layer 4 projecting section 16 having. In the 15 shown embodiment differs from the in 14 shown embodiment in that only the inert electrode 6 one into the solid electrolyte layer 4 projecting section 16 having. In the in 16 The embodiment shown is the electrical connection contact of the first insulator layer 2 as a reactive electrode 5 formed while the inert electrode 6 in the third insulator layer 14 is trained. In addition, the inert electrode 6 one into the solid electrolyte layer 4 protruding projection 17 on. In the 18 shown embodiment of the second embodiment differs from that in 17 shown embodiment in that also the reactive electrode 5 with one in the solid state electrolyte layer 4 protruding projection 18 is provided.

The in the 13 to 18 shown embodiments of the third embodiment of the semiconductor device according to the invention can be prepared by a semiconductor substrate is provided with an insulator layer in which one of the two electrodes of the switching element of the memory cell is designed as a terminal contact, then on the insulator layer 2 a solid perelektrolytschicht 4 is deposited from the solid electrolyte material, with the latter in turn a third insulator layer 14 is deposited. Using an etching mask is then in the third insulator layer 14 etching a hole to form the other of the two electrodes, which is then filled with the corresponding electrode material. The two electrodes of the memory cell can each extend into the adjacent layer, which considerably facilitates the process control with regard to the etch selectivity.

It will now be related to the 19A - 19D taken, wherein schematically the steps for producing an exemplary embodiment of the second embodiment of the semiconductor device according to the invention according to 12 are illustrated. For the production, first a semiconductor substrate 1 provided, which up to the first insulator layer 2 with the connection contacts by means of conventional CMOS technology FEOL (front end of line) is finished processed. The connection contacts in the first insulator layer 2 , which metal tracks and / or active components electrically connect together, serve at the same time as inert Elekt roden 6 , Subsequently, a solid electrolyte layer 4 , For example, a chalcogenide-containing metal alloy, on the first insulator layer 2 isolated ( 19A ). Subsequently, optionally, a dielectric barrier layer 19 deposited. Then a hole is etched, with the etching extending into the first insulator layer 2 can extend into it, and with the material of the reactive electrode 5 filled. Subsequently, it is chemically-mechanically polished, with the additional dielectric layer 19 here serves as a polishing stoppage ( 19B ). In the following, the solid electrolyte layer 4 through the dielectric layer 19 irradiated with UV light to dope the solid electrolyte. By outdiffusing metal ions from the material of the reactive electrode 5 in the solid state electrolyte layer 4 can simultaneously use two memory cells from a single reactive electrode 5 be prepared, ie, a single reactive electrode 5 is then a common reactive electrode 5 two adjacent memory cells, which can be very advantageous in terms of high integration densities. The two adjacent memory cells are indicated by the two dotted frames in 19C characterized. By separately addressing the two memory cells by means of selection devices (eg one selection transistor each), these two memory cells can be separately programmed, released and read. Finally, there is another BEOL (back end of line) processing, for example, another insulator layer 20 with a connection contact 22 and a metal trace 21 are deposited as wiring level ( 19D ).

1

Semiconductor substrate

2

first insulator layer

3

connection contact

4

Solid electrolyte layer

5

reactive electrode

6

inert electrode

7

projecting section

8th

projecting section

9

main surface

10

projecting section

11

projecting section

12

projecting section

13

projecting section

14

third insulator layer

15

projecting section

16

projecting section

17

projecting section

18

projecting section

19

dielectric barrier layer

20

insulating

21

Metal conductor

22

plug

Claims (14)

Semiconductor device having - a semiconductor substrate ( 1 ) and - one, parallel to a main surface ( 9 ) of the semiconductor substrate ( 1 ), with electrical connection contacts ( 3 ), first. Insulator layer ( 2 ), and solid state electrolyte memory cells which can be switched between a high-resistance OFF state and a low-resistance ON state, each memory cell having a reactive electrode ( 5 ), an inert electrode ( 6 ), and a solid electrolyte arranged between the two electrodes, which is suitable, the two electrodes ( 5 . 6 ), whereby the OFF-state of the memory cell is defined, whereby at the reactive electrode ( 5 ) can be generated by applying an electrical voltage metal ions that can cause in the solid electrolyte, the formation of a, electrically connecting the two electrodes, low-resistance current path, whereby the ON state of the solid electrolyte memory cell is defined, wherein - each memory cell parallel to the main surface of the semiconductor substrate Structure has, in a direction parallel to the main surface parallel, non-overlapping electrodes ( 5 . 6 ), wherein the memory cells in one on the first insulator layer ( 2 ) arranged second insulator layer are formed, and in each case a terminal contact ( 3 ) with an electrode from the reactive electrode ( 5 ) and the inert electrode ( 6 ) of a memory cell is electrically conductively connected, characterized in that the other electrode from the reactive electrode ( 5 ) and the inert electrode ( 6 ) of the memory cell a projecting into the first insulator layer portion ( 7 . 8th ) having. Semiconductor component according to Claim 1, characterized in that the memory cells in the first insulator layer ( 2 ) and a second insulator layer arranged on the first insulator layer, and one each in the first insulator layer ( 2 ) formed, electrical connection contact an electrode from the reactive electrode ( 5 ) and the inert electrode ( 6 ) forms a memory cell and the other electrode from the reactive electrode ( 5 ) and the inert electrode ( 6 ) of the memory cell is formed in the second insulator layer, wherein at least one electrode of the reactive electrode and the inert electrode of the memory cell has a section projecting into the second insulator layer (US Pat. 10 . 12 ) having. Semiconductor component according to claim 2, characterized in that both electrodes of a memory cell into the first insulator layer ( 2 ) have protruding portion. Semiconductor component according to Claim 1, characterized in that the memory cells in the first insulator layer ( 2 ), a second insulator layer disposed on the first insulator layer, and a third insulator layer (US Pat. 14 ), wherein an electrical connection contact formed in the first insulator layer comprises an electrode from the reactive electrode ( 5 ) and the inert electrode ( 6 ) forms a memory cell and the other electrode from the reactive electrode ( 5 ) and the inert electrode ( 6 ) of the memory cell in the third insulator layer ( 14 ), wherein at least one of the reactive electrode and the inert electrode of the memory cell has a portion protruding into the second insulator layer (US Pat. 16 . 18 ) having. Semiconductor component according to claim 4, characterized in that both electrodes of a memory cell projecting into the second insulator layer projecting portion ( 15 . 17 ) exhibit. Semiconductor component according to one of the preceding claims, characterized in that the second insulator layer is a solid electrolyte layer ( 4 ). Semiconductor component according to Claim 4, characterized in that the first insulator layer ( 2 ) and / or arranged on the first insulating layer second insulator layer and / or arranged on the second insulator layer third insulating layer ( 14 ) have a layer thickness in the range of 50 nm to 200 nm. Semiconductor component according to one of the preceding Claims, characterized in that a reactive electrode has a common reactive electrode of two adjacent memory cells. Method for producing a semiconductor component according to claim 1, characterized in that it comprises the following steps: - providing a semiconductor substrate ( 1 ) with one, parallel to a main surface ( 9 ) of the semiconductor substrate ( 1 ), with electrical connection contacts ( 3 ), first insulator layer ( 2 ); - depositing a solid electrolyte layer ( 4 ) on the first insulator layer; Etching first holes in the solid electrolyte layer ( 4 ); Filling the first holes with the material of an electrode from the reactive electrode ( 5 ) and the inert electrodes ( 6 ) of the memory cells; Etching second holes into the solid state electrolyte layer ( 4 ); Filling the second holes with the material of the other electrode from the reactive electrode ( 5 ) and the inert electrodes ( 6 ) of the memory cells; - Doping the solid electrolyte, wherein the etching of the first and / or second holes, an etching is carried out partially into the first insulator layer. Method for producing a semiconductor component according to claim 1, characterized in that it comprises the following steps: - providing a semiconductor substrate ( 1 ) with a parallel to a main surface ( 9 ) of the semiconductor substrate ( 1 ), with electrical connection contacts ( 3 ) provided first insulator layer ( 2 ); Depositing a second insulator layer on the first insulator layer; Etching first holes in the second insulator layer; Filling the first holes with the material of an electrode from the reactive electrode ( 5 ) and the inert electrode ( 6 ) of the memory cells; Etching second holes in the second insulator layer; Filling the holes with the material of the other electrode from the reactive electrode ( 5 ) and the inert electrodes ( 6 ) of the memory cells; Etching third holes in the second insulator layer; - Fill the holes with the material of the solid electrolytes of the memory cells; - Doping the solid electrolyte, wherein the etching of the first and / or second holes, an etching is carried out partially into the first insulator layer. Method for producing a semiconductor component according to claim 2, characterized in that it comprises the following steps: - providing a semiconductor substrate ( 1 ) with a parallel to a main surface ( 9 ) of the semiconductor substrate ( 1 ), with electrical connection contacts ( 3 ), first insulator layer ( 2 ), wherein the electrical connection contacts an electrode from the reactive electrode ( 5 ) and the inert electrode ( 6 ) form a memory cell; - depositing a solid electrolyte layer ( 4 ) on the first insulator layer; Etching first holes in the solid electrolyte layer ( 4 ) and partially into the first insulator layer; Filling the holes with the material of the other electrode from the reactive electrode ( 5 ) and the inert electrode ( 6 ) of the memory cells; - doping of the solid electrolyte. Method for producing a semiconductor component according to claim 2, characterized in that it comprises the following steps: - providing a semiconductor substrate ( 1 ) with a parallel to a main surface ( 9 ) of the semiconductor substrate ( 1 ), with electrical connection contacts ( 3 ), first insulator layer ( 2 ), wherein the electrical connection contacts an electrode from the reactive electrode ( 5 ) and the inert electrode ( 6 ) form a memory cell; Depositing a second insulator layer on the first insulator layer; Etching holes into the second insulator layer and partially into the first insulator layer; Filling the holes with the material of the other electrode from the reactive electrode ( 5 ) and the inert electrode ( 6 ) of the memory cells; - etching holes in the second insulator layer; - filling the holes with the material of the solid state electrolyte of the memory cells; - doping of the solid electrolyte. Method for producing a semiconductor component according to claim 4, characterized in that it comprises the following steps: - providing a semiconductor substrate ( 1 ) with a parallel to a main surface ( 9 ) of the semiconductor substrate ( 1 ), with electrical connection contacts ( 3 ), first insulator layer ( 2 ), wherein the electrical connection contacts an electrode from the reactive electrode ( 5 ) and the inert electrode ( 6 ) form a memory cell; - depositing a solid electrolyte layer ( 4 ) on the first insulator layer; Depositing a third insulator layer ( 14 ) on the solid electrolyte layer ( 4 ); Etching holes in the third insulator layer ( 14 ) and partially into the solid electrolyte layer; Filling the holes with the material of the other electrode from the reactive electrode ( 5 ) and the inert electrode ( 6 ) of the memory cells; - doping of the solid electrolyte. Method for producing a semiconductor component according to claim 4, characterized in that it comprises the following steps: - providing a semiconductor substrate ( 1 ) with a parallel to a main surface ( 9 ) of the semiconductor substrate ( 1 ), with electrical connection contacts ( 3 ), first insulator layer ( 2 ), wherein the electrical connection contacts an electrode from the reactive electrode ( 5 ) and the inert electrode ( 6 ) form a memory cell; Depositing a second insulator layer on the first insulator layer; - etching holes in the second insulator layer; - filling the holes with the material of the solid state electrolyte of the memory cells; Depositing a third insulator layer ( 14 ) on the second insulator layer; Etching holes in the third insulator layer ( 14 ) and partially into the second insulator layer; Filling the holes with the material of the other electrode from the reactive electrode ( 5 ) and the inert electrode ( 6 ) of the memory cells; - doping of the solid electrolyte.