DE102004024661B4 - Trench transistor manufacturing method, by back-forming layer in upper trench region, and semiconductor material on side walls of trench before forming new semiconductor material on side walls - Google Patents

Abstract

The method involves back-forming a first layer (DOX) in the upper trench region (30o), the filing (40) serving as a mask. The semiconductor material (20) on the side walls of the trench in the upper region of the trench are back-formed, with the first layer serving as a mask. A new semiconductor material (20n) of defined doping (p) is formed on the back-formed trench side walls near the upper trench region, forming a channel region of defined doping (p).

Description

The The invention relates to a method for producing a trench transistor.

For use in DC / DC converters, power transistors with low on-resistance R _on and low gate-drain capacitance C _{GD are} required. To reduce the gate-drain capacitance C _GD , the gate electrode G can be replaced by a field electrode F at source potential or other defined potential and a gate electrode G 'with a very small overlap region to the drain region.

In this arrangement, the position of the lower edge U of the gate electrode G 'must be adapted very precisely to the position of the body epi-pn junction. If the lower edge U is too low, the gate-drain overlap and therefore C _{GD will become} intolerably large, whereas if the lower edge U is too high or flat, the channel will only be formed at V _G > V _th or not at all. such that R _{on is increased,} in particular at low V _G.

From the DE 102 10 138 A1 For example, a method is known in which the bottom edge of the gate electrode is adapted to the position of the body epi-pn junction. In this case, the respective adapted layers are implanted with the aid of the back-etched first DOX layer as a mask.

Of the Invention is based on the object, a process for the preparation a trench transistor to provide, in which the mentioned disadvantages of the prior art does not occur.

The Task is solved by a method having the features of independent claim 1. Advantageous Further developments are specified in the subclaims.

The invention provides a method for producing a trench transistor, in which at least one trench is formed in a semiconductor material having a semiconductor surface region, wherein the trench sidewalls and the trench bottom region are each covered or lined with a first layer of a first insulating material, in which the first layer lined trench a filling with a filling material is formed, which fills the trench lined with the first layer only partially and thus defines an upper trench and a lower trench region, wherein in the upper trench region, the Trench sidewalls and in the lower trench region, the Trench sidewalls and the Trenchbodenbereich with the first layer are lined and the lower trench area is filled with the filling. The method comprises the following method steps: - Process step (a): Recovering the first layer in the upper trench region, wherein the filling serves as a mask and prevents the regression of the first layer in the lower trench region, so that it remains there. - Process step (b): Re-forming the semiconductor material at the trench side walls in the upper trench region, wherein the first layer serves as a mask and substantially completely prevents the regression of the semiconductor material in the lower trench region. - Process step (c): Forming a new semiconductor material with defined doping at the recessed trench sidewalls in the region of the upper Trench region, so that a channel region with defined doping in the semiconductor material is formed, wherein the first layer serves as a mask, so that the new semiconductor material is applied with defined doping on the recessed trench sidewalls in the upper trench region or on the filling. The new semiconductor material with defined doping is preferably applied only to the reverse-formed trench sidewalls in the upper trench region and / or on the filling, or the polysilicon electrode.

An object of the invention is thus the definition of the upper trench region and the lower trench region by the filling, which serves as mask in process step (a). Thus, in step (a), the first layer is not reformed in the lower trench region, but only in the upper trench region. A further object of the invention is the reformation of the semiconductor material at the trench sidewalls in the upper trench region and the subsequent formation of a new semiconductor material with defined doping at the recessed trench sidewalls in process step (c). Method step (c) essentially restores the original shape of the semiconductor material before method step (b), but new semiconductor material of defined doping is formed at predefined locations, in particular at locations where semiconductor material was previously removed in method step (b). A part of the new semiconductor material with defined doping forms a channel region of the trench transistor. In other words, by forming the new semiconductor material with defined doping, the channel region or channel of the trench transistor can be formed in a particularly advantageous manner. This is done z. B. so that there is a particularly low on-resistance R _on by the local doping adaptation.

Advantageous it is when the channel region (K) is at a distance HS from the trench bottom region is formed and if after that in a process step (d) the first layer regressed is, with the filling as Mask serves so that the first layer only along the trench side walls and is regressed in the direction of the trench bottom area such that the first Layer the trench on the trench sidewalls just up to one more Height, which is approximately equal to the distance HS of the channel region from the trench bottom region. In method step (d), a kind of fine adjustment is thus carried out by which ensures that a bottom area of the channel area at the same height lies, like the surface the first layer. From the trench floor area has measured the first layer on the trench sidewalls so a height HS, the same the distance of the channel area or the floor area of the channel area from the trench floor area is.

Advantageous it is also, if the semiconductor material in the process step (b) on the trench sidewalls in the upper trench area towards the trench bottom area to about is formed back to the distance HS from the Trenchbodenbereich, and so the Distance HS of the channel region from the trench bottom region is defined.

In An advantageous development of the invention is the semiconductor material in process step (b) by a certain depth, d. H. one certain amount per unit area, degenerated, and the regression the first layer in process step (d) takes place in dependence the determined depth of process step (b). That is, it will be certain parameters of the method step (b) evaluated to the for the process step (d) necessary To determine parameters.

Advantageous it is also, if the semiconductor material in the process step (b) on the trench sidewalls in the upper trench area towards the trench bottom area opposite to the surface the first layer is reduced by a distance HO and when the first layer in the process step by about the same distance HO regressed becomes.

Advantageous it is also if, in process step (c), the new semiconductor material with defined doping is formed so that this is essentially the process step (b) dematerialized Semiconductor material replaced. That is, the shape of the semiconductor material is substantially equal to the mold after process step (c) of the semiconductor material before process step (b). But it can even only on the trench side walls Semiconductor material can be formed with defined doping.

It is also possible that in step (b) the filling is also reformed. Thus, can be dispensed with a mask, and in step (b), the regression of the semiconductor material or the filling done for example by a simple etching.

It is possible, too, that in process step (c) the new semiconductor material with defined Doping also on the retrained filling is trained. This means, For example, no mask or the like is needed.

advantageously, is in the semiconductor material before the formation of at least formed a trenches a defined doping by implantation, especially for a body area that pegs the breakthrough. This results the advantage that no sidewall implantation takes place.

Advantageous it is when the first layer is a thick oxide layer, in particular of silicon dioxide, before step (a) and after Forming the trench conforming to the semiconductor surface area on the trench side walls and on the trench bottom area, in particular by means of deposition, CVD, PVD, sputtering, growing and / or converting an existing material area is trained.

In an advantageous development of the invention, the filling is formed by: forming a filling layer, which fills the lined with the first layer trench and / or the semiconductor surface covered with the first layer, and demapping the filling layer such that the filling layer completely removed on the semiconductor layer covered with the first layer and the trench lined with the first layer is only partial filled remains.

advantageously, the regression takes place in process step (a), in process step (b) and in the process step (d) by etching. The etching isotropic, for example wet-chemically or by means of plasma. The Recharge will for example about a fixed time controlled. For example, about 35 seconds to re-etching 150 nm necessary.

Advantageous It is also when the new semiconductor material with defined doping in step (c) is formed by epitaxy. The Control of the layer thickness when applying the new semiconductor material, for example by means of a predetermined fixed time or based on the layer thickness. This is possible, because the scatter in the formation of the new semiconductor material negligible by epitaxy is.

• – konformes Abscheiden einer Isolationsschicht eines Isolationsmaterials über der Halbleiteroberfläche, an den Trenchseitenwänden im oberen Trenchbereich auf der ersten Schicht und entlang der freiliegenden Flächen der Füllung und
• – Rückätzen der Isolationsschicht auf der Halbleiteroberfläche.

Advantageously, after the process step (d), an insulating layer is formed on the trench sidewalls in the upper trench region on the first layer and / or along the exposed surfaces of the filling, in particular by:

• Conformally depositing an insulating layer of an insulating material over the semiconductor surface, on the trench sidewalls in the upper trench region on the first layer and along the exposed surfaces of the filling and
• - Back etching of the insulating layer on the semiconductor surface.

To the formation of the insulating layer is advantageously a further filling formed, in particular of a semiconductor material, which further filling substantially fills the upper trench area, in particular for forming a gate electrode of the trench transistor. That is, the upper trench area is covered with a semiconductor material, for example Polysilicon, substantially completely filled and so the gate electrode formed of the trench transistor.

It is also advantageous if in the semiconductor material from the surface area formed in the semiconductor material protruding doping region is defined, in particular by implantation with a second Doping, in particular for forming or connecting a source region. That is, it is is z. B. a highly doped region in the surface region of the semiconductor material designed for connecting the source of the trench transistor.

Farther it is advantageous if in the semiconductor material one from the bottom of the semiconductor material protruding into the semiconductor material further doping region with a third defined doping is formed, in particular for forming or connection a drain region of the trench transistor. That is, that Semiconductor material is highly doped from the bottom, which for the Connection of the drain of the trench transistor is advantageous.

Moreover, it is advantageous if the trench transistor is formed as a p-channel transistor and in process step (c) silicon germanium or silicon germanium mixed crystal is used as semiconductor material with defined doping. A silicon germanium mixed crystal is a germanium-added silicon crystal.

Farther it is advantageous if the trench transistor as a p-channel transistor is formed and in process step (c) strained silicon is used as semiconductor material with defined doping. at strained silicon affects the bond lengths, so that results in a different stress behavior. This results in a direction-dependent increased conductivity the tense silicon is not strained silicon.

In a preferred embodiment The invention is the filling as a field electrode, the first layer as a field plate, the others filling as the gate electrode and / or the Iso lationsschicht as the gate oxide layer of Trench transistor formed.

Farther it is advantageous that through the channel region the threshold voltage the trench transistor independently is set by the breakdown voltage, in particular in self-aligned Way. This means, through the channel region as an epitaxially grown channel region the threshold voltage of the trench transistor can be independent of the breakdown voltage can be adjusted. At the breakdown voltage occurs a drain-source avalanche breakdown between two side by side lying trench transistors.

The Invention and in particular certain features, aspects and advantages The invention will become apparent from the following detailed description in conjunction with the attached Drawings clarified.

1 to 13 show in sectional side view intermediate stages, which are achieved in one embodiment of the method according to the invention, and

14 shows a trench transistor produced by the manufacturing method according to the invention.

14 shows a trench transistor 1 or a field plate trench transistor with a field electrode F, which consists of a filling 40 is formed. The trench transistor 1 is in a semiconductor material 20 formed and further comprises a gate electrode G, which consists of a further filling 50 is formed. The field electrode F consists of a first field electrode part 40o and a second field electrode part 40n or a grown field electrode part.

The field electrode F is of the gate electrode G and the semiconductor material 20 completely isolated. The isolation with respect to the gate electrode G is achieved by a gate oxide layer GOX and the isolation from the semiconductor material 20 essentially by a thick oxide layer DOX, which forms the field plate FOX of the trench transistor.

The trench transistor 1 is with a trench 30 or trench with trench sidewalls 30w and a trench floor area 30b educated.

The trench transistor 1 also points outside the trench 30 a channel K or channel region, which consists of grown semiconductor material 20n is formed. The in the direction of the bottom U of the semiconductor material 20 extending side surface 20u the grown semiconductor material 20n or the channel region K has a distance HS from the trench bottom region 30b of the trench 30 of the trench transistor 1 ,

As 14 shows is a lower trench area 30u lined by the thick oxide layer DOX. The lower trench region lined with the thick oxide layer DOX 30u is with the field electrode F or the filling 40 filled. At the trench side walls 30w the thick oxide layer DOX extends from the trench bottom area 30b from measured to a height HS which is approximately equal to the distance of the channel K from the trench bottom area 30b is.

In a doping area 60 which is in a region of the semiconductor material 20 which is adjacent to the surface area 20a of the semiconductor material 20 adjacent, is the semiconductor material 20 n ⁺⁺ doped.

Furthermore, in the semiconductor material 20 in an area adjacent to the semiconductor base U further doping range 70 formed with an n ⁺ doping. The further doping region 70 For example, it may be advantageous as a drain D or for connecting the drain D of the trench transistor 1 be used. The doping region 60 with the n ⁺⁺ doping can be used, for example, as the source S or for the connection of the source S of the trench transistor 1 be used.

Below the doping region 60 from the surface area 20a of the semiconductor material 20 From this point of view, a third doping area is adjacent 80 in which the semiconductor material 20 p ⁺ doped. From the surface area 20a seen from below the third doping region 80 a fourth doping region 90 in which the semiconductor material 20 n ⁺ doped. One from the surface area 20a from the bottom surface 80u of the doping region 80 has a distance 81 from the surface area 20a or the surface of the semiconductor material 20 , That is, the third doping region 80 extends to the distance 81 in the semiconductor material 20 in, measured from the surface area 20a out. It is important in this context that the lower surface 80u of the third doping region 80 from the surface area 20a always measured above the downward facing side surface 20u the grown semiconductor material 20n lies. That is, a distance H-80 of the lower surface 80u of the third doping region 80 from the trench floor area 30b is always greater than or equal to a distance HS of the bottom area of the channel K from the trench bottom area 30b ,

The following is based on the 1 to 13 the manufacture of the trench transistor 1 described.

1 shows the semiconductor material 20 with the semiconductor surface 20a and the semiconductor surface area and the semiconductor bottom U. The semiconductor material 20 is from the semiconductor surface 20a seen n ⁺ -doped and doped in the area of the semiconductor base U n ⁺⁺ . A portion of the n ⁺ doped region later forms the fourth doping region 90 and the n ⁺⁺ doped region forms the further doping region 70 ,

The semiconductor material 20 is now p ⁺ -doped by ion implantation ( 2 ). For the finished trench transistor 1 This results in the advantage that a significantly higher Bodydotierung within the Mesa region than previously possible, without affecting the threshold voltage of the transistor. In other words, the Mesalotung or Mesadotierung in the finished trench transistor 1 be determined independently of the channel charge or channel doping. The Mesagebiet can thus be highly doped, resulting in improved robustness of the finished trench transistor 1 results. In particular, avalanche obesity can be improved. In the Avalancherobustheit the trench transistor 1 is operated in the breakthrough, whereby a large power loss arises. Due to the possible high doping of the Mesagebiets and independent of the defined channel doping by the invention can thereby destroy the device or the trench transistor 1 be prevented. Thus, no bipolar transistor is ignited.

The result of the p ⁺ doping is p ⁺ -doped semiconductor material 20 , this in 2 is shown.

Subsequently, the trench 30 in the semiconductor material 20 formed by etching. That is, for example, a mask is used, and the trench 30 is formed at the locations of the mask having corresponding recesses. The in the semiconductor material 20 trained trench 30 has the trench sidewalls 30w and the trench floor area 30b on.

Subsequently, a thick oxide layer becomes DOX conform on the semiconductor surface 20a , on the trench side walls 30w and in the trench floor area 30b deposited. That is, the thick oxide layer DOX covers the semiconductor surface 20a , the trench sidewalls 30w and the trench floor area 30b each with an equally thick layer of insulation material from ( 4 ).

Subsequently, the lined with the thick oxide layer DOX trench 30 at least partially with a filling 40 filled from a further semiconductor material. For this purpose, a layer 40s the further semiconductor material, for. B. polysilicon POLY deposited over the semiconductor device. That is, the layer 40s polysilicon POLY covers the semiconductor surface covered with the thick oxide layer DOX 20a and fills the trench lined with the thick oxide layer DOX 30 completely off, like this in 5 is shown.

Subsequently, the layer 40s made of polysilicon POLY re-formed by etching. The semiconductor surface covered with the thick oxide layer DOX 20a is completely absorbed by the layer 40s polysilicon POLY free. Furthermore, the etching is performed so long that polysilicon POLY the trench lined with the thick oxide layer DOX 30 only partially filled. Thus, the results in 6 shown filling 40 , The filling 40 fills the trench lined with the thick oxide layer DOX 30 at most in part, creating a lower trench area 30u and an upper trench area 30o To be defined. In the lower trench area 30u are the trench sidewalls 30w and the trench floor area 30b lined with the thick oxide layer DOX, and in this lined lower trench area 30u there is the filling 40 , The upper trench area 30o is at the corresponding areas of the trench sidewalls 30w lined with the thick oxide layer DOX, but not with the filling 40 filled.

In the following process step (a), the thick oxide layer DOX on the semiconductor surface 20a and in the upper trench area 30o removed by etching. The result of method step (a) is in 7 shown.

Subsequently, in a further method step (b), the semiconductor material 20 on the semiconductor surface 20a and in the upper trench area 30o etched. In 8th is the shape of the semiconductor material 20 along the semiconductor surface 20a and in the upper trench area 30o shown with a dashed line and the shape after the etching back with a solid line. By the etching process is also the filling 40 regressed, so that the above-mentioned first field electrode part 40o is formed.

During the etching process in method step (b), the thick oxide layer DOX acts as a mask and prevents the reformation of the semiconductor material 20 in the lower trench area 30u , The semiconductor material 20 when etching on the trench sidewalls 30w but towards the trench bottom area 30b regressed by a distance HO. The distance HO is thus the distance of the upper edge or surface of the thick oxide layer DOX and a surface Kw formed by the etching. The surface Kw is also referred to below as the bottom region of the channel K. The surface Kw forms a kind of stage in the semiconductor material 20 , The area between the area Kw and the demolded semiconductor surface 20a forms in the finished trench transistor 1 essentially the channel K.

The bottom area Kw of the channel K has a distance HS from the trench bottom area 30b ,

This is followed by a method step (c), in which the original shape of the semiconductor material 20 that is, the shape before re-etching the semiconductor material 20 is restored in process step (b). For this purpose, new semiconductor material 20n with defined doping p at the recessed trench sidewalls 30w in the area of the upper trench area 30o and on the demolded semiconductor surface 20a of the semiconductor material region 20 applied by epitaxy.

New semiconductor material 20n is also on the first field electrode part 40o applied, whereby the second or grown field electrode part 40n is formed. The application of the new semiconductor material 20n on the first field electrode part 40o is not mandatory. That is, in step (c) new semiconductor material 20n with defined doping p only at the recessed trench sidewalls 30b in the area of the upper trench area 30o and on the demolded semiconductor surface 20a of the semiconductor material region 20 be applied by epitaxy. In this case, the surface of the filling lies 40 lower than in the figures. In particular, the surface of the filling 40 lower than the thick oxide layer DOX on the trench sidewalls 30w ,

The reformation of the semiconductor material 20 in process step (b) and the regrowth of the reformed semiconductor material 20 with a defined and local doping p allows the formation of the channel K of the trench transistor with a well-defined doping without affecting the other dopants. As a result, as described above, the robustness of the component or the trench transistor 1 be improved.

The channel region K thus lies on the trench side walls 30w in the upper trench area 30o , The bottom area Kw of the channel K thus has the same distance HS from the trench bottom area 30b like the area Kw or step formed in process step (b) (see above).

This is followed by a method step (d), in which a fine adjustment is carried out. At this time, the thick oxide layer DOX becomes along the trench sidewalls 30w towards the trench floor area 30b etched back to a depth HO. The depth HO is approximately equal to the distance HO of the surface or upper edge of the thick oxide layer DOX from the bottom region Kw of the channel in method step (b).

It is therefore ensured in method step (d) that the surface of the thick oxide layer DOX is at approximately the same height as the bottom region Kw of the channel. Thus, the bottom area Kw of the channel K and the surface of the thick oxide layer DOX have substantially the same distance HS from the door chbodenbereich 30b ,

Due to the etching back of the thick oxide layer DOX, the filling protrudes 40 something about the thick oxide layer DOX out. The protruding area of the filling 40 has approximately a length corresponding to the distance HO. Due to variations in the etching process, the protruding portion of the filling may 40 but also be slightly larger or smaller than the distance HO. However, it is always ensured in method step (d) that the surface of the thick oxide layer DOX is at the same height as the bottom region Kw of the channel K, measured from the trench bottom region 30b , lies.

In order to achieve this in practice particularly simply, the necessary etching time is calculated from the etching duration in method step (b). That is, in step (b), the semiconductor material becomes 20 Recessed by a certain depth, ie a certain amount per unit area, and the regression of the thick oxide layer DOX in process step (d) takes place as a function of the determined depth of process step (b).

It is possible, too, the etching time in method step (d) on the basis of parameters of epitaxy in the method step (c) to determine.

Subsequently, the gate oxide layer GOX for insulating the gate electrode G (see 11 ) educated. For this purpose, a gate oxide layer GOX-S conformally deposited via the semiconductor device. The semiconductor device consists of the semiconductor material 20 and the trench transistor 1 , That is, the gate oxide film GOX-S covers the semiconductor surface 20a and clothe the upper trench area 30o completely off. That is, in the trench 30 are in the upper trench area 30o the trench side walls 30w , the surface of the thick oxide DOX layer and the protruding portion of the filling 40 completely covered with the gate oxide layer GOX-S.

In the following method step, the gate oxide layer GOX-S on the semiconductor surface 20a etched away. 12 shows the result after the etch back of the gate oxide layer GOX-S on the semiconductor surface 20a , There is only one more gate oxide layer GOX in the upper trench area 30o left over, the the trench sidewalls 30w in the upper trench area 30o , the surface of the thick oxide layer DOX and the exposed surfaces 40w the outstanding part of the filling 40 covered.

In the following process step for the production of the trench transistor 1 will now be in the upper lined trench area 30o the gate oxide layer GOX the further filling 50 formed of a further semiconductor material. But it can also be the same semiconductor material as for the filling 40 or the field electrode F are used, for example polysilicon POLY. Further possible materials are, for example, titanium silicon, tungsten and copper.

In a further method step, the semiconductor material is now 20 from the semiconductor surface 20a from n ⁺⁺ -doped. This becomes the doping region 60 with n ⁺⁺ -dot in 14 educated. The doping region 60 with n ⁺⁺ doping can advantageously be used as source S or for example for connecting the source S.

Furthermore, in the bottom U of the semiconductor material 20 adjacent area another doping area 70 formed with n ⁺ doping. For this purpose, an ion implantation takes place on the underside U of the semiconductor material 20 , The further doping region 70 with n ⁺ doping can advantageously be used as drain D or for example for connecting the drain region D or the drain of the trench transistor 1 be used.

These and other objects of the invention will become apparent from the following further explained.

For use in DC / DC converters, power transistors with low turn-on resistance R _on and low gate-drain capacitance C _{GD are} required. Currently, the low on-resistance is achieved by the field plate principle. In order to reduce the gate-drain capacitance, the gate electrode G may be replaced with a field electrode F which is at source potential or another defined potential and a gate electrode G 'with a very small overlap region with the drain region.

In this arrangement, the position of the lower edge U of the gate electrode G 'has to be adapted very precisely to the position of the body epi-pn junction: if the position of U is too low, the gate-drain overlap and therefore C _{GD become} intolerably large If U is too flat, the channel will only be formed at V _G > V _th, or in extreme cases at all, so that R _{on is increased,} especially at low V _G.

The present invention solves the problem, inter alia, by utilizing a self-aligned method. The channel is defined after the field plate etching via local epitaxy. Thus, the gate-drain overlap can be minimized. An additional advantage of this solution is that this concept allows a much higher body doping within the mesa area without affecting the threshold voltage of the transistor. This benefits the avalanche robustness of the device. The channel can be made shorter, resulting in a reduction of R _on . Furthermore, the G / S overlap is reduced by the partial removal of the poly-S plug.

• (1) selbstjustierter Gate/Drain-Überlapp über lokale Epitaxie → Minimierung der Gate-Drain-Kapazität CGD, Gate-Source Kapazität CGS;
• (2) Modifikation bzw. Optimierung des Bodyprofils durch Ausnutzung zweier separater Prozessschritte (Body Implantation vor der Trenchätzung, Kanal über Epitaxie).

An object of the invention essentially comprises two points:

• (1) self-aligned gate / drain over local epitaxy → minimization of gate-drain capacitance CGD, gate-source capacitance CGS;
• (2) modification or optimization of the body profile by utilizing two separate process steps (body implantation before trench etching, channel via epitaxy).

• • Body-Implantation (und evtl. Diffusion);
• • Trench mit Feldplatte ausbilden;
• • Nach der Feldplattenätzung – isotrope Si-Rückätzung (dabei teilweise Entfernung des POLY-S-Stöpsels);
• • Epitaktisches Aufwachsen der Kanaldotierschicht;
• • Gateoxidation;
• • Ausbilden des GatePOLY;
• • Rückätzen des GatePOLY;
• • Zwischenoxid aufbringen (Interlayer Dielektric – ILD);
• • Source-Metallisierung.

Process flow for the production of self-aligned gate-drain overlap:

• • Body implantation (and possibly diffusion);
• • form trench with field plate;
• • After field plate etching - isotropic Si etchback (with partial removal of the POLY-S plug);
• Epitaxial growth of the channel dopant layer;
• • gate oxidation;
• Forming the GatePOLY;
• • back etching of the GatePOLY;
• • Apply intermediate oxide (Interlayer Dielectric - ILD);
• • Source metallization.

at a further embodiment the isotropic etchback is omitted. The advantage here is that in the upper area more space for contacting to disposal is as in the prior art and therefore a smaller cell grid can be realized. The smaller space requirement arises in particular since that new semiconductor material, formed by epitaxy will grow up in the existing field or material.

The epitaxially grown p-channel doping is substantially less endowed as the body area, at least lower than the maximum Bodydotierung directly next to the canal area.

The channel area extends deeper than the body area. would the body, that is the area that is in 14 With 81 range below the channel region, the threshold voltage would increase and there would be a deterioration of the transistor parameters. However, since the distance H-80 of the lower surface 80u of the third impurity region of the trench bottom region is greater than the distance HS (see 14 ), these disadvantages do not arise.

1

trench transistor

20

Semiconductor material

20a

Semiconductor surface, semiconductor surface area

20 n

grown Semiconductor material

20u

to bottom facing side surface of the grown up

Semiconductor material 20n on the trench side walls 30w

30

trench, dig

30b

Trench bottom area

30o

upper trench area

30u

lower trench area

30w

Trench sidewall

40

filling

40n

second or grown field electrode part

40o

first Field electrode part

50

Further filling

60

Doping region with n ⁺⁺ doping

70

further doping region with n ⁺⁺ doping

80

third doping region

80u

lower surface of the third doping region 80

81

distance the lower surface of the third

dopant region 80 from the surface area 20a

90

fourth doping region

D

Drain or drain region of the trench transistor 1

DOX

thick oxide layer, first shift

F

field electrode

FOX

field plate

G

gate electrode

GOX

gate oxide layer

H-80

Distance of the lower surface 80u of the third

dopant region from the trench floor area

K

Channel region channel

kw

floor area Kw of the canal

POLY

polysilicon

U

Semiconductor side

Claims (21)

Method for producing a trench transistor ( 1 ), - in which in a semiconductor material ( 20 ) having a semiconductor surface area ( 20a ) at least one trench ( 30 ), wherein the trench side walls ( 30w ) and the trench floor area ( 30b ) are each covered or lined with a first layer (DOX) of a first insulating material, - in which in the first layer (DOX) lined trench ( 30 ) a filling ( 40 ) is formed with a filling material (POLY) which seals the trench (12) lined with the first layer (DOX). 30 ) only partially filled and so an upper trench area ( 30o ) and a lower trench area ( 30u ), wherein in the upper trench region ( 30o ) the trench sidewalls ( 30w ) and in the lower trench area ( 30u ) the trench sidewalls ( 30w ) and the trench floor area ( 30b ) are lined with the first layer (DOX) and the lower trench region ( 30u ) with the filling ( 40 ), characterized by the following process steps: (a) reformation of the first layer (DOX) in the upper trench region ( 30o ), the filling ( 40 ) serves as a mask and the regression of the first layer (DOX) in the lower trench region ( 30u ), so that it is retained there, and (b) recovering the semiconductor material ( 20 ) at the trench sidewalls ( 30w ) in the upper trench area ( 30o ), wherein the first layer (DOX) serves as a mask and the regression of the semiconductor material ( 20 ) in the lower trench area ( 30u ) substantially completely prevents (c) forming a new semiconductor material ( 20n ) with defined doping (p) at the recessed trench sidewalls ( 30w ) in the region of the upper trench region ( 30o ), so that a channel region (K) with a defined doping (p) in the semiconductor material ( 20 ), wherein the first layer (DOX) serves as a mask, so that the new semiconductor material ( 20n ) with defined doping (p) at the recessed trench sidewalls ( 30w ) in the upper trench area ( 30o ) or on the filling ( 40 ) is applied. A method according to claim 1, characterized in that - the channel region (K) at a distance HS from the trench bottom region ( 30b ) is formed and - that then in a process step (d) the first layer (DOX) is reformed, wherein the filling ( 40 ) serves as a mask, so that the first layer (DOX) only along the trench side walls ( 30w ) and in the direction of the trench bottom area ( 30b ) such that the first layer (DOX) separates the trench ( 30 ) at the trench sidewalls ( 30w ) only to a height which is approximately equal to the distance HS of the channel region (S) from the trench bottom region (FIG. 30b ). Method according to one of the preceding claims, characterized in that semiconductor material ( 20 ) in process step (b) on the trench sidewalls ( 20w ) in the upper trench area ( 30o ) towards the trench bottom area ( 30b ) to about the distance HS from the trench bottom area ( 30b ) and thus the distance HS of the channel region (K) from the trench bottom region ( 30b ) is defined. Method according to one of claims 2 or 3, characterized in that - the semiconductor material ( 20 ) is reduced by a certain depth in method step (b), and - that the regression of the first layer (DOX) in method step (d) takes place as a function of the determined depth of method step (b). Method according to one of claims 2 to 4, characterized in that - the semiconductor material ( 20 ) in process step (b) on the trench sidewalls ( 30w ) in the upper trench area ( 30o ) towards the trench bottom area ( 30b ) is regressed by a distance H0 from the surface of the first layer (DOX), and - the first layer (DOX) is reduced by approximately the same distance H0 in process step (d). Method according to one of the preceding claims, characterized in that in process step (c) the new semiconductor material ( 20n ) is formed with defined doping (p) in such a way that it has the semiconductor material which has been reformed in process step (b) ( 20 ) replaced. Method according to one of the preceding claims, characterized in that in step (b) also the filling ( 40 ) is regressed. Method according to claim 7, characterized in that in process step (c) the new semiconductor material ( 20n ) with defined doping (p) also on the reformed filling ( 40 ) is formed. Method according to one of the preceding claims, characterized in that in the semiconductor material ( 20 ) before the formation of the at least one trench ( 30 ) a defined doping (p ⁺ ) is formed by implantation, in particular for a body region (B). Method according to one of the preceding claims, characterized in that the first layer (DOX) is a thick oxide layer, in particular of silicon dioxide, which before the process step (a) and after the formation of the trenches ( 30 ) compliant on the semiconductor surface area ( 20a ) at the trench sidewalls ( 30w ) and on the trench floor area ( 30b ) is formed in particular by means of deposition, CVD, PVD, sputtering, growing and / or converting an existing material region. Method according to one of the preceding claims, characterized in that the filling ( 40 ) is formed by: - forming a filling layer ( 40s ) covering the first layer (DOX) lined trench (FIG. 30 ) and / or the semiconductor surface covered with the first layer (DOX) ( 20a ), and - recovering the filling layer ( 40s ) such that the filling layer ( 40s ) on the semiconductor surface covered with the first layer (DOX) ( 20a ) is completely removed and the first layer (DOX) lined trench ( 30 ) remains only partially filled. Method according to one of claims 2 to 11, characterized that rebuilding in process step (a), in process step (b) and in the process step (d) by etching, especially wet-chemically or by means of plasma. Method according to one of the preceding claims, characterized in that the new semiconductor material ( 20n ) is formed with defined doping (p) in method step (c) by means of epitaxy, wherein in particular a fixed time is used to control the epitaxy. Method according to one of claims 2 to 13, characterized in that after the method step (d) at the trench side walls ( 30w ) in the upper trench area ( 30o ), on the first layer (DOX) and / or along the exposed surfaces ( 40w ) of the filling ( 40 ) an insulating layer (GOX) is formed, in particular by: - conforming deposition of an insulating layer of an insulating material over the semiconductor surface ( 20a ), on the trench sidewalls ( 30w ) in the upper trench area ( 30o ) on the first layer (DOX) and along the exposed surfaces ( 40w ) of the filling ( 40 ) and - back etching of the insulating layer on the semiconductor surface ( 20a ). A method according to claim 14, characterized in that after the formation of the insulating layer (GOX) another filling ( 50 ), in particular of a semiconductor material, is formed, the upper trench region ( 30o ) substantially fills, in particular for forming a gate electrode (G) of the trench transistor ( 1 ). Method according to one of the preceding claims, characterized in that in the semiconductor material ( 20 ) from the surface area ( 20a ) in the semiconductor material ( 20 ) doping region ( 60 ) is formed, in particular by implantation with a second defined doping (n ⁺⁺ ), in particular for forming or for connecting a source region (S). Method according to one of the preceding claims, characterized in that in the semiconductor material ( 20 ) from the underside (U) of the semiconductor material ( 20 ) in the semiconductor material protruding further doping region ( 70 ) is formed with a third defined doping (n ⁺ ), in particular for forming or for connecting a drain region (D) of the trench transistor ( 1 ). Method according to one of the preceding claims, characterized in that the trench transistor ( 1 ) is formed as a p-channel transistor and in step (c) silicon germanium is used as semiconductor material with a defined doping (p). Method according to one of claims 1 to 17, characterized in that the trench transistor ( 1 ) is formed as a p-channel transistor and in step (c) tes silicon as a semiconductor material ( 20 ) with defined doping (p) is used. Method according to one of claims 15 to 19, characterized in that - the filling ( 40 ) as a field electrode (F), - the first layer (DOX) as a field plate, - the further filling ( 50 ) as the gate electrode (G) and / or - the insulation layer (GOX) as the gate oxide layer of the trench transistor ( 1 ) be formed. Method according to one of the preceding claims, characterized characterized in that through the channel region the threshold voltage the trench transistor independently is adjusted by the breakdown voltage, in particular in self-adjusting way.