DE102004020260A1 - System zum temporären Modifizieren eines Ausgangssignalsverlaufs - Google Patents

System zum temporären Modifizieren eines Ausgangssignalsverlaufs Download PDF

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Publication number
DE102004020260A1
DE102004020260A1 DE102004020260A DE102004020260A DE102004020260A1 DE 102004020260 A1 DE102004020260 A1 DE 102004020260A1 DE 102004020260 A DE102004020260 A DE 102004020260A DE 102004020260 A DE102004020260 A DE 102004020260A DE 102004020260 A1 DE102004020260 A1 DE 102004020260A1
Authority
DE
Germany
Prior art keywords
mode
output
output waveform
temporarily
waveform
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE102004020260A
Other languages
English (en)
Inventor
Samuel D Naffziger
Eric S Fetzer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Publication of DE102004020260A1 publication Critical patent/DE102004020260A1/de
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/06—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31928—Formatter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Control Of Eletrric Generators (AREA)

Abstract

Es sind Systeme und Verfahren zum Liefern eines temporär modifizierten Ausgangs offenbart. Eine Signalverlaufsteuerung liefert einen Steuerausgang, der sich temporär auf einen Zwischenpegel zwischen einem normal hohen und einem niedrigen Pegel während eines ersten Betriebsmodus einstellt. Die Signalverlaufsteuerung liefert den Steuerausgang, um periodisch zwischen dem hohen und dem niedrigen Pegel während eines zweiten Betriebsmodus überzugehen. Ein Verzögerungsnetzwerk steuert die Signalverlaufsteuerung, um den Ausgang bei dem Zwischenpegel für eine Dauer während des ersten Betriebsmodus zu liefern.
DE102004020260A 2003-08-22 2004-04-26 System zum temporären Modifizieren eines Ausgangssignalsverlaufs Withdrawn DE102004020260A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/646,936 US7199611B2 (en) 2003-08-22 2003-08-22 System to temporarily modify an output waveform

Publications (1)

Publication Number Publication Date
DE102004020260A1 true DE102004020260A1 (de) 2005-05-04

Family

ID=34194610

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102004020260A Withdrawn DE102004020260A1 (de) 2003-08-22 2004-04-26 System zum temporären Modifizieren eines Ausgangssignalsverlaufs

Country Status (2)

Country Link
US (1) US7199611B2 (de)
DE (1) DE102004020260A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009302883A (ja) * 2008-06-13 2009-12-24 Sanyo Electric Co Ltd ３値入力回路

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5838015B2 (ja) * 1976-08-07 1983-08-19 株式会社日立製作所 デ−タ通信方式
US4303945A (en) * 1977-03-21 1981-12-01 Westinghouse Electric Corp. Image motion compensation for a TV sensor system
US5181133A (en) * 1991-05-15 1993-01-19 Stereographics Corporation Drive method for twisted nematic liquid crystal shutters for stereoscopic and other applications
US5296756A (en) * 1993-02-08 1994-03-22 Patel Hitesh N Self adjusting CMOS transmission line driver
US5440243A (en) 1993-09-21 1995-08-08 Apple Computer, Inc. Apparatus and method for allowing a dynamic logic gate to operation statically using subthreshold conduction precharging
US5485977A (en) * 1994-09-26 1996-01-23 Union Switch & Signal Inc. Reduced harmonic switching mode apparatus and method for railroad vehicle signaling
US6075386A (en) * 1997-10-22 2000-06-13 Hewlett-Packard Company Dynamic logic gate with relaxed timing requirements and output state holding
US6127858A (en) 1998-04-30 2000-10-03 Intel Corporation Method and apparatus for varying a clock frequency on a phase by phase basis
US5949723A (en) * 1998-07-28 1999-09-07 International Business Machines Corporation Fast single ended sensing with configurable half-latch
US6097207A (en) * 1998-08-21 2000-08-01 International Business Machines Corporation Robust domino circuit design for high stress conditions
US6339835B1 (en) * 1999-06-10 2002-01-15 International Business Machines Corporation Pseudo-anding in dynamic logic circuits
US6529045B2 (en) * 1999-09-28 2003-03-04 Intel Corporation NMOS precharge domino logic
US6281710B1 (en) * 1999-12-17 2001-08-28 Hewlett-Packard Company Selective latch for a domino logic gate
US6518796B1 (en) * 2000-06-30 2003-02-11 Intel Corporation Dynamic CMOS circuits with individually adjustable noise immunity
US6781416B1 (en) * 2001-12-19 2004-08-24 Rambus Inc. Push-pull output driver
US6830550B2 (en) * 2002-06-25 2004-12-14 James Lee Hedgecock Stair step voltage actuated measurement method and apparatus

Also Published As

Publication number Publication date
US20050040870A1 (en) 2005-02-24
US7199611B2 (en) 2007-04-03

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OP8 Request for examination as to paragraph 44 patent law
8139 Disposal/non-payment of the annual fee